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bsp/altera-cyclone-v: Move hwlib to bsps

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This patch is a part of the BSP source reorganization.

Update #3285.
This commit is contained in:
Sebastian Huber
2018-04-22 15:05:47 +02:00
parent adb85dd473
commit f004ace828
12 changed files with 10 additions and 47 deletions
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57
c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am
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@@ -12,27 +12,6 @@ include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = ../../../../../../bsps/arm/altera-cyclone-v/start/bsp_specs
###############################################################################
# Header #
###############################################################################
# Altera hwlib
#The following Altera hwlib header files have been left out because so far
#they are not required:
#include_bsp_HEADERS += hwlib/include/alt_bridge_manager.h
#include_bsp_HEADERS += hwlib/include/alt_fpga_manager.h
#include_bsp_HEADERS += hwlib/include/alt_globaltmr.h
#include_bsp_HEADERS += hwlib/include/alt_system_manager.h
#include_bsp_HEADERS += hwlib/include/alt_timers.h
#include_bsp_HEADERS += hwlib/include/alt_watchdog.h
#The following Altera hwlib headers would be problematic with RTEMS:
#include_bsp_HEADERS += hwlib/include/alt_interrupt.h
# Some of the headers from hwlib need the files from socal. Install them.
###############################################################################
# Data #
###############################################################################
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
@@ -42,41 +21,25 @@ dist_project_lib_DATA += ../../../../../../bsps/arm/altera-cyclone-v/start/linkc
dist_project_lib_DATA += ../../../../../../bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit
dist_project_lib_DATA += ../../../../../../bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit_smp
###############################################################################
# LibBSP #
###############################################################################
project_lib_LIBRARIES = librtemsbsp.a
librtemsbsp_a_SOURCES =
librtemsbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
# for the Altera hwlib
librtemsbsp_a_CPPFLAGS += -I${srcdir}/hwlib/include
librtemsbsp_a_CPPFLAGS += -std=gnu99
librtemsbsp_a_CPPFLAGS += -I$(RTEMS_SOURCE_ROOT)/bsps/arm/altera-cyclone-v/contrib/hwlib/include
CFLAGS += -Wno-missing-prototypes
# hwlib from Altera
librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_16550_uart.c
librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_address_space.c
librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_clock_manager.c
librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma.c
librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma_program.c
librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_generalpurpose_io.c
librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_i2c.c
librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_qspi.c
librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_reset_manager.c
#The following Altera hwlib source files have been left out because so far
#they are not required:
#librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_bridge_manager.c
#librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_fpga_manager.c
#librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_globaltmr.c
#librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_system_manager.c
#librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_timers.c
#librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_watchdog.c
# The following Altera hwlib source files would be problematic with RTEMS:
#librtemsbsp_a_SOURCES += hwlib/src/hwmgr/alt_interrupt.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_16550_uart.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_address_space.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_clock_manager.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_dma.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_dma_program.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_generalpurpose_io.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_i2c.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_qspi.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_reset_manager.c
# Shared
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/getentropy/getentropy-cpucounter.c

19
c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt
View File

@@ -1,19 +0,0 @@
HWLIB
=====
Hwlib is a collection of sources provided by Altera for the Cyclone-V.
As hwlib is third party software, please keep modifications and additions
to the sources to a minimum for easy maintenance. Otherwise updating to a
new version of hwlib released by Altera can become difficult.
The hwlib directory contains only those files from Alteras hwlib which are
required by the BSP (the whole hwlib was considered too big).
The directory structure within the hwlib directory is equivalent to Alteras
hwlib directory structure. For easy maintenance only whole files have been
left out.
Altera provides the hwlib with their SoC Embedded Design Suite (EDS).
HWLIB Version:
--------------
All files are from hwlib 13.1 distributed with SoC EDS 14.0.0.200.

1535
c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi.h
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File diff suppressed because it is too large Load Diff

1179
c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_16550_uart.c
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File diff suppressed because it is too large Load Diff

509
c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c
View File

@@ -1,509 +0,0 @@
/******************************************************************************
*
* alt_address_space.c - API for the Altera SoC FPGA address space.
*
******************************************************************************/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include <stddef.h>
#include <bsp/alt_address_space.h>
#include <bsp/socal/alt_l3.h>
#include <bsp/socal/socal.h>
#include <bsp/socal/alt_acpidmap.h>
#include <bsp/hwlib.h>
#define ALT_ACP_ID_MAX_INPUT_ID 7
#define ALT_ACP_ID_MAX_OUTPUT_ID 4096
/******************************************************************************/
ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_bridge_attr,
ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_bridge_attr)
{
uint32_t remap_reg_val = 0;
// Parameter checking and validation...
if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM)
{
remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_BOOTROM);
}
else if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM)
{
remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_OCRAM);
}
else
{
return ALT_E_INV_OPTION;
}
if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM)
{
remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_SDRAM);
}
else if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM)
{
remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_OCRAM);
}
else
{
return ALT_E_INV_OPTION;
}
if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_INACCESSIBLE)
{
remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_INVISIBLE);
}
else if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_ACCESSIBLE)
{
remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_VISIBLE);
}
else
{
return ALT_E_INV_OPTION;
}
if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_INACCESSIBLE)
{
remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_INVISIBLE);
}
else if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_ACCESSIBLE)
{
remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_VISIBLE);
}
else
{
return ALT_E_INV_OPTION;
}
// Perform the remap.
alt_write_word(ALT_L3_REMAP_ADDR, remap_reg_val);
return ALT_E_SUCCESS;
}
/******************************************************************************/
// Remap the MPU address space view of address 0 to access the SDRAM controller.
// This is done by setting the L2 cache address filtering register start address
// to 0 and leaving the address filtering address end address value
// unmodified. This causes all physical addresses in the range
// address_filter_start <= physical_address < address_filter_end to be directed
// to the to the AXI Master Port M1 which is connected to the SDRAM
// controller. All other addresses are directed to AXI Master Port M0 which
// connect the MPU subsystem to the L3 interconnect.
//
// It is unnecessary to modify the MPU remap options in the L3 remap register
// because those options only affect addresses in the MPU subsystem address
// ranges that are now redirected to the SDRAM controller and never reach the L3
// interconnect anyway.
ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void)
{
uint32_t addr_filt_end = (alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR) &
L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
return alt_l2_addr_filter_cfg_set(0x0, addr_filt_end);
}
/******************************************************************************/
// Return the L2 cache address filtering registers configuration settings in the
// user provided start and end address range out parameters.
ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
uint32_t* addr_filt_end)
{
if (addr_filt_start == NULL || addr_filt_end == NULL)
{
return ALT_E_BAD_ARG;
}
uint32_t addr_filt_start_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_START_ADDR);
uint32_t addr_filt_end_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR);
*addr_filt_start = (addr_filt_start_reg & L2_CACHE_ADDR_FILTERING_START_ADDR_MASK);
*addr_filt_end = (addr_filt_end_reg & L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
uint32_t addr_filt_end)
{
// Address filtering start and end values must be 1 MB aligned.
if ( (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK)
|| (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) )
{
return ALT_E_ARG_RANGE;
}
// While it is possible to set the address filtering end value above its
// reset value and thereby access a larger SDRAM address range, it is not
// recommended. Doing so would potentially obscure any mapped HPS to FPGA
// bridge address spaces and peripherals on the L3 interconnect.
if (addr_filt_end > L2_CACHE_ADDR_FILTERING_END_RESET)
{
return ALT_E_ARG_RANGE;
}
// NOTE: ARM (ARM DDI 0246F CoreLink Level 2 Cache Controller L2C-310 TRM)
// recommends programming the Address Filtering End Register before the
// Address Filtering Start Register to avoid unpredictable behavior between
// the two writes.
alt_write_word(L2_CACHE_ADDR_FILTERING_END_ADDR, addr_filt_end);
// It is recommended that address filtering always remain enabled.
addr_filt_start |= L2_CACHE_ADDR_FILTERING_ENABLE_MASK;
alt_write_word(L2_CACHE_ADDR_FILTERING_START_ADDR, addr_filt_start);
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
const uint32_t output_id,
const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t aruser)
{
if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR,
ALT_ACPIDMAP_VID2RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID2RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID2RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR,
ALT_ACPIDMAP_VID3RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID3RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID3RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR,
ALT_ACPIDMAP_VID4RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID4RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID4RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR,
ALT_ACPIDMAP_VID5RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID5RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID5RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR,
ALT_ACPIDMAP_VID6RD_MID_SET(input_id)
| ALT_ACPIDMAP_VID6RD_PAGE_SET(page)
| ALT_ACPIDMAP_VID6RD_USER_SET(aruser)
| ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL));
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
const uint32_t output_id,
const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t awuser)
{
if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR,
ALT_ACPIDMAP_VID2WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID2WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID2WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR,
ALT_ACPIDMAP_VID3WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID3WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID3WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR,
ALT_ACPIDMAP_VID4WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID4WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID4WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR,
ALT_ACPIDMAP_VID5WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID5WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID5WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR,
ALT_ACPIDMAP_VID6WR_MID_SET(input_id)
| ALT_ACPIDMAP_VID6WR_PAGE_SET(page)
| ALT_ACPIDMAP_VID6WR_USER_SET(awuser)
| ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL)
);
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
uint32_t aruser, page;
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
| ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
uint32_t awuser, page;
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
page = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
page = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
page = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
page = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
page = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
| ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t aruser)
{
alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
| ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
const uint32_t awuser)
{
alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
| ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
return ALT_E_SUCCESS;
}
/******************************************************************************/
ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
bool * fixed,
uint32_t * input_id,
ALT_ACP_ID_MAP_PAGE_t * page,
uint32_t * aruser)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
*aruser = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
*aruser = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
*aruser = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
*aruser = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
*aruser = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
*input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
*fixed = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_7:
*aruser = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
bool * fixed,
uint32_t * input_id,
ALT_ACP_ID_MAP_PAGE_t * page,
uint32_t * awuser)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
*awuser = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
*awuser = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
*awuser = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
*awuser = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
*awuser = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_7:
*awuser = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}

5554
c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c
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c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c
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c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma_program.c
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c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c
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@@ -1,777 +0,0 @@
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <bsp/socal/hps.h>
#include <bsp/socal/socal.h>
#include <bsp/socal/alt_gpio.h>
#include <bsp/socal/alt_rstmgr.h>
#include <bsp/hwlib.h>
#include <bsp/alt_generalpurpose_io.h>
/****************************************************************************************/
/******************************* Useful local definitions *******************************/
/****************************************************************************************/
#define ALT_GPIO_EOPA ALT_GPIO_1BIT_28
#define ALT_GPIO_EOPB ALT_GPIO_1BIT_57
#define ALT_GPIO_EOPC ALT_HLGPI_15
#define ALT_GPIO_BITMASK 0x1FFFFFFF
// expands the zero or one bit to the 29-bit GPIO word
#define ALT_GPIO_ALLORNONE(tst) ((uint32_t) ((tst == 0) ? 0 : ALT_GPIO_BITMASK))
/****************************************************************************************/
/* alt_gpio_init() initializes the GPIO modules */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_init(void)
{
// put GPIO modules into system manager reset if not already there
alt_gpio_uninit();
// release GPIO modules from system reset (w/ two-instruction delay)
alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK |
ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK |
ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, 0);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_uninit() uninitializes the GPIO modules */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_uninit(void)
{
// put all GPIO modules into system manager reset
alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK |
ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK |
ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK,
ALT_GPIO_BITMASK);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_datadir_set() sets the specified GPIO data bits to use the data */
/* direction(s) specified. 0 = input (default). 1 = output. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t config)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_SWPORTA_DDR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DDR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DDR_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_datadir_get() returns the data direction configuration of selected */
/* bits of the designated GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_SWPORTA_DDR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DDR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DDR_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
/****************************************************************************************/
/* alt_gpio_port_data_write() sets the GPIO data outputs of the specified GPIO module */
/* to a one or zero. Actual outputs are only set if the data direction for that bit(s) */
/* has previously been set to configure them as output(s). */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t val)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (val & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_SWPORTA_DR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DR_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DR_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, val);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_data_read() returns the value of the data inputs of the specified */
/* GPIO module. Data direction for these bits must have been previously set to inputs. */
/****************************************************************************************/
#if (!ALT_GPIO_DATAREAD_TEST_MODE)
/* This is the production code version. For software unit testing, set the */
/* ALT_GPIO_DATAREAD_TEST_MODE flag to true in the makefile, which will compile */
/* the GPIO test software version of alt_gpio_port_data_read() instead. */
uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_EXT_PORTA_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_EXT_PORTA_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_EXT_PORTA_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
#endif
/****************************************************************************************/
/* alt_gpio_port_int_type_set() sets selected signals of the specified GPIO port to */
/* be either level-sensitive ( =0) or edge-triggered ( =1). */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t config)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTTYPE_LEVEL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTTYPE_LEVEL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTTYPE_LEVEL_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_int_type_get() returns the interrupt configuration (edge-triggered or */
/* level-triggered) for the specified signals of the specified GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTTYPE_LEVEL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTTYPE_LEVEL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTTYPE_LEVEL_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
/****************************************************************************************/
/* alt_gpio_port_int_pol_set() sets the interrupt polarity of the signals of the */
/* specified GPIO register (when used as inputs) to active-high ( =0) or active-low */
/* ( =1). */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t config)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INT_POL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INT_POL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INT_POL_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_int_pol_get() returns the active-high or active-low polarity */
/* configuration for the possible interrupt sources of the specified GPIO module. */
/* 0 = The interrupt polarity for this bit is set to active-low mode. 1 = The */
/* interrupt polarity for this bit is set to active-highmode. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INT_POL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INT_POL_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INT_POL_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
/****************************************************************************************/
/* alt_gpio_port_debounce_set() sets the debounce configuration for input signals of */
/* the specified GPIO module. 0 - Debounce is not selected for this signal (default). */
/* 1 - Debounce is selected for this signal. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t config)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_DEBOUNCE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_DEBOUNCE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_DEBOUNCE_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, mask, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_debounce_get() returns the debounce configuration for the input */
/* signals of the specified GPIO register. 0 - Debounce is not selected for this */
/* signal. 1 - Debounce is selected for this signal. */
/****************************************************************************************/
uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_DEBOUNCE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_DEBOUNCE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_DEBOUNCE_ADDR; }
else { return 0; }
return alt_read_word(addr) & mask;
}
/****************************************************************************************/
/* alt_gpio_port_sync_set() sets the synchronization configuration for the signals of */
/* the specified GPIO register. This allows for synchronizing level-sensitive */
/* interrupts to the internal clock signal. This is a port-wide option that controls */
/* all level-sensitive interrupt signals of that GPIO port. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, uint32_t config)
{
volatile uint32_t *addr;
config = (config != 0) ? 1 : 0;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_LS_SYNC_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_LS_SYNC_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_LS_SYNC_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_write_word(addr, config);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_sync_get() returns the synchronization configuration for the signals */
/* of the specified GPIO register. This allows for synchronizing level-sensitive */
/* interrupts to the internal clock signal. This is a port-wide option that controls */
/* all level-sensitive interrupt signals of that GPIO port. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_LS_SYNC_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_LS_SYNC_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_LS_SYNC_ADDR; }
else { return ALT_E_BAD_ARG; } // error
return (alt_read_word(addr) != 0) ? ALT_E_TRUE : ALT_E_FALSE;
}
/****************************************************************************************/
/* alt_gpio_port_config() configures a group of GPIO signals with the same parameters. */
/* Allows for configuring all parameters of a given port at one time. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc,
uint32_t data)
{
ALT_STATUS_CODE ret;
// set all affected GPIO bits to inputs
ret = alt_gpio_port_datadir_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(ALT_GPIO_PIN_INPUT));
// the ALT_GPIO_ALLORNONE() macro expands the zero or one bit to the 29-bit GPIO word
// set trigger type
if (ret == ALT_E_SUCCESS)
{
ret = alt_gpio_port_int_type_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(type));
}
// set polarity
if (ret == ALT_E_SUCCESS)
{
alt_gpio_port_int_pol_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(pol));
}
// set debounce
if (ret == ALT_E_SUCCESS)
{
alt_gpio_port_debounce_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(debounc));
}
// set data output(s)
if (ret == ALT_E_SUCCESS)
{
alt_gpio_port_data_write(gpio_pid, mask, ALT_GPIO_ALLORNONE(data));
}
if (ret == ALT_E_SUCCESS)
{
// set data direction of one or more bits to select output
ret = alt_gpio_port_datadir_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(dir));
}
return ret;
}
/****************************************************************************************/
/* Enables the specified GPIO data register interrupts. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config)
{
volatile uint32_t *addr;
if (config & ~ALT_GPIO_BITMASK) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, config, UINT32_MAX);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* Disables the specified GPIO data module interrupts. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config)
{
volatile uint32_t *addr;
if (config & ~ALT_GPIO_BITMASK) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; }
else { return ALT_E_BAD_ARG; }
alt_replbits_word(addr, config, 0);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* Get the current state of the specified GPIO port interrupts enables. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; }
else { return 0; }
return alt_read_word(addr);
}
/****************************************************************************************/
/* Masks or unmasks selected interrupt source bits of the data register of the */
/* specified GPIO module. Uses a second bit mask to determine which signals may be */
/* changed by this call. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid,
uint32_t mask, uint32_t val)
{
volatile uint32_t *addr;
if ((mask & ~ALT_GPIO_BITMASK) || (val & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTMSK_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTMSK_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTMSK_ADDR; }
else { return ALT_E_BAD_ARG; } // argument error
alt_replbits_word(addr, mask, val);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* Returns the interrupt source mask of the specified GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTMSK_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTMSK_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTMSK_ADDR; }
else { return 0; } // error
return alt_read_word(addr);
}
/****************************************************************************************/
/* alt_gpio_port_int_status_get() returns the interrupt pending status of all signals */
/* of the specified GPIO register. */
/****************************************************************************************/
uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTSTAT_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTSTAT_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTSTAT_ADDR; }
else { return 0; } // error
return alt_read_word(addr);
}
/****************************************************************************************/
/* Clear the interrupt pending status of selected signals of the specified GPIO */
/* register. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid,
uint32_t clrmask)
{
volatile uint32_t *addr;
if (clrmask & ~ALT_GPIO_BITMASK) { return ALT_E_ERROR; }
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTSTAT_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTSTAT_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTSTAT_ADDR; }
else { return ALT_E_BAD_ARG; } // argument error
alt_write_word(addr, clrmask);
return ALT_E_SUCCESS;
}
/****************************************************************************************/
/* alt_gpio_port_idcode_get() returns the ID code of the specified GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_ID_CODE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_ID_CODE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_ID_CODE_ADDR; }
else { return 0; }
return alt_read_word(addr);
}
/****************************************************************************************/
/* alt_gpio_port_ver_get() returns the version code of the specified GPIO module. */
/****************************************************************************************/
uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid)
{
volatile uint32_t *addr;
if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_VER_ID_CODE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_VER_ID_CODE_ADDR; }
else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_VER_ID_CODE_ADDR; }
else { return 0; }
return alt_read_word(addr);
}
/****************************************************************************************/
/* alt_gpio_bit_config() configures one bit (signal) of the GPIO ports. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num,
ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce,
ALT_GPIO_PIN_DATA_t data)
{
ALT_GPIO_PORT_t pid;
uint32_t mask;
pid = alt_gpio_bit_to_pid(signal_num);
mask = 0x1 << alt_gpio_bit_to_port_pin(signal_num);
return alt_gpio_port_config(pid, mask, dir, type, pol, debounce, data);
}
/****************************************************************************************/
/* Returns the configuration parameters of a given GPIO bit. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num,
ALT_GPIO_CONFIG_RECORD_t *config)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
ALT_GPIO_PORT_t pid;
uint32_t mask, shift;
if ((config != NULL) && (signal_num != ALT_END_OF_GPIO_SIGNALS) && (signal_num <= ALT_LAST_VALID_GPIO_BIT))
{
pid = alt_gpio_bit_to_pid(signal_num);
shift = alt_gpio_bit_to_port_pin(signal_num);
if ((pid != ALT_GPIO_PORT_UNKNOWN) && (shift <= ALT_GPIO_BIT_MAX))
{
config->signal_number = signal_num;
mask = 0x00000001 << shift;
config->direction = (alt_gpio_port_datadir_get(pid, mask) == 0) ? ALT_GPIO_PIN_INPUT : ALT_GPIO_PIN_OUTPUT;
config->type = (alt_gpio_port_int_type_get(pid, mask) == 0) ? ALT_GPIO_PIN_LEVEL_TRIG_INT : ALT_GPIO_PIN_EDGE_TRIG_INT;
// save the following data whatever the state of config->direction
config->polarity = (alt_gpio_port_int_pol_get(pid, mask) == 0) ? ALT_GPIO_PIN_ACTIVE_LOW : ALT_GPIO_PIN_ACTIVE_HIGH;
config->debounce = (alt_gpio_port_debounce_get(pid, mask) == 0) ? ALT_GPIO_PIN_NODEBOUNCE : ALT_GPIO_PIN_DEBOUNCE;
config->data = (alt_gpio_port_data_read(pid, mask) == 0) ? ALT_GPIO_PIN_DATAZERO : ALT_GPIO_PIN_DATAONE;
ret = ALT_E_SUCCESS;
}
}
return ret;
}
/****************************************************************************************/
/* alt_gpio_group_config() configures a list of GPIO bits. The GPIO bits do not have */
/* to be configured the same, as was the case for the mask version of this function, */
/* alt_gpio_port_config(). Each bit may be configured differently and bits may be */
/* listed in any order. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, uint32_t len)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
if (config_array != NULL)
{
if (config_array->signal_number == ALT_END_OF_GPIO_SIGNALS) { ret = ALT_E_SUCCESS; }
// catches the condition where the pointers are good, but the
// first index is the escape character - which isn't an error
else
{
for (; (len-- > 0) && (config_array->signal_number != ALT_END_OF_GPIO_SIGNALS) && (config_array != NULL); config_array++)
{
ret = alt_gpio_bit_config(config_array->signal_number,
config_array->direction, config_array->type, config_array->polarity,
config_array->debounce, config_array->data);
if ((config_array->direction == ALT_GPIO_PIN_OUTPUT) && (ret == ALT_E_SUCCESS))
{
// if the pin is set to be an output, set it to the correct value
alt_gpio_port_data_write(alt_gpio_bit_to_pid(config_array->signal_number),
0x1 << alt_gpio_bit_to_port_pin(config_array->signal_number),
ALT_GPIO_ALLORNONE(config_array->data));
// ret should retain the value returned by alt_gpio_bit_config() above
// and should not be changed by the alt_gpio_port_data_write() call.
}
if (((ret != ALT_E_SUCCESS) && (config_array->signal_number <= ALT_LAST_VALID_GPIO_BIT))
|| ((ret == ALT_E_SUCCESS) && (config_array->signal_number > ALT_LAST_VALID_GPIO_BIT)))
{
ret = ALT_E_ERROR;
break;
}
}
}
}
return ret;
}
/****************************************************************************************/
/* Returns a list of the pin signal indices and the associated configuration settings */
/* (data direction, interrupt type, polarity, debounce, and synchronization) of that */
/* list of signals. Only the signal indices in the first field of each configuration */
/* record need be filled in. This function will fill in all the other fields of the */
/* configuration record, returning all configuration parameters in the array. A signal */
/* number index in the array equal to ALT_END_OF_GPIO_SIGNALS (-1) also terminates the */
/* function. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array,
uint32_t len)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
if ((config_array != NULL) && (config_array->signal_number == ALT_END_OF_GPIO_SIGNALS))
{
ret = ALT_E_SUCCESS;
}
else
{
for ( ; (len > 0) && (config_array != NULL) && (config_array->signal_number != ALT_END_OF_GPIO_SIGNALS)
&& (config_array->signal_number <= ALT_LAST_VALID_GPIO_BIT); len--)
{
ret = alt_gpio_bitconfig_get(config_array->signal_number, config_array);
config_array++;
if (ret != ALT_E_SUCCESS) { break; }
}
}
return ret;
}
/****************************************************************************************/
/* Another way to return a configuration list. The difference between this version and */
/* alt_gpio_group_config_get() is that this version follows a separate list of signal */
/* indices instead of having the signal list provided in the first field of the */
/* configuration records in the array. This function will fill in the fields of the */
/* configuration record, returning all configuration parameters in the array. A signal */
/* number index in the array equal to ALT_END_OF_GPIO_SIGNALS (-1) also terminates */
/* operation. */
/****************************************************************************************/
ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array,
ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len)
{
ALT_STATUS_CODE ret = ALT_E_ERROR;
if ((config_array != NULL) && (pinid_array != NULL) && (*pinid_array == ALT_END_OF_GPIO_SIGNALS))
{
ret = ALT_E_SUCCESS;
// catches the condition where the pointers are good, but the
// first index is the escape character - which isn't an error
}
else
{
for ( ;(len > 0) && (pinid_array != NULL) && (*pinid_array != ALT_END_OF_GPIO_SIGNALS) && (config_array != NULL); len--)
{
ret = alt_gpio_bitconfig_get(*pinid_array, config_array);
config_array++;
pinid_array++;
if (ret != ALT_E_SUCCESS) { break; }
}
}
return ret;
}
/****************************************************************************************/
/* A useful utility function. Extracts the GPIO port ID from the supplied GPIO Signal */
/* Index Number. */
/****************************************************************************************/
ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num)
{
ALT_GPIO_PORT_t pid = ALT_GPIO_PORT_UNKNOWN;
if (pin_num <= ALT_GPIO_EOPA) { pid = ALT_GPIO_PORTA; }
else if (pin_num <= ALT_GPIO_EOPB) { pid = ALT_GPIO_PORTB; }
else if (pin_num <= ALT_GPIO_EOPC) { pid = ALT_GPIO_PORTC; }
return pid;
}
/****************************************************************************************/
/* A useful utility function. Extracts the GPIO signal (pin) mask from the supplied */
/* GPIO Signal Index Number. */
/****************************************************************************************/
ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num)
{
if (pin_num <= ALT_GPIO_EOPA) {}
else if (pin_num <= ALT_GPIO_EOPB) { pin_num -= (ALT_GPIO_EOPA + 1); }
else if (pin_num <= ALT_GPIO_EOPC) { pin_num -= (ALT_GPIO_EOPB + 1); }
else { return ALT_END_OF_GPIO_PORT_SIGNALS; }
return (ALT_GPIO_PORTBIT_t) pin_num;
}
/****************************************************************************************/
/* A useful utility function. Extracts the GPIO Signal Index Number from the supplied */
/* GPIO port ID and signal mask. If passed a bitmask composed of more than one signal, */
/* the signal number of the lowest bitmask presented is returned. */
/****************************************************************************************/
ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid,
uint32_t bitmask)
{
uint32_t i;
for (i=0; i <= ALT_GPIO_BITNUM_MAX ;i++)
{
if (bitmask & 0x00000001)
{
if (pid == ALT_GPIO_PORTA) {}
else if (pid == ALT_GPIO_PORTB) { i += ALT_GPIO_EOPA + 1; }
else if (pid == ALT_GPIO_PORTC) { i += ALT_GPIO_EOPB + 1; }
else { return ALT_END_OF_GPIO_SIGNALS; }
return (ALT_GPIO_1BIT_t) i;
}
bitmask >>= 1;
}
return ALT_END_OF_GPIO_SIGNALS;
}

2004
c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_i2c.c
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2619
c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_qspi.c
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135
c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_reset_manager.c
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@@ -1,135 +0,0 @@
/******************************************************************************
*
* alt_reset_manager.c - API for the Altera SoC FPGA reset manager.
*
******************************************************************************/
/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
#include <bsp/alt_reset_manager.h>
#include <bsp/socal/socal.h>
#include <bsp/socal/hps.h>
#include <bsp/socal/alt_rstmgr.h>
/////
uint32_t alt_reset_event_get(void)
{
return alt_read_word(ALT_RSTMGR_STAT_ADDR);
}
ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask)
{
alt_write_word(ALT_RSTMGR_STAT_ADDR, event_mask);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_reset_cold_reset(void)
{
alt_write_word(ALT_RSTMGR_CTL_ADDR, ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
uint32_t nRST_pin_clk_assertion,
bool sdram_refresh_enable,
bool fpga_mgr_handshake,
bool scan_mgr_handshake,
bool fpga_handshake,
bool etr_stall)
{
// Cached register values
uint32_t ctrl_reg = ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK;
uint32_t counts_reg = 0;
/////
// Validate warm_reset_delay is above 16 and below the field width
if ((warm_reset_delay < 16) || (warm_reset_delay >= (1 << ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH)))
{
return ALT_E_BAD_ARG;
}
// Validate nRST_pin_clk_assertion delay is non-zero and below the field width
if (!nRST_pin_clk_assertion)
{
return ALT_E_ERROR;
}
if (nRST_pin_clk_assertion >= (1 << ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH))
{
return ALT_E_BAD_ARG;
}
// Update counts register with warm_reset_delay information
counts_reg |= ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(warm_reset_delay);
// Update counts register with nRST_pin_clk_assertion information
counts_reg |= ALT_RSTMGR_COUNTS_NRSTCNT_SET(nRST_pin_clk_assertion);
/////
// Update ctrl register with the specified option flags
if (sdram_refresh_enable)
{
ctrl_reg |= ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK;
}
if (fpga_mgr_handshake)
{
ctrl_reg |= ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK;
}
if (scan_mgr_handshake)
{
ctrl_reg |= ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK;
}
if (fpga_handshake)
{
ctrl_reg |= ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK;
}
if (etr_stall)
{
ctrl_reg |= ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK;
}
/////
// Commit registers to hardware
alt_write_word(ALT_RSTMGR_COUNTS_ADDR, counts_reg);
alt_write_word(ALT_RSTMGR_CTL_ADDR, ctrl_reg);
return ALT_E_SUCCESS;
}