From ed71774a5b17dee1e4c213a0378c5f7dd32cb186 Mon Sep 17 00:00:00 2001 From: Eric Norum Date: Fri, 28 Jan 2005 19:42:09 +0000 Subject: [PATCH] New BSP/CPU. --- c/src/lib/libcpu/m68k/ChangeLog | 5 + c/src/lib/libcpu/m68k/Makefile.am | 2 +- c/src/lib/libcpu/m68k/configure.ac | 2 + c/src/lib/libcpu/m68k/mcf5282/Makefile.am | 37 + .../libcpu/m68k/mcf5282/include/Makefile.am | 23 + .../lib/libcpu/m68k/mcf5282/include/mcf5282.h | 2399 +++++++++++++++++ 6 files changed, 2467 insertions(+), 1 deletion(-) create mode 100644 c/src/lib/libcpu/m68k/mcf5282/Makefile.am create mode 100644 c/src/lib/libcpu/m68k/mcf5282/include/Makefile.am create mode 100644 c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h diff --git a/c/src/lib/libcpu/m68k/ChangeLog b/c/src/lib/libcpu/m68k/ChangeLog index e58f89cef0..1f83196952 100644 --- a/c/src/lib/libcpu/m68k/ChangeLog +++ b/c/src/lib/libcpu/m68k/ChangeLog @@ -1,3 +1,8 @@ +2005-01-28 Eric Norum + + * Makefile.am, configure.ac, mcf5282/Makefile.am, + mcf5282/include/Makefile.am, mcf5282/include/mcf5282.h: New BSP/CPU + 2005-01-07 Ralf Corsepius * m68040/Makefile.am, mcf5206/Makefile.am, mcf5272/Makefile.am, diff --git a/c/src/lib/libcpu/m68k/Makefile.am b/c/src/lib/libcpu/m68k/Makefile.am index e496837ea7..556b22051f 100644 --- a/c/src/lib/libcpu/m68k/Makefile.am +++ b/c/src/lib/libcpu/m68k/Makefile.am @@ -4,7 +4,7 @@ ACLOCAL_AMFLAGS = -I ../../../aclocal -SUBDIRS = shared m68040 mcf5206 mcf5272 +SUBDIRS = shared m68040 mcf5206 mcf5272 mcf5282 include $(top_srcdir)/../../../automake/subdirs.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/m68k/configure.ac b/c/src/lib/libcpu/m68k/configure.ac index f837030474..53d92ea35c 100644 --- a/c/src/lib/libcpu/m68k/configure.ac +++ b/c/src/lib/libcpu/m68k/configure.ac @@ -41,6 +41,7 @@ AM_CONDITIONAL(mcpu32p, test "$RTEMS_CPU_MODEL" = "m68360" \ ) AM_CONDITIONAL(mcf5272, test "$RTEMS_CPU_MODEL" = "mcf5272" ) +AM_CONDITIONAL(mcf5282, test "$RTEMS_CPU_MODEL" = "mcf5282" ) # Explicitly list all Makefiles here AC_CONFIG_FILES([Makefile @@ -48,5 +49,6 @@ shared/Makefile m68040/Makefile mcf5206/Makefile mcf5272/Makefile +mcf5282/Makefile ]) AC_OUTPUT diff --git a/c/src/lib/libcpu/m68k/mcf5282/Makefile.am b/c/src/lib/libcpu/m68k/mcf5282/Makefile.am new file mode 100644 index 0000000000..78eacb81c7 --- /dev/null +++ b/c/src/lib/libcpu/m68k/mcf5282/Makefile.am @@ -0,0 +1,37 @@ +## +## $Id$ +## + +include $(top_srcdir)/../../../automake/compile.am + +CLEANFILES = +EXTRA_PROGRAMS = +noinst_DATA = + +if mcf5282 + +# include +include_mcf5282dir = $(includedir)/mcf5282 +include_mcf5282_HEADERS = include/mcf5282.h +endif + +all-local: $(PREINSTALL_FILES) + +PREINSTALL_DIRS = +PREINSTALL_FILES = + +if mcf5282 +$(PROJECT_INCLUDE)/mcf5282/$(dirstamp): + @$(mkdir_p) $(PROJECT_INCLUDE)/mcf5282 + @: > $(PROJECT_INCLUDE)/mcf5282/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf5282/$(dirstamp) + +$(PROJECT_INCLUDE)/mcf5282/mcf5282.h: include/mcf5282.h $(PROJECT_INCLUDE)/mcf5282/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5282/mcf5282.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5282/mcf5282.h +endif + +CLEANFILES += $(PREINSTALL_FILES) +DISTCLEANFILES = $(PREINSTALL_DIRS) + +include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/m68k/mcf5282/include/Makefile.am b/c/src/lib/libcpu/m68k/mcf5282/include/Makefile.am new file mode 100644 index 0000000000..7d7f007ae6 --- /dev/null +++ b/c/src/lib/libcpu/m68k/mcf5282/include/Makefile.am @@ -0,0 +1,23 @@ +## +## Makefile.am,v 1.3 2002/03/28 00:48:01 joel Exp +## + + +include_mcf5282dir = $(includedir)/mcf5282 + +include_mcf5282_HEADERS = mcf5282.h + +$(PROJECT_INCLUDE)/mcf5282: + $(mkinstalldirs) $@ + +$(PROJECT_INCLUDE)/mcf5282/%.h: %.h + $(INSTALL_DATA) $< $@ + +TMPINSTALL_FILES = $(PROJECT_INCLUDE)/mcf5282 \ + $(include_mcf5282_HEADERS:%=$(PROJECT_INCLUDE)/mcf5282/%) + +all-local: $(TMPINSTALL_FILES) + +EXTRA_DIST = $(include_mcf5282_HEADERS) + +include $(top_srcdir)/../../../../../../automake/local.am diff --git a/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h b/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h new file mode 100644 index 0000000000..508c67eb07 --- /dev/null +++ b/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h @@ -0,0 +1,2399 @@ +/* + ******************************************* + * Definitions from Motorola/FreeScale * + ******************************************* + */ + +/* + * File: mcf5282.h + * Purpose: MCF5282 definitions + * + * Notes: + */ + +#ifndef _CPU_MCF5282_H +#define _CPU_MCF5282_H + +/********************************************************************/ + +/* + * File: mcf5xxx.h + * Purpose: Definitions common to all ColdFire processors + * + * Notes: + */ + +#ifndef _CPU_MCF5XXX_H +#define _CPU_MCF5XXX_H + +/***********************************************************************/ +/* + * The basic data types + */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +typedef volatile uint8 vuint8; /* 8 bits */ +typedef volatile uint16 vuint16; /* 16 bits */ +typedef volatile uint32 vuint32; /* 32 bits */ + +/***********************************************************************/ +/* + * Common M68K & ColdFire definitions + */ + +#define ADDRESS uint32 +#define INSTRUCTION uint16 +#define ILLEGAL 0x4AFC +#define CPU_WORD_SIZE 16 + +#define MCF5XXX_SR_T (0x8000) +#define MCF5XXX_SR_S (0x2000) +#define MCF5XXX_SR_M (0x1000) +#define MCF5XXX_SR_IPL (0x0700) +#define MCF5XXX_SR_IPL_0 (0x0000) +#define MCF5XXX_SR_IPL_1 (0x0100) +#define MCF5XXX_SR_IPL_2 (0x0200) +#define MCF5XXX_SR_IPL_3 (0x0300) +#define MCF5XXX_SR_IPL_4 (0x0400) +#define MCF5XXX_SR_IPL_5 (0x0500) +#define MCF5XXX_SR_IPL_6 (0x0600) +#define MCF5XXX_SR_IPL_7 (0x0700) +#define MCF5XXX_SR_X (0x0010) +#define MCF5XXX_SR_N (0x0008) +#define MCF5XXX_SR_Z (0x0004) +#define MCF5XXX_SR_V (0x0002) +#define MCF5XXX_SR_C (0x0001) + +#define MCF5XXX_CACR_CENB (0x80000000) +#define MCF5XXX_CACR_CPDI (0x10000000) +#define MCF5XXX_CACR_CPD (0x10000000) +#define MCF5XXX_CACR_CFRZ (0x08000000) +#define MCF5XXX_CACR_CINV (0x01000000) +#define MCF5XXX_CACR_DIDI (0x00800000) +#define MCF5XXX_CACR_DISD (0x00400000) +#define MCF5XXX_CACR_INVI (0x00200000) +#define MCF5XXX_CACR_INVD (0x00100000) +#define MCF5XXX_CACR_CEIB (0x00000400) +#define MCF5XXX_CACR_DCM_WR (0x00000000) +#define MCF5XXX_CACR_DCM_CB (0x00000100) +#define MCF5XXX_CACR_DCM_IP (0x00000200) +#define MCF5XXX_CACR_DCM (0x00000200) +#define MCF5XXX_CACR_DCM_II (0x00000300) +#define MCF5XXX_CACR_DBWE (0x00000100) +#define MCF5XXX_CACR_DWP (0x00000020) +#define MCF5XXX_CACR_EUST (0x00000010) +#define MCF5XXX_CACR_CLNF_00 (0x00000000) +#define MCF5XXX_CACR_CLNF_01 (0x00000002) +#define MCF5XXX_CACR_CLNF_10 (0x00000004) +#define MCF5XXX_CACR_CLNF_11 (0x00000006) + +#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) +#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) +#define MCF5XXX_ACR_EN (0x00008000) +#define MCF5XXX_ACR_SM_USER (0x00000000) +#define MCF5XXX_ACR_SM_SUPER (0x00002000) +#define MCF5XXX_ACR_SM_IGNORE (0x00006000) +#define MCF5XXX_ACR_ENIB (0x00000080) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_DCM_WR (0x00000000) +#define MCF5XXX_ACR_DCM_CB (0x00000020) +#define MCF5XXX_ACR_DCM_IP (0x00000040) +#define MCF5XXX_ACR_DCM_II (0x00000060) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_BWE (0x00000020) +#define MCF5XXX_ACR_WP (0x00000004) + +#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) +#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) +#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) +#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) +#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) +#define MCF5XXX_RAMBAR_WP (0x00000100) +#define MCF5XXX_RAMBAR_CI (0x00000020) +#define MCF5XXX_RAMBAR_SC (0x00000010) +#define MCF5XXX_RAMBAR_SD (0x00000008) +#define MCF5XXX_RAMBAR_UC (0x00000004) +#define MCF5XXX_RAMBAR_UD (0x00000002) +#define MCF5XXX_RAMBAR_V (0x00000001) + +/***********************************************************************/ +/* + * The ColdFire family of processors has a simplified exception stack + * frame that looks like the following: + * + * 3322222222221111 111111 + * 1098765432109876 5432109876543210 + * 8 +----------------+----------------+ + * | Program Counter | + * 4 +----------------+----------------+ + * |FS/Fmt/Vector/FS| SR | + * SP --> 0 +----------------+----------------+ + * + * The stack self-aligns to a 4-byte boundary at an exception, with + * the FS/Fmt/Vector/FS field indicating the size of the adjustment + * (SP += 0,1,2,3 bytes). + */ + +#define MCF5XXX_RD_SF_FORMAT(PTR) \ + ((*((uint16 *)(PTR)) >> 12) & 0x00FF) + +#define MCF5XXX_RD_SF_VECTOR(PTR) \ + ((*((uint16 *)(PTR)) >> 2) & 0x00FF) + +#define MCF5XXX_RD_SF_FS(PTR) \ + ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) + +#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) +#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) + +/********************************************************************/ +/* + * Functions provided by mcf5xxx.s + */ + +int asm_set_ipl (uint32); +void mcf5xxx_wr_cacr (uint32); +void mcf5xxx_wr_acr0 (uint32); +void mcf5xxx_wr_acr1 (uint32); +void mcf5xxx_wr_acr2 (uint32); +void mcf5xxx_wr_acr3 (uint32); +void mcf5xxx_wr_other_a7 (uint32); +void mcf5xxx_wr_other_sp (uint32); +void mcf5xxx_wr_vbr (uint32); +void mcf5xxx_wr_macsr (uint32); +void mcf5xxx_wr_mask (uint32); +void mcf5xxx_wr_acc0 (uint32); +void mcf5xxx_wr_accext01 (uint32); +void mcf5xxx_wr_accext23 (uint32); +void mcf5xxx_wr_acc1 (uint32); +void mcf5xxx_wr_acc2 (uint32); +void mcf5xxx_wr_acc3 (uint32); +void mcf5xxx_wr_sr (uint32); +void mcf5xxx_wr_rambar0 (uint32); +void mcf5xxx_wr_rambar1 (uint32); +void mcf5xxx_wr_mbar (uint32); +void mcf5xxx_wr_mbar0 (uint32); +void mcf5xxx_wr_mbar1 (uint32); + +/********************************************************************/ + +#endif /* _CPU_MCF5XXX_H */ + + +/********************************************************************/ +/* + * Memory map definitions from linker command files + */ +extern uint8 __IPSBAR[]; + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_SCM_IPSBAR (*(vuint32 *)(void *)(&__IPSBAR[0x0000])) +#define MCF5282_SCM_RAMBAR (*(vuint32 *)(void *)(&__IPSBAR[0x0008])) +#define MCF5282_SCM_CRSR (*(vuint8 *)(void *)(&__IPSBAR[0x0010])) +#define MCF5282_SCM_CWCR (*(vuint8 *)(void *)(&__IPSBAR[0x0011])) +#define MCF5282_SCM_LPICR (*(vuint8 *)(void *)(&__IPSBAR[0x0012])) +#define MCF5282_SCM_CWSR (*(vuint8 *)(void *)(&__IPSBAR[0x0013])) +#define MCF5282_SCM_DMAREQC (*(vuint32 *)(void *)(&__IPSBAR[0x0014])) +#define MCF5282_SCM_MPARK (*(vuint32 *)(void *)(&__IPSBAR[0x001C])) +#define MCF5282_SCM_MPR (*(vuint8 *)(void *)(&__IPSBAR[0x0020])) +#define MCF5282_SCM_PACR0 (*(vuint8 *)(void *)(&__IPSBAR[0x0024])) +#define MCF5282_SCM_PACR1 (*(vuint8 *)(void *)(&__IPSBAR[0x0025])) +#define MCF5282_SCM_PACR2 (*(vuint8 *)(void *)(&__IPSBAR[0x0026])) +#define MCF5282_SCM_PACR3 (*(vuint8 *)(void *)(&__IPSBAR[0x0027])) +#define MCF5282_SCM_PACR4 (*(vuint8 *)(void *)(&__IPSBAR[0x0028])) +#define MCF5282_SCM_PACR5 (*(vuint8 *)(void *)(&__IPSBAR[0x002A])) +#define MCF5282_SCM_PACR6 (*(vuint8 *)(void *)(&__IPSBAR[0x002B])) +#define MCF5282_SCM_PACR7 (*(vuint8 *)(void *)(&__IPSBAR[0x002C])) +#define MCF5282_SCM_PACR8 (*(vuint8 *)(void *)(&__IPSBAR[0x002E])) +#define MCF5282_SCM_GPACR0 (*(vuint8 *)(void *)(&__IPSBAR[0x0030])) +#define MCF5282_SCM_GPACR1 (*(vuint8 *)(void *)(&__IPSBAR[0x0031])) + +/* Bit level definitions and macros */ +#define MCF5282_SCM_IPSBAR_BA(x) ((x)&0xC0000000) +#define MCF5282_SCM_IPSBAR_V (0x00000001) + +#define MCF5282_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) +#define MCF5282_SCM_RAMBAR_BDE (0x00000200) + +#define MCF5282_SCM_CRSR_EXT (0x80) +#define MCF5282_SCM_CRSR_CWDR (0x20) + +#define MCF5282_SCM_CWCR_CWE (0x80) +#define MCF5282_SCM_CWCR_CWRI (0x40) +#define MCF5282_SCM_CWCR_CWT(x) (((x)&0x03)<<3) +#define MCF5282_SCM_CWCR_CWTA (0x04) +#define MCF5282_SCM_CWCR_CWTAVAL (0x02) +#define MCF5282_SCM_CWCR_CWTIC (0x01) + +#define MCF5282_SCM_LPICR_ENBSTOP (0x80) +#define MCF5282_SCM_LPICR_XSTOP_IPL(x) (((x)&0x07)<<4) + +#define MCF5282_SCM_CWSR_SEQ1 (0x55) +#define MCF5282_SCM_CWSR_SEQ2 (0xAA) + +#define MCF5282_SCM_DMAREQC_DMAC3(x) (((x)&0x000F)<<12) +#define MCF5282_SCM_DMAREQC_DMAC2(x) (((x)&0x000F)<<8) +#define MCF5282_SCM_DMAREQC_DMAC1(x) (((x)&0x000F)<<4) +#define MCF5282_SCM_DMAREQC_DMAC0(x) (((x)&0x000F)) +#define MCF5282_SCM_DMAREQC_DMATIMER0 (0x4) +#define MCF5282_SCM_DMAREQC_DMATIMER1 (0x5) +#define MCF5282_SCM_DMAREQC_DMATIMER2 (0x6) +#define MCF5282_SCM_DMAREQC_DMATIMER3 (0x7) +#define MCF5282_SCM_DMAREQC_UART0 (0x8) +#define MCF5282_SCM_DMAREQC_UART1 (0x9) +#define MCF5282_SCM_DMAREQC_UART2 (0xA) + +#define MCF5282_SCM_MPARK_M2_P_EN (0x02000000) +#define MCF5282_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF5282_SCM_MPARK_M3_PRTY(x) (((x)&0x03)<<22) +#define MCF5282_SCM_MPARK_M2_PRTY(x) (((x)&0x03)<<20) +#define MCF5282_SCM_MPARK_M0_PRTY(x) (((x)&0x03)<<18) +#define MCF5282_SCM_MPARK_M1_PRTY(x) (((x)&0x03)<<16) +#define MCF5282_SCM_MPARK_FIXED (0x00040000) +#define MCF5282_SCM_MPARK_TIMEOUT (0x00020000) +#define MCF5282_SCM_MPARK_PRK_LAST (0x00010000) +#define MCF5282_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x000F)<<8) + +#define MCF5282_SCM_MPARK_MX_PRTY_FIRST (0x3) +#define MCF5282_SCM_MPARK_MX_PRTY_SECOND (0x2) +#define MCF5282_SCM_MPARK_MX_PRTY_THIRD (0x1) +#define MCF5282_SCM_MPARK_MX_PRTY_FOURTH (0x0) + +#define MCF5282_SCM_MPR_MPR(x) (((x)&0x0F)) + +#define MCF5282_SCM_PACR_LOCK1 (0x80) +#define MCF5282_SCM_PACR_ACCESSCTRL1 (((x)&0x07)<<4) +#define MCF5282_SCM_PACR_LOCK0 (0x08) +#define MCF5282_SCM_PACR_ACCESSCTRL0 (((x)&0x07)) +#define MCF5282_SCM_PACR_RW_NA (0x0) +#define MCF5282_SCM_PACR_R_NA (0x1) +#define MCF5282_SCM_PACR_R_R (0x2) +#define MCF5282_SCM_PACR_RW_RW (0x4) +#define MCF5282_SCM_PACR_RW_R (0x5) +#define MCF5282_SCM_PACR_NA_NA (0x7) + +#define MCF5282_SCM_GPACR_LOCK (0x80) +#define MCF5282_SCM_GPACR_ACCESSCTRL (((x)&0x0F)) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_NA (0x0) +#define MCF5282_SCM_GPACR_ACCESSCTRL_R_NA (0x1) +#define MCF5282_SCM_GPACR_ACCESSCTRL_R_R (0x2) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_RW (0x4) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_R (0x5) +#define MCF5282_SCM_GPACR_ACCESSCTRL_NA_NA (0x7) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_NA (0x8) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RE_NA (0x9) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RE_RE (0xA) +#define MCF5282_SCM_GPACR_ACCESSCTRL_E_NA (0xB) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_RWE (0xC) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_RE (0xD) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_E (0xF) + +/********************************************************************* +* +* SDRAM Controller Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_SDRAMC_DCR (*(vuint16 *)(void *)(&__IPSBAR[0x0040])) +#define MCF5282_SDRAMC_DACR0 (*(vuint32 *)(void *)(&__IPSBAR[0x0048])) +#define MCF5282_SDRAMC_DMR0 (*(vuint32 *)(void *)(&__IPSBAR[0x004C])) +#define MCF5282_SDRAMC_DACR1 (*(vuint32 *)(void *)(&__IPSBAR[0x0050])) +#define MCF5282_SDRAMC_DMR1 (*(vuint32 *)(void *)(&__IPSBAR[0x0054])) + +/* Bit level definitions and macros */ +#define MCF5282_SDRAMC_DCR_NAM (0x2000) +#define MCF5282_SDRAMC_DCR_COC (0x1000) +#define MCF5282_SDRAMC_DCR_IS (0x0800) +#define MCF5282_SDRAMC_DCR_RTIM_3 (0x0000) +#define MCF5282_SDRAMC_DCR_RTIM_6 (0x0200) +#define MCF5282_SDRAMC_DCR_RTIM_9 (0x0400) +#define MCF5282_SDRAMC_DCR_RC(x) ((x)&0x01FF) + +#define MCF5282_SDRAMC_DACR_BASE(x) ((x)&0xFFFC0000) +#define MCF5282_SDRAMC_DACR_RE (0x00008000) +#define MCF5282_SDRAMC_DACR_CASL(x) (((x)&0x03)<<12) +#define MCF5282_SDRAMC_DACR_CBM(x) (((x)&0x07)<<8) +#define MCF5282_SDRAMC_DACR_PS_32 (0x00000000) +#define MCF5282_SDRAMC_DACR_PS_8 (0x00000010) +#define MCF5282_SDRAMC_DACR_PS_16 (0x00000020) +#define MCF5282_SDRAMC_DACR_IMRS (0x00000040) +#define MCF5282_SDRAMC_DACR_IP (0x00000008) + +#define MCF5282_SDRAMC_DMR_BAM_4G (0xFFFC0000) +#define MCF5282_SDRAMC_DMR_BAM_2G (0x7FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_1G (0x3FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_1024M (0x3FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_512M (0x1FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_256M (0x0FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_128M (0x07FC0000) +#define MCF5282_SDRAMC_DMR_BAM_64M (0x03FC0000) +#define MCF5282_SDRAMC_DMR_BAM_32M (0x01FC0000) +#define MCF5282_SDRAMC_DMR_BAM_16M (0x00FC0000) +#define MCF5282_SDRAMC_DMR_BAM_8M (0x007C0000) +#define MCF5282_SDRAMC_DMR_BAM_4M (0x003C0000) +#define MCF5282_SDRAMC_DMR_BAM_2M (0x001C0000) +#define MCF5282_SDRAMC_DMR_BAM_1M (0x000C0000) +#define MCF5282_SDRAMC_DMR_BAM_1024K (0x000C0000) +#define MCF5282_SDRAMC_DMR_BAM_512K (0x00040000) +#define MCF5282_SDRAMC_DMR_BAM_256K (0x00000000) +#define MCF5282_SDRAMC_DMR_WP (0x00000100) +#define MCF5282_SDRAMC_DMR_CI (0x00000040) +#define MCF5282_SDRAMC_DMR_AM (0x00000020) +#define MCF5282_SDRAMC_DMR_SC (0x00000010) +#define MCF5282_SDRAMC_DMR_SD (0x00000008) +#define MCF5282_SDRAMC_DMR_UC (0x00000004) +#define MCF5282_SDRAMC_DMR_UD (0x00000002) +#define MCF5282_SDRAMC_DMR_V (0x00000001) + +/********************************************************************* +* +* Chip Select Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_CS0_CSAR (*(vuint16 *)(void *)(&__IPSBAR[0x0080])) +#define MCF5282_CS0_CSMR (*(vuint32 *)(void *)(&__IPSBAR[0x0084])) +#define MCF5282_CS0_CSCR (*(vuint16 *)(void *)(&__IPSBAR[0x008A])) + +#define MCF5282_CS1_CSAR (*(vuint16 *)(void *)(&__IPSBAR[0x008C])) +#define MCF5282_CS1_CSMR (*(vuint32 *)(void *)(&__IPSBAR[0x0090])) +#define MCF5282_CS1_CSCR (*(vuint16 *)(void *)(&__IPSBAR[0x0096])) + +#define MCF5282_CS2_CSAR (*(vuint16 *)(void *)(&__IPSBAR[0x0098])) +#define MCF5282_CS2_CSMR (*(vuint32 *)(void *)(&__IPSBAR[0x009C])) +#define MCF5282_CS2_CSCR (*(vuint16 *)(void *)(&__IPSBAR[0x00A2])) + +#define MCF5282_CS3_CSAR (*(vuint16 *)(void *)(&__IPSBAR[0x00A4])) +#define MCF5282_CS3_CSMR (*(vuint32 *)(void *)(&__IPSBAR[0x00A8])) +#define MCF5282_CS3_CSCR (*(vuint16 *)(void *)(&__IPSBAR[0x00AE])) + +#define MCF5282_CS4_CSAR (*(vuint16 *)(void *)(&__IPSBAR[0x00B0])) +#define MCF5282_CS4_CSMR (*(vuint32 *)(void *)(&__IPSBAR[0x00B4])) +#define MCF5282_CS4_CSCR (*(vuint16 *)(void *)(&__IPSBAR[0x00BA])) + +#define MCF5282_CS5_CSAR (*(vuint16 *)(void *)(&__IPSBAR[0x00BC])) +#define MCF5282_CS5_CSMR (*(vuint32 *)(void *)(&__IPSBAR[0x00C0])) +#define MCF5282_CS5_CSCR (*(vuint16 *)(void *)(&__IPSBAR[0x00C6])) + +#define MCF5282_CS6_CSAR (*(vuint16 *)(void *)(&__IPSBAR[0x00C8])) +#define MCF5282_CS6_CSMR (*(vuint32 *)(void *)(&__IPSBAR[0x00CC])) +#define MCF5282_CS6_CSCR (*(vuint16 *)(void *)(&__IPSBAR[0x00D2])) + +#define MCF5282_CS_CSAR(x) (*(vuint16 *)(void *)(&__IPSBAR[0x0080+(x*0x0C)])) +#define MCF5282_CS_CSMR(x) (*(vuint32 *)(void *)(&__IPSBAR[0x0084+(x*0x0C)])) +#define MCF5282_CS_CSCR(x) (*(vuint16 *)(void *)(&__IPSBAR[0x008A+(x*0x0C)])) + +/* Bit level definitions and macros */ +#define MCF5282_CS_CSAR_BA(a) (uint16)(((a)&0xFFFF0000)>>16) + +#define MCF5282_CS_CSMR_BAM_4G (0xFFFF0000) +#define MCF5282_CS_CSMR_BAM_2G (0x7FFF0000) +#define MCF5282_CS_CSMR_BAM_1G (0x3FFF0000) +#define MCF5282_CS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF5282_CS_CSMR_BAM_512M (0x1FFF0000) +#define MCF5282_CS_CSMR_BAM_256M (0x0FFF0000) +#define MCF5282_CS_CSMR_BAM_128M (0x07FF0000) +#define MCF5282_CS_CSMR_BAM_64M (0x03FF0000) +#define MCF5282_CS_CSMR_BAM_32M (0x01FF0000) +#define MCF5282_CS_CSMR_BAM_16M (0x00FF0000) +#define MCF5282_CS_CSMR_BAM_8M (0x007F0000) +#define MCF5282_CS_CSMR_BAM_4M (0x003F0000) +#define MCF5282_CS_CSMR_BAM_2M (0x001F0000) +#define MCF5282_CS_CSMR_BAM_1M (0x000F0000) +#define MCF5282_CS_CSMR_BAM_1024K (0x000F0000) +#define MCF5282_CS_CSMR_BAM_512K (0x00070000) +#define MCF5282_CS_CSMR_BAM_256K (0x00030000) +#define MCF5282_CS_CSMR_BAM_128K (0x00010000) +#define MCF5282_CS_CSMR_BAM_64K (0x00000000) +#define MCF5282_CS_CSMR_WP (0x00000100) +#define MCF5282_CS_CSMR_AM (0x00000040) +#define MCF5282_CS_CSMR_CI (0x00000020) +#define MCF5282_CS_CSMR_SC (0x00000010) +#define MCF5282_CS_CSMR_SD (0x00000008) +#define MCF5282_CS_CSMR_UC (0x00000004) +#define MCF5282_CS_CSMR_UD (0x00000002) +#define MCF5282_CS_CSMR_V (0x00000001) + +#define MCF5282_CS_CSCR_WS(x) (((x)&0x0F)<<10) +#define MCF5282_CS_CSCR_AA (0x0100) +#define MCF5282_CS_CSCR_PS_8 (0x0040) +#define MCF5282_CS_CSCR_PS_16 (0x0080) +#define MCF5282_CS_CSCR_PS_32 (0x0000) +#define MCF5282_CS_CSCR_BEM (0x0020) +#define MCF5282_CS_CSCR_BSTR (0x0010) +#define MCF5282_CS_CSCR_BSTW (0x0008) + +/********************************************************************* +* +* Direct Memory Access (DMA) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_DMA0_SAR (*(vuint32 *)(void *)(&__IPSBAR[0x0100])) +#define MCF5282_DMA0_DAR (*(vuint32 *)(void *)(&__IPSBAR[0x0104])) +#define MCF5282_DMA0_DCR (*(vuint32 *)(void *)(&__IPSBAR[0x0108])) +#define MCF5282_DMA0_BCR (*(vuint32 *)(void *)(&__IPSBAR[0x010C])) +#define MCF5282_DMA0_DSR (*(vuint8 *)(void *)(&__IPSBAR[0x0110])) + +#define MCF5282_DMA1_SAR (*(vuint32 *)(void *)(&__IPSBAR[0x0140])) +#define MCF5282_DMA1_DAR (*(vuint32 *)(void *)(&__IPSBAR[0x0144])) +#define MCF5282_DMA1_DCR (*(vuint32 *)(void *)(&__IPSBAR[0x0148])) +#define MCF5282_DMA1_BCR (*(vuint32 *)(void *)(&__IPSBAR[0x014C])) +#define MCF5282_DMA1_DSR (*(vuint8 *)(void *)(&__IPSBAR[0x0150])) + +#define MCF5282_DMA2_SAR (*(vuint32 *)(void *)(&__IPSBAR[0x0180])) +#define MCF5282_DMA2_DAR (*(vuint32 *)(void *)(&__IPSBAR[0x0184])) +#define MCF5282_DMA2_DCR (*(vuint32 *)(void *)(&__IPSBAR[0x0188])) +#define MCF5282_DMA2_BCR (*(vuint32 *)(void *)(&__IPSBAR[0x018C])) +#define MCF5282_DMA2_DSR (*(vuint8 *)(void *)(&__IPSBAR[0x0190])) + +#define MCF5282_DMA3_SAR (*(vuint32 *)(void *)(&__IPSBAR[0x01C0])) +#define MCF5282_DMA3_DAR (*(vuint32 *)(void *)(&__IPSBAR[0x01C4])) +#define MCF5282_DMA3_DCR (*(vuint32 *)(void *)(&__IPSBAR[0x01C8])) +#define MCF5282_DMA3_BCR (*(vuint32 *)(void *)(&__IPSBAR[0x01CC])) +#define MCF5282_DMA3_DSR (*(vuint8 *)(void *)(&__IPSBAR[0x01D0])) + +#define MCF5282_DMA_SAR(x) (*(vuint32 *)(void *)(&__IPSBAR[0x0100+(x*0x40)])) +#define MCF5282_DMA_DAR(x) (*(vuint32 *)(void *)(&__IPSBAR[0x0104+(x*0x40)])) +#define MCF5282_DMA_DCR(x) (*(vuint32 *)(void *)(&__IPSBAR[0x0108+(x*0x40)])) +#define MCF5282_DMA_BCR(x) (*(vuint32 *)(void *)(&__IPSBAR[0x010C+(x*0x40)])) +#define MCF5282_DMA_DSR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0110+(x*0x40)])) + +/* Bit level definitions and macros */ +#define MCF5282_DMA_DCR_INT (0x80000000) +#define MCF5282_DMA_DCR_EEXT (0x40000000) +#define MCF5282_DMA_DCR_CS (0x20000000) +#define MCF5282_DMA_DCR_AA (0x10000000) +#define MCF5282_DMA_DCR_BWC_DMA (0x00000000) +#define MCF5282_DMA_DCR_BWC_512 (0x02000000) +#define MCF5282_DMA_DCR_BWC_1024 (0x04000000) +#define MCF5282_DMA_DCR_BWC_2048 (0x06000000) +#define MCF5282_DMA_DCR_BWC_4096 (0x08000000) +#define MCF5282_DMA_DCR_BWC_8192 (0x0A000000) +#define MCF5282_DMA_DCR_BWC_16384 (0x0C000000) +#define MCF5282_DMA_DCR_BWC_32768 (0x0E000000) +#define MCF5282_DMA_DCR_SINC (0x00400000) +#define MCF5282_DMA_DCR_SSIZE_LONG (0x00000000) +#define MCF5282_DMA_DCR_SSIZE_BYTE (0x00100000) +#define MCF5282_DMA_DCR_SSIZE_WORD (0x00200000) +#define MCF5282_DMA_DCR_SSIZE_LINE (0x00300000) +#define MCF5282_DMA_DCR_DINC (0x00080000) +#define MCF5282_DMA_DCR_DSIZE_LONG (0x00000000) +#define MCF5282_DMA_DCR_DSIZE_BYTE (0x00020000) +#define MCF5282_DMA_DCR_DSIZE_WORD (0x00040000) +#define MCF5282_DMA_DCR_START (0x00010000) +#define MCF5282_DMA_DCR_AT (0x00008000) + +#define MCF5282_DMA_DSR_CE (0x40) +#define MCF5282_DMA_DSR_BES (0x20) +#define MCF5282_DMA_DSR_BED (0x10) +#define MCF5282_DMA_DSR_REQ (0x04) +#define MCF5282_DMA_DSR_BSY (0x02) +#define MCF5282_DMA_DSR_DONE (0x01) + +/********************************************************************* +* +* Universal Asychronous Receiver/Transmitter (UART) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_UART0_UMR (*(vuint8 *)(void *)(&__IPSBAR[0x0200])) +#define MCF5282_UART0_USR (*(vuint8 *)(void *)(&__IPSBAR[0x0204])) +#define MCF5282_UART0_UCSR (*(vuint8 *)(void *)(&__IPSBAR[0x0204])) +#define MCF5282_UART0_UCR (*(vuint8 *)(void *)(&__IPSBAR[0x0208])) +#define MCF5282_UART0_URB (*(vuint8 *)(void *)(&__IPSBAR[0x020C])) +#define MCF5282_UART0_UTB (*(vuint8 *)(void *)(&__IPSBAR[0x020C])) +#define MCF5282_UART0_UIPCR (*(vuint8 *)(void *)(&__IPSBAR[0x0210])) +#define MCF5282_UART0_UACR (*(vuint8 *)(void *)(&__IPSBAR[0x0210])) +#define MCF5282_UART0_UISR (*(vuint8 *)(void *)(&__IPSBAR[0x0214])) +#define MCF5282_UART0_UIMR (*(vuint8 *)(void *)(&__IPSBAR[0x0214])) +#define MCF5282_UART0_UBG1 (*(vuint8 *)(void *)(&__IPSBAR[0x0218])) +#define MCF5282_UART0_UBG2 (*(vuint8 *)(void *)(&__IPSBAR[0x021C])) +#define MCF5282_UART0_UIP (*(vuint8 *)(void *)(&__IPSBAR[0x0234])) +#define MCF5282_UART0_UOP1 (*(vuint8 *)(void *)(&__IPSBAR[0x0238])) +#define MCF5282_UART0_UOP0 (*(vuint8 *)(void *)(&__IPSBAR[0x023C])) + +#define MCF5282_UART1_UMR (*(vuint8 *)(void *)(&__IPSBAR[0x0240])) +#define MCF5282_UART1_USR (*(vuint8 *)(void *)(&__IPSBAR[0x0244])) +#define MCF5282_UART1_UCSR (*(vuint8 *)(void *)(&__IPSBAR[0x0244])) +#define MCF5282_UART1_UCR (*(vuint8 *)(void *)(&__IPSBAR[0x0248])) +#define MCF5282_UART1_URB (*(vuint8 *)(void *)(&__IPSBAR[0x024C])) +#define MCF5282_UART1_UTB (*(vuint8 *)(void *)(&__IPSBAR[0x024C])) +#define MCF5282_UART1_UIPCR (*(vuint8 *)(void *)(&__IPSBAR[0x0250])) +#define MCF5282_UART1_UACR (*(vuint8 *)(void *)(&__IPSBAR[0x0250])) +#define MCF5282_UART1_UISR (*(vuint8 *)(void *)(&__IPSBAR[0x0254])) +#define MCF5282_UART1_UIMR (*(vuint8 *)(void *)(&__IPSBAR[0x0254])) +#define MCF5282_UART1_UBG1 (*(vuint8 *)(void *)(&__IPSBAR[0x0258])) +#define MCF5282_UART1_UBG2 (*(vuint8 *)(void *)(&__IPSBAR[0x025C])) +#define MCF5282_UART1_UIP (*(vuint8 *)(void *)(&__IPSBAR[0x0274])) +#define MCF5282_UART1_UOP1 (*(vuint8 *)(void *)(&__IPSBAR[0x0278])) +#define MCF5282_UART1_UOP0 (*(vuint8 *)(void *)(&__IPSBAR[0x027C])) + +#define MCF5282_UART2_UMR (*(vuint8 *)(void *)(&__IPSBAR[0x0280])) +#define MCF5282_UART2_USR (*(vuint8 *)(void *)(&__IPSBAR[0x0284])) +#define MCF5282_UART2_UCSR (*(vuint8 *)(void *)(&__IPSBAR[0x0284])) +#define MCF5282_UART2_UCR (*(vuint8 *)(void *)(&__IPSBAR[0x0288])) +#define MCF5282_UART2_URB (*(vuint8 *)(void *)(&__IPSBAR[0x028C])) +#define MCF5282_UART2_UTB (*(vuint8 *)(void *)(&__IPSBAR[0x028C])) +#define MCF5282_UART2_UIPCR (*(vuint8 *)(void *)(&__IPSBAR[0x0290])) +#define MCF5282_UART2_UACR (*(vuint8 *)(void *)(&__IPSBAR[0x0290])) +#define MCF5282_UART2_UISR (*(vuint8 *)(void *)(&__IPSBAR[0x0294])) +#define MCF5282_UART2_UIMR (*(vuint8 *)(void *)(&__IPSBAR[0x0294])) +#define MCF5282_UART2_UBG1 (*(vuint8 *)(void *)(&__IPSBAR[0x0298])) +#define MCF5282_UART2_UBG2 (*(vuint8 *)(void *)(&__IPSBAR[0x029C])) +#define MCF5282_UART2_UIP (*(vuint8 *)(void *)(&__IPSBAR[0x02B4])) +#define MCF5282_UART2_UOP1 (*(vuint8 *)(void *)(&__IPSBAR[0x02B8])) +#define MCF5282_UART2_UOP0 (*(vuint8 *)(void *)(&__IPSBAR[0x02BC])) + +#define MCF5282_UART_UMR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0200+(x*0x40)])) +#define MCF5282_UART_USR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0204+(x*0x40)])) +#define MCF5282_UART_UCSR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0204+(x*0x40)])) +#define MCF5282_UART_UCR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0208+(x*0x40)])) +#define MCF5282_UART_URB(x) (*(vuint8 *)(void *)(&__IPSBAR[0x20C+(x*0x40)])) +#define MCF5282_UART_UTB(x) (*(vuint8 *)(void *)(&__IPSBAR[0x020C+(x*0x40)])) +#define MCF5282_UART_UIPCR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0210+(x*0x40)])) +#define MCF5282_UART_UACR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0210+(x*0x40)])) +#define MCF5282_UART_UISR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0214+(x*0x40)])) +#define MCF5282_UART_UIMR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0214+(x*0x40)])) +#define MCF5282_UART_UBG1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0218+(x*0x40)])) +#define MCF5282_UART_UBG2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x021C+(x*0x40)])) +#define MCF5282_UART_UIP(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0234+(x*0x40)])) +#define MCF5282_UART_UOP1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0238+(x*0x40)])) +#define MCF5282_UART_UOP0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x023C+(x*0x40)])) + +/* Bit level definitions and macros */ +#define MCF5282_UART_UMR1_RXRTS (0x80) +#define MCF5282_UART_UMR1_RXIRQ (0x40) +#define MCF5282_UART_UMR1_ERR (0x20) +#define MCF5282_UART_UMR1_PM_MULTI_ADDR (0x1C) +#define MCF5282_UART_UMR1_PM_MULTI_DATA (0x18) +#define MCF5282_UART_UMR1_PM_NONE (0x10) +#define MCF5282_UART_UMR1_PM_FORCE_HI (0x0C) +#define MCF5282_UART_UMR1_PM_FORCE_LO (0x08) +#define MCF5282_UART_UMR1_PM_ODD (0x04) +#define MCF5282_UART_UMR1_PM_EVEN (0x00) +#define MCF5282_UART_UMR1_BC_5 (0x00) +#define MCF5282_UART_UMR1_BC_6 (0x01) +#define MCF5282_UART_UMR1_BC_7 (0x02) +#define MCF5282_UART_UMR1_BC_8 (0x03) + +#define MCF5282_UART_UMR2_CM_NORMAL (0x00) +#define MCF5282_UART_UMR2_CM_ECHO (0x40) +#define MCF5282_UART_UMR2_CM_LOCAL_LOOP (0x80) +#define MCF5282_UART_UMR2_CM_REMOTE_LOOP (0xC0) +#define MCF5282_UART_UMR2_TXRTS (0x20) +#define MCF5282_UART_UMR2_TXCTS (0x10) +#define MCF5282_UART_UMR2_STOP_BITS_1 (0x07) +#define MCF5282_UART_UMR2_STOP_BITS_15 (0x08) +#define MCF5282_UART_UMR2_STOP_BITS_2 (0x0F) +#define MCF5282_UART_UMR2_STOP_BITS(a) ((a)&0x0f) + +#define MCF5282_UART_USR_RB (0x80) +#define MCF5282_UART_USR_FE (0x40) +#define MCF5282_UART_USR_PE (0x20) +#define MCF5282_UART_USR_OE (0x10) +#define MCF5282_UART_USR_TXEMP (0x08) +#define MCF5282_UART_USR_TXRDY (0x04) +#define MCF5282_UART_USR_FFULL (0x02) +#define MCF5282_UART_USR_RXRDY (0x01) + +#define MCF5282_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF5282_UART_UCSR_RCS_DTIN16 (0xE0) +#define MCF5282_UART_UCSR_RCS_DTIN (0xF0) +#define MCF5282_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF5282_UART_UCSR_TCS_DTIN16 (0x0E) +#define MCF5282_UART_UCSR_TCS_DTIN (0x0F) + +#define MCF5282_UART_UCR_NONE (0x00) +#define MCF5282_UART_UCR_STOP_BREAK (0x70) +#define MCF5282_UART_UCR_START_BREAK (0x60) +#define MCF5282_UART_UCR_RESET_BKCHGINT (0x50) +#define MCF5282_UART_UCR_RESET_ERROR (0x40) +#define MCF5282_UART_UCR_RESET_TX (0x30) +#define MCF5282_UART_UCR_RESET_RX (0x20) +#define MCF5282_UART_UCR_RESET_MR (0x10) +#define MCF5282_UART_UCR_TX_DISABLED (0x08) +#define MCF5282_UART_UCR_TX_ENABLED (0x04) +#define MCF5282_UART_UCR_RX_DISABLED (0x02) +#define MCF5282_UART_UCR_RX_ENABLED (0x01) + +#define MCF5282_UART_UIPCR_COS (0x10) +#define MCF5282_UART_UIPCR_CTS (0x01) + +#define MCF5282_UART_UACR_IEC (0x01) + +#define MCF5282_UART_UISR_COS (0x80) +#define MCF5282_UART_UISR_ABC (0x40) +#define MCF5282_UART_UISR_RXFIFO (0x20) +#define MCF5282_UART_UISR_TXFIFO (0x10) +#define MCF5282_UART_UISR_RXFTO (0x08) +#define MCF5282_UART_UISR_DB (0x04) +#define MCF5282_UART_UISR_RXRDY (0x02) +#define MCF5282_UART_UISR_TXRDY (0x01) + +#define MCF5282_UART_UIMR_COS (0x80) +#define MCF5282_UART_UIMR_DB (0x04) +#define MCF5282_UART_UIMR_FFULL (0x02) +#define MCF5282_UART_UIMR_TXRDY (0x01) + +#define MCF5282_UART_UIP_CTS (0x01) + +#define MCF5282_UART_UOP_RTS (0x01) + +/********************************************************************* +* +* Inter-IC (I2C) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_I2C_I2ADR (*(vuint8 *)(void *)(&__IPSBAR[0x0300])) +#define MCF5282_I2C_I2FDR (*(vuint8 *)(void *)(&__IPSBAR[0x0304])) +#define MCF5282_I2C_I2CR (*(vuint8 *)(void *)(&__IPSBAR[0x0308])) +#define MCF5282_I2C_I2SR (*(vuint8 *)(void *)(&__IPSBAR[0x030C])) +#define MCF5282_I2C_I2DR (*(vuint8 *)(void *)(&__IPSBAR[0x0310])) + +/* Bit level definitions and macros */ +#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) + +#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) + +#define MCF5282_I2C_I2CR_IEN (0x80) +#define MCF5282_I2C_I2CR_IIEN (0x40) +#define MCF5282_I2C_I2CR_MSTA (0x20) +#define MCF5282_I2C_I2CR_MTX (0x10) +#define MCF5282_I2C_I2CR_TXAK (0x08) +#define MCF5282_I2C_I2CR_RSTA (0x04) + +#define MCF5282_I2C_I2SR_ICF (0x80) +#define MCF5282_I2C_I2SR_IAAS (0x40) +#define MCF5282_I2C_I2SR_IBB (0x20) +#define MCF5282_I2C_I2SR_IAL (0x10) +#define MCF5282_I2C_I2SR_SRW (0x04) +#define MCF5282_I2C_I2SR_IIF (0x02) +#define MCF5282_I2C_I2SR_RXAK (0x01) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_QSPI_QMR (*(vuint16 *)(void *)(&__IPSBAR[0x0340])) +#define MCF5282_QSPI_QDLYR (*(vuint16 *)(void *)(&__IPSBAR[0x0344])) +#define MCF5282_QSPI_QWR (*(vuint16 *)(void *)(&__IPSBAR[0x0348])) +#define MCF5282_QSPI_QIR (*(vuint16 *)(void *)(&__IPSBAR[0x034C])) +#define MCF5282_QSPI_QAR (*(vuint16 *)(void *)(&__IPSBAR[0x0350])) +#define MCF5282_QSPI_QDR (*(vuint16 *)(void *)(&__IPSBAR[0x0354])) +#define MCF5282_QSPI_QCR (*(vuint16 *)(void *)(&__IPSBAR[0x0354])) + +/* Bit level definitions and macros */ +#define MCF5282_QSPI_QMR_MSTR (0x8000) +#define MCF5282_QSPI_QMR_DOHIE (0x4000) +#define MCF5282_QSPI_QMR_BITS_16 (0x0000) +#define MCF5282_QSPI_QMR_BITS_8 (0x2000) +#define MCF5282_QSPI_QMR_BITS_9 (0x2400) +#define MCF5282_QSPI_QMR_BITS_10 (0x2800) +#define MCF5282_QSPI_QMR_BITS_11 (0x2C00) +#define MCF5282_QSPI_QMR_BITS_12 (0x3000) +#define MCF5282_QSPI_QMR_BITS_13 (0x3400) +#define MCF5282_QSPI_QMR_BITS_14 (0x3800) +#define MCF5282_QSPI_QMR_BITS_15 (0x3C00) +#define MCF5282_QSPI_QMR_CPOL (0x0200) +#define MCF5282_QSPI_QMR_CPHA (0x0100) +#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) + +#define MCF5282_QSPI_QDLYR_SPE (0x80) +#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) + +#define MCF5282_QSPI_QWR_HALT (0x8000) +#define MCF5282_QSPI_QWR_WREN (0x4000) +#define MCF5282_QSPI_QWR_WRTO (0x2000) +#define MCF5282_QSPI_QWR_CSIV (0x1000) +#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) +#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) + +#define MCF5282_QSPI_QIR_WCEFB (0x8000) +#define MCF5282_QSPI_QIR_ABRTB (0x4000) +#define MCF5282_QSPI_QIR_ABRTL (0x1000) +#define MCF5282_QSPI_QIR_WCEFE (0x0800) +#define MCF5282_QSPI_QIR_ABRTE (0x0400) +#define MCF5282_QSPI_QIR_SPIFE (0x0100) +#define MCF5282_QSPI_QIR_WCEF (0x0008) +#define MCF5282_QSPI_QIR_ABRT (0x0004) +#define MCF5282_QSPI_QIR_SPIF (0x0001) + +#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) + +#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) + +#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) +#define MCF5282_QSPI_QCR_CONT (0x8000) +#define MCF5282_QSPI_QCR_BITSE (0x4000) +#define MCF5282_QSPI_QCR_DT (0x2000) +#define MCF5282_QSPI_QCR_DSCK (0x1000) +#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8) + +/********************************************************************* +* +* DMA Timer Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_TIMER0_DTMR (*(vuint16 *)(void *)(&__IPSBAR[0x0400])) +#define MCF5282_TIMER0_DTXMR (*(vuint8 *)(void *)(&__IPSBAR[0x0402])) +#define MCF5282_TIMER0_DTER (*(vuint8 *)(void *)(&__IPSBAR[0x0403])) +#define MCF5282_TIMER0_DTRR (*(vuint32 *)(void *)(&__IPSBAR[0x0404])) +#define MCF5282_TIMER0_DTCR (*(vuint32 *)(void *)(&__IPSBAR[0x0408])) +#define MCF5282_TIMER0_DTCN (*(vuint32 *)(void *)(&__IPSBAR[0x040C])) + +#define MCF5282_TIMER1_DTMR (*(vuint16 *)(void *)(&__IPSBAR[0x0440])) +#define MCF5282_TIMER1_DTXMR (*(vuint8 *)(void *)(&__IPSBAR[0x0442])) +#define MCF5282_TIMER1_DTER (*(vuint8 *)(void *)(&__IPSBAR[0x0443])) +#define MCF5282_TIMER1_DTRR (*(vuint32 *)(void *)(&__IPSBAR[0x0444])) +#define MCF5282_TIMER1_DTCR (*(vuint32 *)(void *)(&__IPSBAR[0x0448])) +#define MCF5282_TIMER1_DTCN (*(vuint32 *)(void *)(&__IPSBAR[0x044C])) + +#define MCF5282_TIMER2_DTMR (*(vuint16 *)(void *)(&__IPSBAR[0x0480])) +#define MCF5282_TIMER2_DTXMR (*(vuint8 *)(void *)(&__IPSBAR[0x0482])) +#define MCF5282_TIMER2_DTER (*(vuint8 *)(void *)(&__IPSBAR[0x0483])) +#define MCF5282_TIMER2_DTRR (*(vuint32 *)(void *)(&__IPSBAR[0x0484])) +#define MCF5282_TIMER2_DTCR (*(vuint32 *)(void *)(&__IPSBAR[0x0488])) +#define MCF5282_TIMER2_DTCN (*(vuint32 *)(void *)(&__IPSBAR[0x048C])) + +#define MCF5282_TIMER3_DTMR (*(vuint16 *)(void *)(&__IPSBAR[0x04C0])) +#define MCF5282_TIMER3_DTXMR (*(vuint8 *)(void *)(&__IPSBAR[0x04C2])) +#define MCF5282_TIMER3_DTER (*(vuint8 *)(void *)(&__IPSBAR[0x04C3])) +#define MCF5282_TIMER3_DTRR (*(vuint32 *)(void *)(&__IPSBAR[0x04C4])) +#define MCF5282_TIMER3_DTCR (*(vuint32 *)(void *)(&__IPSBAR[0x04C8])) +#define MCF5282_TIMER3_DTCN (*(vuint32 *)(void *)(&__IPSBAR[0x04CC])) + +#define MCF5282_TIMER_DTMR(x) (*(vuint16 *)(void *)(&__IPSBAR[0x0400+(x*0x40)])) +#define MCF5282_TIMER_DTXMR(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0402+(x*0x40)])) +#define MCF5282_TIMER_DTER(x) (*(vuint8 *)(void *)(&__IPSBAR[0x0403+(x*0x40)])) +#define MCF5282_TIMER_DTRR(x) (*(vuint32 *)(void *)(&__IPSBAR[0x0404+(x*0x40)])) +#define MCF5282_TIMER_DTCR(x) (*(vuint32 *)(void *)(&__IPSBAR[0x0408+(x*0x40)])) +#define MCF5282_TIMER_DTCN(x) (*(vuint32 *)(void *)(&__IPSBAR[0x040C+(x*0x40)])) + +/* Bit level definitions and macros */ +#define MCF5282_TIMER_DTMR_PS(a) (((a)&0x00FF)<<8) +#define MCF5282_TIMER_DTMR_CE_ANY (0x00C0) +#define MCF5282_TIMER_DTMR_CE_FALL (0x0080) +#define MCF5282_TIMER_DTMR_CE_RISE (0x0040) +#define MCF5282_TIMER_DTMR_CE_NONE (0x0000) +#define MCF5282_TIMER_DTMR_OM (0x0020) +#define MCF5282_TIMER_DTMR_ORRI (0x0010) +#define MCF5282_TIMER_DTMR_FRR (0x0008) +#define MCF5282_TIMER_DTMR_CLK_DTIN (0x0006) +#define MCF5282_TIMER_DTMR_CLK_DIV16 (0x0004) +#define MCF5282_TIMER_DTMR_CLK_DIV1 (0x0002) +#define MCF5282_TIMER_DTMR_CLK_STOP (0x0000) +#define MCF5282_TIMER_DTMR_RST (0x0001) + +#define MCF5282_TIMER_DTXMR_DMAEN (0x80) +#define MCF5282_TIMER_DTXMR_MODE16 (0x01) + +#define MCF5282_TIMER_DTER_REF (0x02) +#define MCF5282_TIMER_DTER_CAP (0x01) + +/********************************************************************* +* +* Interrupt Controller (INTC) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_INTC0_IPRH (*(vuint32 *)(void *)(&__IPSBAR[0x0C00])) +#define MCF5282_INTC0_IPRL (*(vuint32 *)(void *)(&__IPSBAR[0x0C04])) +#define MCF5282_INTC0_IMRH (*(vuint32 *)(void *)(&__IPSBAR[0x0C08])) +#define MCF5282_INTC0_IMRL (*(vuint32 *)(void *)(&__IPSBAR[0x0C0C])) +#define MCF5282_INTC0_INTFRCH (*(vuint32 *)(void *)(&__IPSBAR[0x0C10])) +#define MCF5282_INTC0_INTFRCL (*(vuint32 *)(void *)(&__IPSBAR[0x0C14])) +#define MCF5282_INTC0_IRLR (*(vuint8 *)(void *)(&__IPSBAR[0x0C18])) +#define MCF5282_INTC0_IACKLPR (*(vuint8 *)(void *)(&__IPSBAR[0x0C19])) +#define MCF5282_INTC0_ICR1 (*(vuint8 *)(void *)(&__IPSBAR[0x0C41])) +#define MCF5282_INTC0_ICR2 (*(vuint8 *)(void *)(&__IPSBAR[0x0C42])) +#define MCF5282_INTC0_ICR3 (*(vuint8 *)(void *)(&__IPSBAR[0x0C43])) +#define MCF5282_INTC0_ICR4 (*(vuint8 *)(void *)(&__IPSBAR[0x0C44])) +#define MCF5282_INTC0_ICR5 (*(vuint8 *)(void *)(&__IPSBAR[0x0C45])) +#define MCF5282_INTC0_ICR6 (*(vuint8 *)(void *)(&__IPSBAR[0x0C46])) +#define MCF5282_INTC0_ICR7 (*(vuint8 *)(void *)(&__IPSBAR[0x0C47])) +#define MCF5282_INTC0_ICR8 (*(vuint8 *)(void *)(&__IPSBAR[0x0C48])) +#define MCF5282_INTC0_ICR9 (*(vuint8 *)(void *)(&__IPSBAR[0x0C49])) +#define MCF5282_INTC0_ICR10 (*(vuint8 *)(void *)(&__IPSBAR[0x0C4A])) +#define MCF5282_INTC0_ICR11 (*(vuint8 *)(void *)(&__IPSBAR[0x0C4B])) +#define MCF5282_INTC0_ICR12 (*(vuint8 *)(void *)(&__IPSBAR[0x0C4C])) +#define MCF5282_INTC0_ICR13 (*(vuint8 *)(void *)(&__IPSBAR[0x0C4D])) +#define MCF5282_INTC0_ICR14 (*(vuint8 *)(void *)(&__IPSBAR[0x0C4E])) +#define MCF5282_INTC0_ICR15 (*(vuint8 *)(void *)(&__IPSBAR[0x0C4F])) +#define MCF5282_INTC0_ICR17 (*(vuint8 *)(void *)(&__IPSBAR[0x0C51])) +#define MCF5282_INTC0_ICR18 (*(vuint8 *)(void *)(&__IPSBAR[0x0C52])) +#define MCF5282_INTC0_ICR19 (*(vuint8 *)(void *)(&__IPSBAR[0x0C53])) +#define MCF5282_INTC0_ICR20 (*(vuint8 *)(void *)(&__IPSBAR[0x0C54])) +#define MCF5282_INTC0_ICR21 (*(vuint8 *)(void *)(&__IPSBAR[0x0C55])) +#define MCF5282_INTC0_ICR22 (*(vuint8 *)(void *)(&__IPSBAR[0x0C56])) +#define MCF5282_INTC0_ICR23 (*(vuint8 *)(void *)(&__IPSBAR[0x0C57])) +#define MCF5282_INTC0_ICR24 (*(vuint8 *)(void *)(&__IPSBAR[0x0C58])) +#define MCF5282_INTC0_ICR25 (*(vuint8 *)(void *)(&__IPSBAR[0x0C59])) +#define MCF5282_INTC0_ICR26 (*(vuint8 *)(void *)(&__IPSBAR[0x0C5A])) +#define MCF5282_INTC0_ICR27 (*(vuint8 *)(void *)(&__IPSBAR[0x0C5B])) +#define MCF5282_INTC0_ICR28 (*(vuint8 *)(void *)(&__IPSBAR[0x0C5C])) +#define MCF5282_INTC0_ICR29 (*(vuint8 *)(void *)(&__IPSBAR[0x0C5D])) +#define MCF5282_INTC0_ICR30 (*(vuint8 *)(void *)(&__IPSBAR[0x0C5E])) +#define MCF5282_INTC0_ICR31 (*(vuint8 *)(void *)(&__IPSBAR[0x0C5F])) +#define MCF5282_INTC0_ICR32 (*(vuint8 *)(void *)(&__IPSBAR[0x0C60])) +#define MCF5282_INTC0_ICR33 (*(vuint8 *)(void *)(&__IPSBAR[0x0C61])) +#define MCF5282_INTC0_ICR34 (*(vuint8 *)(void *)(&__IPSBAR[0x0C62])) +#define MCF5282_INTC0_ICR35 (*(vuint8 *)(void *)(&__IPSBAR[0x0C63])) +#define MCF5282_INTC0_ICR36 (*(vuint8 *)(void *)(&__IPSBAR[0x0C64])) +#define MCF5282_INTC0_ICR37 (*(vuint8 *)(void *)(&__IPSBAR[0x0C65])) +#define MCF5282_INTC0_ICR38 (*(vuint8 *)(void *)(&__IPSBAR[0x0C66])) +#define MCF5282_INTC0_ICR39 (*(vuint8 *)(void *)(&__IPSBAR[0x0C67])) +#define MCF5282_INTC0_ICR40 (*(vuint8 *)(void *)(&__IPSBAR[0x0C68])) +#define MCF5282_INTC0_ICR41 (*(vuint8 *)(void *)(&__IPSBAR[0x0C69])) +#define MCF5282_INTC0_ICR42 (*(vuint8 *)(void *)(&__IPSBAR[0x0C6A])) +#define MCF5282_INTC0_ICR43 (*(vuint8 *)(void *)(&__IPSBAR[0x0C6B])) +#define MCF5282_INTC0_ICR44 (*(vuint8 *)(void *)(&__IPSBAR[0x0C6C])) +#define MCF5282_INTC0_ICR45 (*(vuint8 *)(void *)(&__IPSBAR[0x0C6D])) +#define MCF5282_INTC0_ICR46 (*(vuint8 *)(void *)(&__IPSBAR[0x0C6E])) +#define MCF5282_INTC0_ICR47 (*(vuint8 *)(void *)(&__IPSBAR[0x0C6F])) +#define MCF5282_INTC0_ICR48 (*(vuint8 *)(void *)(&__IPSBAR[0x0C70])) +#define MCF5282_INTC0_ICR49 (*(vuint8 *)(void *)(&__IPSBAR[0x0C71])) +#define MCF5282_INTC0_ICR50 (*(vuint8 *)(void *)(&__IPSBAR[0x0C72])) +#define MCF5282_INTC0_ICR51 (*(vuint8 *)(void *)(&__IPSBAR[0x0C73])) +#define MCF5282_INTC0_ICR52 (*(vuint8 *)(void *)(&__IPSBAR[0x0C74])) +#define MCF5282_INTC0_ICR53 (*(vuint8 *)(void *)(&__IPSBAR[0x0C75])) +#define MCF5282_INTC0_ICR54 (*(vuint8 *)(void *)(&__IPSBAR[0x0C76])) +#define MCF5282_INTC0_ICR55 (*(vuint8 *)(void *)(&__IPSBAR[0x0C77])) +#define MCF5282_INTC0_ICR56 (*(vuint8 *)(void *)(&__IPSBAR[0x0C78])) +#define MCF5282_INTC0_ICR57 (*(vuint8 *)(void *)(&__IPSBAR[0x0C79])) +#define MCF5282_INTC0_ICR58 (*(vuint8 *)(void *)(&__IPSBAR[0x0C7A])) +#define MCF5282_INTC0_ICR59 (*(vuint8 *)(void *)(&__IPSBAR[0x0C7B])) +#define MCF5282_INTC0_ICR60 (*(vuint8 *)(void *)(&__IPSBAR[0x0C7C])) +#define MCF5282_INTC0_ICR61 (*(vuint8 *)(void *)(&__IPSBAR[0x0C7D])) +#define MCF5282_INTC0_ICR62 (*(vuint8 *)(void *)(&__IPSBAR[0x0C7E])) +#define MCF5282_INTC0_SWIACK (*(vuint8 *)(void *)(&__IPSBAR[0x0CE0])) +#define MCF5282_INTC0_L1IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0CE4])) +#define MCF5282_INTC0_L2IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0CE8])) +#define MCF5282_INTC0_L3IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0CEC])) +#define MCF5282_INTC0_L4IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0CF0])) +#define MCF5282_INTC0_L5IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0CF4])) +#define MCF5282_INTC0_L6IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0CF8])) +#define MCF5282_INTC0_L7IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0CFC])) + +#define MCF5282_INTC1_IPRH (*(vuint32 *)(void *)(&__IPSBAR[0x0D00])) +#define MCF5282_INTC1_IPRL (*(vuint32 *)(void *)(&__IPSBAR[0x0D04])) +#define MCF5282_INTC1_IMRH (*(vuint32 *)(void *)(&__IPSBAR[0x0D08])) +#define MCF5282_INTC1_IMRL (*(vuint32 *)(void *)(&__IPSBAR[0x0D0C])) +#define MCF5282_INTC1_INTFRCH (*(vuint32 *)(void *)(&__IPSBAR[0x0D10])) +#define MCF5282_INTC1_INTFRCL (*(vuint32 *)(void *)(&__IPSBAR[0x0D14])) +#define MCF5282_INTC1_IRLR (*(vuint8 *)(void *)(&__IPSBAR[0x0D18])) +#define MCF5282_INTC1_IACKLPR (*(vuint8 *)(void *)(&__IPSBAR[0x0D19])) +#define MCF5282_INTC1_ICR08 (*(vuint8 *)(void *)(&__IPSBAR[0x0D48])) +#define MCF5282_INTC1_ICR09 (*(vuint8 *)(void *)(&__IPSBAR[0x0D49])) +#define MCF5282_INTC1_ICR10 (*(vuint8 *)(void *)(&__IPSBAR[0x0D4A])) +#define MCF5282_INTC1_ICR11 (*(vuint8 *)(void *)(&__IPSBAR[0x0D4B])) +#define MCF5282_INTC1_ICR12 (*(vuint8 *)(void *)(&__IPSBAR[0x0D4C])) +#define MCF5282_INTC1_ICR13 (*(vuint8 *)(void *)(&__IPSBAR[0x0D4D])) +#define MCF5282_INTC1_ICR14 (*(vuint8 *)(void *)(&__IPSBAR[0x0D4E])) +#define MCF5282_INTC1_ICR15 (*(vuint8 *)(void *)(&__IPSBAR[0x0D4F])) +#define MCF5282_INTC1_ICR16 (*(vuint8 *)(void *)(&__IPSBAR[0x0D50])) +#define MCF5282_INTC1_ICR17 (*(vuint8 *)(void *)(&__IPSBAR[0x0D51])) +#define MCF5282_INTC1_ICR18 (*(vuint8 *)(void *)(&__IPSBAR[0x0D52])) +#define MCF5282_INTC1_ICR19 (*(vuint8 *)(void *)(&__IPSBAR[0x0D53])) +#define MCF5282_INTC1_ICR20 (*(vuint8 *)(void *)(&__IPSBAR[0x0D54])) +#define MCF5282_INTC1_ICR21 (*(vuint8 *)(void *)(&__IPSBAR[0x0D55])) +#define MCF5282_INTC1_ICR22 (*(vuint8 *)(void *)(&__IPSBAR[0x0D56])) +#define MCF5282_INTC1_ICR23 (*(vuint8 *)(void *)(&__IPSBAR[0x0D57])) +#define MCF5282_INTC1_ICR24 (*(vuint8 *)(void *)(&__IPSBAR[0x0D58])) +#define MCF5282_INTC1_ICR25 (*(vuint8 *)(void *)(&__IPSBAR[0x0D59])) +#define MCF5282_INTC1_ICR26 (*(vuint8 *)(void *)(&__IPSBAR[0x0D5A])) +#define MCF5282_INTC1_SWIACK (*(vuint8 *)(void *)(&__IPSBAR[0x0DE0])) +#define MCF5282_INTC1_L1IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0DE4])) +#define MCF5282_INTC1_L2IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0DE8])) +#define MCF5282_INTC1_L3IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0DEC])) +#define MCF5282_INTC1_L4IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0DF0])) +#define MCF5282_INTC1_L5IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0DF4])) +#define MCF5282_INTC1_L6IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0DF8])) +#define MCF5282_INTC1_L7IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0DFC])) + +/* Bit level definitions and macros */ +#define MCF5282_INTC_IPRH_INT63 (0x80000000) +#define MCF5282_INTC_IPRH_INT62 (0x40000000) +#define MCF5282_INTC_IPRH_INT61 (0x20000000) +#define MCF5282_INTC_IPRH_INT60 (0x10000000) +#define MCF5282_INTC_IPRH_INT59 (0x08000000) +#define MCF5282_INTC_IPRH_INT58 (0x04000000) +#define MCF5282_INTC_IPRH_INT57 (0x02000000) +#define MCF5282_INTC_IPRH_INT56 (0x01000000) +#define MCF5282_INTC_IPRH_INT55 (0x00800000) +#define MCF5282_INTC_IPRH_INT54 (0x00400000) +#define MCF5282_INTC_IPRH_INT53 (0x00200000) +#define MCF5282_INTC_IPRH_INT52 (0x00100000) +#define MCF5282_INTC_IPRH_INT51 (0x00080000) +#define MCF5282_INTC_IPRH_INT50 (0x00040000) +#define MCF5282_INTC_IPRH_INT49 (0x00020000) +#define MCF5282_INTC_IPRH_INT48 (0x00010000) +#define MCF5282_INTC_IPRH_INT47 (0x00008000) +#define MCF5282_INTC_IPRH_INT46 (0x00004000) +#define MCF5282_INTC_IPRH_INT45 (0x00002000) +#define MCF5282_INTC_IPRH_INT44 (0x00001000) +#define MCF5282_INTC_IPRH_INT43 (0x00000800) +#define MCF5282_INTC_IPRH_INT42 (0x00000400) +#define MCF5282_INTC_IPRH_INT41 (0x00000200) +#define MCF5282_INTC_IPRH_INT40 (0x00000100) +#define MCF5282_INTC_IPRH_INT39 (0x00000080) +#define MCF5282_INTC_IPRH_INT38 (0x00000040) +#define MCF5282_INTC_IPRH_INT37 (0x00000020) +#define MCF5282_INTC_IPRH_INT36 (0x00000010) +#define MCF5282_INTC_IPRH_INT35 (0x00000008) +#define MCF5282_INTC_IPRH_INT34 (0x00000004) +#define MCF5282_INTC_IPRH_INT33 (0x00000002) +#define MCF5282_INTC_IPRH_INT32 (0x00000001) + +#define MCF5282_INTC_IPRL_INT31 (0x80000000) +#define MCF5282_INTC_IPRL_INT30 (0x40000000) +#define MCF5282_INTC_IPRL_INT29 (0x20000000) +#define MCF5282_INTC_IPRL_INT28 (0x10000000) +#define MCF5282_INTC_IPRL_INT27 (0x08000000) +#define MCF5282_INTC_IPRL_INT26 (0x04000000) +#define MCF5282_INTC_IPRL_INT25 (0x02000000) +#define MCF5282_INTC_IPRL_INT24 (0x01000000) +#define MCF5282_INTC_IPRL_INT23 (0x00800000) +#define MCF5282_INTC_IPRL_INT22 (0x00400000) +#define MCF5282_INTC_IPRL_INT21 (0x00200000) +#define MCF5282_INTC_IPRL_INT20 (0x00100000) +#define MCF5282_INTC_IPRL_INT19 (0x00080000) +#define MCF5282_INTC_IPRL_INT18 (0x00040000) +#define MCF5282_INTC_IPRL_INT17 (0x00020000) +#define MCF5282_INTC_IPRL_INT16 (0x00010000) +#define MCF5282_INTC_IPRL_INT15 (0x00008000) +#define MCF5282_INTC_IPRL_INT14 (0x00004000) +#define MCF5282_INTC_IPRL_INT13 (0x00002000) +#define MCF5282_INTC_IPRL_INT12 (0x00001000) +#define MCF5282_INTC_IPRL_INT11 (0x00000800) +#define MCF5282_INTC_IPRL_INT10 (0x00000400) +#define MCF5282_INTC_IPRL_INT9 (0x00000200) +#define MCF5282_INTC_IPRL_INT8 (0x00000100) +#define MCF5282_INTC_IPRL_INT7 (0x00000080) +#define MCF5282_INTC_IPRL_INT6 (0x00000040) +#define MCF5282_INTC_IPRL_INT5 (0x00000020) +#define MCF5282_INTC_IPRL_INT4 (0x00000010) +#define MCF5282_INTC_IPRL_INT3 (0x00000008) +#define MCF5282_INTC_IPRL_INT2 (0x00000004) +#define MCF5282_INTC_IPRL_INT1 (0x00000002) + +#define MCF5282_INTC_IMRH_INT63 (0x80000000) +#define MCF5282_INTC_IMRH_INT62 (0x40000000) +#define MCF5282_INTC_IMRH_INT61 (0x20000000) +#define MCF5282_INTC_IMRH_INT60 (0x10000000) +#define MCF5282_INTC_IMRH_INT59 (0x08000000) +#define MCF5282_INTC_IMRH_INT58 (0x04000000) +#define MCF5282_INTC_IMRH_INT57 (0x02000000) +#define MCF5282_INTC_IMRH_INT56 (0x01000000) +#define MCF5282_INTC_IMRH_INT55 (0x00800000) +#define MCF5282_INTC_IMRH_INT54 (0x00400000) +#define MCF5282_INTC_IMRH_INT53 (0x00200000) +#define MCF5282_INTC_IMRH_INT52 (0x00100000) +#define MCF5282_INTC_IMRH_INT51 (0x00080000) +#define MCF5282_INTC_IMRH_INT50 (0x00040000) +#define MCF5282_INTC_IMRH_INT49 (0x00020000) +#define MCF5282_INTC_IMRH_INT48 (0x00010000) +#define MCF5282_INTC_IMRH_INT47 (0x00008000) +#define MCF5282_INTC_IMRH_INT46 (0x00004000) +#define MCF5282_INTC_IMRH_INT45 (0x00002000) +#define MCF5282_INTC_IMRH_INT44 (0x00001000) +#define MCF5282_INTC_IMRH_INT43 (0x00000800) +#define MCF5282_INTC_IMRH_INT42 (0x00000400) +#define MCF5282_INTC_IMRH_INT41 (0x00000200) +#define MCF5282_INTC_IMRH_INT40 (0x00000100) +#define MCF5282_INTC_IMRH_INT39 (0x00000080) +#define MCF5282_INTC_IMRH_INT38 (0x00000040) +#define MCF5282_INTC_IMRH_INT37 (0x00000020) +#define MCF5282_INTC_IMRH_INT36 (0x00000010) +#define MCF5282_INTC_IMRH_INT35 (0x00000008) +#define MCF5282_INTC_IMRH_INT34 (0x00000004) +#define MCF5282_INTC_IMRH_INT33 (0x00000002) +#define MCF5282_INTC_IMRH_INT32 (0x00000001) + +#define MCF5282_INTC_IMRL_INT31 (0x80000000) +#define MCF5282_INTC_IMRL_INT30 (0x40000000) +#define MCF5282_INTC_IMRL_INT29 (0x20000000) +#define MCF5282_INTC_IMRL_INT28 (0x10000000) +#define MCF5282_INTC_IMRL_INT27 (0x08000000) +#define MCF5282_INTC_IMRL_INT26 (0x04000000) +#define MCF5282_INTC_IMRL_INT25 (0x02000000) +#define MCF5282_INTC_IMRL_INT24 (0x01000000) +#define MCF5282_INTC_IMRL_INT23 (0x00800000) +#define MCF5282_INTC_IMRL_INT22 (0x00400000) +#define MCF5282_INTC_IMRL_INT21 (0x00200000) +#define MCF5282_INTC_IMRL_INT20 (0x00100000) +#define MCF5282_INTC_IMRL_INT19 (0x00080000) +#define MCF5282_INTC_IMRL_INT18 (0x00040000) +#define MCF5282_INTC_IMRL_INT17 (0x00020000) +#define MCF5282_INTC_IMRL_INT16 (0x00010000) +#define MCF5282_INTC_IMRL_INT15 (0x00008000) +#define MCF5282_INTC_IMRL_INT14 (0x00004000) +#define MCF5282_INTC_IMRL_INT13 (0x00002000) +#define MCF5282_INTC_IMRL_INT12 (0x00001000) +#define MCF5282_INTC_IMRL_INT11 (0x00000800) +#define MCF5282_INTC_IMRL_INT10 (0x00000400) +#define MCF5282_INTC_IMRL_INT9 (0x00000200) +#define MCF5282_INTC_IMRL_INT8 (0x00000100) +#define MCF5282_INTC_IMRL_INT7 (0x00000080) +#define MCF5282_INTC_IMRL_INT6 (0x00000040) +#define MCF5282_INTC_IMRL_INT5 (0x00000020) +#define MCF5282_INTC_IMRL_INT4 (0x00000010) +#define MCF5282_INTC_IMRL_INT3 (0x00000008) +#define MCF5282_INTC_IMRL_INT2 (0x00000004) +#define MCF5282_INTC_IMRL_INT1 (0x00000002) +#define MCF5282_INTC_IMRL_MASKALL (0x00000001) + +#define MCF5282_INTC_INTFRCH_INT63 (0x80000000) +#define MCF5282_INTC_INTFRCH_INT62 (0x40000000) +#define MCF5282_INTC_INTFRCH_INT61 (0x20000000) +#define MCF5282_INTC_INTFRCH_INT60 (0x10000000) +#define MCF5282_INTC_INTFRCH_INT59 (0x08000000) +#define MCF5282_INTC_INTFRCH_INT58 (0x04000000) +#define MCF5282_INTC_INTFRCH_INT57 (0x02000000) +#define MCF5282_INTC_INTFRCH_INT56 (0x01000000) +#define MCF5282_INTC_INTFRCH_INT55 (0x00800000) +#define MCF5282_INTC_INTFRCH_INT54 (0x00400000) +#define MCF5282_INTC_INTFRCH_INT53 (0x00200000) +#define MCF5282_INTC_INTFRCH_INT52 (0x00100000) +#define MCF5282_INTC_INTFRCH_INT51 (0x00080000) +#define MCF5282_INTC_INTFRCH_INT50 (0x00040000) +#define MCF5282_INTC_INTFRCH_INT49 (0x00020000) +#define MCF5282_INTC_INTFRCH_INT48 (0x00010000) +#define MCF5282_INTC_INTFRCH_INT47 (0x00008000) +#define MCF5282_INTC_INTFRCH_INT46 (0x00004000) +#define MCF5282_INTC_INTFRCH_INT45 (0x00002000) +#define MCF5282_INTC_INTFRCH_INT44 (0x00001000) +#define MCF5282_INTC_INTFRCH_INT43 (0x00000800) +#define MCF5282_INTC_INTFRCH_INT42 (0x00000400) +#define MCF5282_INTC_INTFRCH_INT41 (0x00000200) +#define MCF5282_INTC_INTFRCH_INT40 (0x00000100) +#define MCF5282_INTC_INTFRCH_INT39 (0x00000080) +#define MCF5282_INTC_INTFRCH_INT38 (0x00000040) +#define MCF5282_INTC_INTFRCH_INT37 (0x00000020) +#define MCF5282_INTC_INTFRCH_INT36 (0x00000010) +#define MCF5282_INTC_INTFRCH_INT35 (0x00000008) +#define MCF5282_INTC_INTFRCH_INT34 (0x00000004) +#define MCF5282_INTC_INTFRCH_INT33 (0x00000002) +#define MCF5282_INTC_INTFRCH_INT32 (0x00000001) + +#define MCF5282_INTC_INTFRCL_INT31 (0x80000000) +#define MCF5282_INTC_INTFRCL_INT30 (0x40000000) +#define MCF5282_INTC_INTFRCL_INT29 (0x20000000) +#define MCF5282_INTC_INTFRCL_INT28 (0x10000000) +#define MCF5282_INTC_INTFRCL_INT27 (0x08000000) +#define MCF5282_INTC_INTFRCL_INT26 (0x04000000) +#define MCF5282_INTC_INTFRCL_INT25 (0x02000000) +#define MCF5282_INTC_INTFRCL_INT24 (0x01000000) +#define MCF5282_INTC_INTFRCL_INT23 (0x00800000) +#define MCF5282_INTC_INTFRCL_INT22 (0x00400000) +#define MCF5282_INTC_INTFRCL_INT21 (0x00200000) +#define MCF5282_INTC_INTFRCL_INT20 (0x00100000) +#define MCF5282_INTC_INTFRCL_INT19 (0x00080000) +#define MCF5282_INTC_INTFRCL_INT18 (0x00040000) +#define MCF5282_INTC_INTFRCL_INT17 (0x00020000) +#define MCF5282_INTC_INTFRCL_INT16 (0x00010000) +#define MCF5282_INTC_INTFRCL_INT15 (0x00008000) +#define MCF5282_INTC_INTFRCL_INT14 (0x00004000) +#define MCF5282_INTC_INTFRCL_INT13 (0x00002000) +#define MCF5282_INTC_INTFRCL_INT12 (0x00001000) +#define MCF5282_INTC_INTFRCL_INT11 (0x00000800) +#define MCF5282_INTC_INTFRCL_INT10 (0x00000400) +#define MCF5282_INTC_INTFRCL_INT9 (0x00000200) +#define MCF5282_INTC_INTFRCL_INT8 (0x00000100) +#define MCF5282_INTC_INTFRCL_INT7 (0x00000080) +#define MCF5282_INTC_INTFRCL_INT6 (0x00000040) +#define MCF5282_INTC_INTFRCL_INT5 (0x00000020) +#define MCF5282_INTC_INTFRCL_INT4 (0x00000010) +#define MCF5282_INTC_INTFRCL_INT3 (0x00000008) +#define MCF5282_INTC_INTFRCL_INT2 (0x00000004) +#define MCF5282_INTC_INTFRCL_INT1 (0x00000002) + +#define MCF5282_INTC_IRLR_IRQ7 (0x80) +#define MCF5282_INTC_IRLR_IRQ6 (0x40) +#define MCF5282_INTC_IRLR_IRQ5 (0x20) +#define MCF5282_INTC_IRLR_IRQ4 (0x10) +#define MCF5282_INTC_IRLR_IRQ3 (0x08) +#define MCF5282_INTC_IRLR_IRQ2 (0x04) +#define MCF5282_INTC_IRLR_IRQ1 (0x02) + +#define MCF5282_INTC_ICR_IL(x) (((x)&0x07)<<3) +#define MCF5282_INTC_ICR_IP(x) (((x)&0x07)<<0) + +/********************************************************************* +* +* Global Interrupt Acknowledge Cycle (GIAC) Registers +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_GIAC_GSWIACK (*(vuint8 *)(void *)(&__IPSBAR[0x0FE0])) +#define MCF5282_GIAC_GL1IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0FE4])) +#define MCF5282_GIAC_GL2IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0FE8])) +#define MCF5282_GIAC_GL3IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0FEC])) +#define MCF5282_GIAC_GL4IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0FF0])) +#define MCF5282_GIAC_GL5IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0FF4])) +#define MCF5282_GIAC_GL6IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0FF8])) +#define MCF5282_GIAC_GL7IACK (*(vuint8 *)(void *)(&__IPSBAR[0x0FFC])) + +/* Bit level definitions and macros */ + +/* To do - add bit level definintions */ + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_FEC_EIR (*(vuint32 *)(void *)(&__IPSBAR[0x1004])) +#define MCF5282_FEC_EIMR (*(vuint32 *)(void *)(&__IPSBAR[0x1008])) +#define MCF5282_FEC_RDAR (*(vuint32 *)(void *)(&__IPSBAR[0x1010])) +#define MCF5282_FEC_TDAR (*(vuint32 *)(void *)(&__IPSBAR[0x1014])) +#define MCF5282_FEC_ECR (*(vuint32 *)(void *)(&__IPSBAR[0x1024])) +#define MCF5282_FEC_MMFR (*(vuint32 *)(void *)(&__IPSBAR[0x1040])) +#define MCF5282_FEC_MSCR (*(vuint32 *)(void *)(&__IPSBAR[0x1044])) +#define MCF5282_FEC_MIBC (*(vuint32 *)(void *)(&__IPSBAR[0x1064])) +#define MCF5282_FEC_RCR (*(vuint32 *)(void *)(&__IPSBAR[0x1084])) +#define MCF5282_FEC_TCR (*(vuint32 *)(void *)(&__IPSBAR[0x10C4])) +#define MCF5282_FEC_PALR (*(vuint32 *)(void *)(&__IPSBAR[0x10E4])) +#define MCF5282_FEC_PAUR (*(vuint32 *)(void *)(&__IPSBAR[0x10E8])) +#define MCF5282_FEC_OPD (*(vuint32 *)(void *)(&__IPSBAR[0x10EC])) +#define MCF5282_FEC_IAUR (*(vuint32 *)(void *)(&__IPSBAR[0x1118])) +#define MCF5282_FEC_IALR (*(vuint32 *)(void *)(&__IPSBAR[0x111C])) +#define MCF5282_FEC_GAUR (*(vuint32 *)(void *)(&__IPSBAR[0x1120])) +#define MCF5282_FEC_GALR (*(vuint32 *)(void *)(&__IPSBAR[0x1124])) +#define MCF5282_FEC_TFWR (*(vuint32 *)(void *)(&__IPSBAR[0x1144])) +#define MCF5282_FEC_FRBR (*(vuint32 *)(void *)(&__IPSBAR[0x114C])) +#define MCF5282_FEC_FRSR (*(vuint32 *)(void *)(&__IPSBAR[0x1150])) +#define MCF5282_FEC_ERDSR (*(vuint32 *)(void *)(&__IPSBAR[0x1180])) +#define MCF5282_FEC_ETDSR (*(vuint32 *)(void *)(&__IPSBAR[0x1184])) +#define MCF5282_FEC_EMRBR (*(vuint32 *)(void *)(&__IPSBAR[0x1188])) + +#define MCF5282_FEC_RMON_T_DROP (*(vuint32 *)(void *)(&__IPSBAR[0x1200])) +#define MCF5282_FEC_RMON_T_PACKETS (*(vuint32 *)(void *)(&__IPSBAR[0x1204])) +#define MCF5282_FEC_RMON_T_BC_PKT (*(vuint32 *)(void *)(&__IPSBAR[0x1208])) +#define MCF5282_FEC_RMON_T_MC_PKT (*(vuint32 *)(void *)(&__IPSBAR[0x120C])) +#define MCF5282_FEC_RMON_T_CRC_ALIGN (*(vuint32 *)(void *)(&__IPSBAR[0x1210])) +#define MCF5282_FEC_RMON_T_UNDERSIZE (*(vuint32 *)(void *)(&__IPSBAR[0x1214])) +#define MCF5282_FEC_RMON_T_OVERSIZE (*(vuint32 *)(void *)(&__IPSBAR[0x1218])) +#define MCF5282_FEC_RMON_T_FRAG (*(vuint32 *)(void *)(&__IPSBAR[0x121C])) +#define MCF5282_FEC_RMON_T_JAB (*(vuint32 *)(void *)(&__IPSBAR[0x1220])) +#define MCF5282_FEC_RMON_T_COL (*(vuint32 *)(void *)(&__IPSBAR[0x1224])) +#define MCF5282_FEC_RMON_T_P64 (*(vuint32 *)(void *)(&__IPSBAR[0x1228])) +#define MCF5282_FEC_RMON_T_P65TO127 (*(vuint32 *)(void *)(&__IPSBAR[0x122C])) +#define MCF5282_FEC_RMON_T_P128TO255 (*(vuint32 *)(void *)(&__IPSBAR[0x1230])) +#define MCF5282_FEC_RMON_T_P256TO511 (*(vuint32 *)(void *)(&__IPSBAR[0x1234])) +#define MCF5282_FEC_RMON_T_P512TO1023 (*(vuint32 *)(void *)(&__IPSBAR[0x1238])) +#define MCF5282_FEC_RMON_T_P1024TO2047 (*(vuint32 *)(void *)(&__IPSBAR[0x123C])) +#define MCF5282_FEC_RMON_T_P_GTE2048 (*(vuint32 *)(void *)(&__IPSBAR[0x1240])) +#define MCF5282_FEC_RMON_T_OCTETS (*(vuint32 *)(void *)(&__IPSBAR[0x1244])) +#define MCF5282_FEC_IEEE_T_DROP (*(vuint32 *)(void *)(&__IPSBAR[0x1248])) +#define MCF5282_FEC_IEEE_T_FRAME_OK (*(vuint32 *)(void *)(&__IPSBAR[0x124C])) +#define MCF5282_FEC_IEEE_T_1COL (*(vuint32 *)(void *)(&__IPSBAR[0x1250])) +#define MCF5282_FEC_IEEE_T_MCOL (*(vuint32 *)(void *)(&__IPSBAR[0x1254])) +#define MCF5282_FEC_IEEE_T_DEF (*(vuint32 *)(void *)(&__IPSBAR[0x1258])) +#define MCF5282_FEC_IEEE_T_LCOL (*(vuint32 *)(void *)(&__IPSBAR[0x125C])) +#define MCF5282_FEC_IEEE_T_EXCOL (*(vuint32 *)(void *)(&__IPSBAR[0x1260])) +#define MCF5282_FEC_IEEE_T_MACERR (*(vuint32 *)(void *)(&__IPSBAR[0x1264])) +#define MCF5282_FEC_IEEE_T_CSERR (*(vuint32 *)(void *)(&__IPSBAR[0x1268])) +#define MCF5282_FEC_IEEE_T_SQE (*(vuint32 *)(void *)(&__IPSBAR[0x126C])) +#define MCF5282_FEC_IEEE_T_FDXFC (*(vuint32 *)(void *)(&__IPSBAR[0x1270])) +#define MCF5282_FEC_IEEE_T_OCTETS_OK (*(vuint32 *)(void *)(&__IPSBAR[0x1274])) +#define MCF5282_FEC_RMON_R_PACKETS (*(vuint32 *)(void *)(&__IPSBAR[0x1284])) +#define MCF5282_FEC_RMON_R_BC_PKT (*(vuint32 *)(void *)(&__IPSBAR[0x1288])) +#define MCF5282_FEC_RMON_R_MC_PKT (*(vuint32 *)(void *)(&__IPSBAR[0x128C])) +#define MCF5282_FEC_RMON_R_CRC_ALIGN (*(vuint32 *)(void *)(&__IPSBAR[0x1290])) +#define MCF5282_FEC_RMON_R_UNDERSIZE (*(vuint32 *)(void *)(&__IPSBAR[0x1294])) +#define MCF5282_FEC_RMON_R_OVERSIZE (*(vuint32 *)(void *)(&__IPSBAR[0x1298])) +#define MCF5282_FEC_RMON_R_FRAG (*(vuint32 *)(void *)(&__IPSBAR[0x129C])) +#define MCF5282_FEC_RMON_R_JAB (*(vuint32 *)(void *)(&__IPSBAR[0x12A0])) +#define MCF5282_FEC_RMON_R_RESVD_0 (*(vuint32 *)(void *)(&__IPSBAR[0x12A4])) +#define MCF5282_FEC_RMON_R_P64 (*(vuint32 *)(void *)(&__IPSBAR[0x12A8])) +#define MCF5282_FEC_RMON_R_P65T0127 (*(vuint32 *)(void *)(&__IPSBAR[0x12AC])) +#define MCF5282_FEC_RMON_R_P128TO255 (*(vuint32 *)(void *)(&__IPSBAR[0x12B0])) +#define MCF5282_FEC_RMON_R_P256TO511 (*(vuint32 *)(void *)(&__IPSBAR[0x12B4])) +#define MCF5282_FEC_RMON_R_P512TO1023 (*(vuint32 *)(void *)(&__IPSBAR[0x12B8])) +#define MCF5282_FEC_RMON_R_P1024TO2047 (*(vuint32 *)(void *)(&__IPSBAR[0x12BC])) +#define MCF5282_FEC_RMON_R_GTE2048 (*(vuint32 *)(void *)(&__IPSBAR[0x12C0])) +#define MCF5282_FEC_RMON_R_OCTETS (*(vuint32 *)(void *)(&__IPSBAR[0x12C4])) +#define MCF5282_FEC_IEEE_R_DROP (*(vuint32 *)(void *)(&__IPSBAR[0x12C8])) +#define MCF5282_FEC_IEEE_R_FRAME_OK (*(vuint32 *)(void *)(&__IPSBAR[0x12CC])) +#define MCF5282_FEC_IEEE_R_CRC (*(vuint32 *)(void *)(&__IPSBAR[0x12D0])) +#define MCF5282_FEC_IEEE_R_ALIGN (*(vuint32 *)(void *)(&__IPSBAR[0x12D4])) +#define MCF5282_FEC_IEEE_R_MACERR (*(vuint32 *)(void *)(&__IPSBAR[0x12D8])) +#define MCF5282_FEC_IEEE_R_FDXFC (*(vuint32 *)(void *)(&__IPSBAR[0x12DC])) +#define MCF5282_FEC_IEEE_R_OCTETS_OK (*(vuint32 *)(void *)(&__IPSBAR[0x12E0])) + +/* Bit level definitions and macros */ +#define MCF5282_FEC_EIR_HBERR (0x80000000) +#define MCF5282_FEC_EIR_BABR (0x40000000) +#define MCF5282_FEC_EIR_BABT (0x20000000) +#define MCF5282_FEC_EIR_GRA (0x10000000) +#define MCF5282_FEC_EIR_TXF (0x08000000) +#define MCF5282_FEC_EIR_TXB (0x04000000) +#define MCF5282_FEC_EIR_RXF (0x02000000) +#define MCF5282_FEC_EIR_RXB (0x01000000) +#define MCF5282_FEC_EIR_MII (0x00800000) +#define MCF5282_FEC_EIR_EBERR (0x00400000) +#define MCF5282_FEC_EIR_LC (0x00200000) +#define MCF5282_FEC_EIR_RL (0x00100000) +#define MCF5282_FEC_EIR_UN (0x00080000) + +#define MCF5282_FEC_EIMR_HBERR (0x80000000) +#define MCF5282_FEC_EIMR_BABR (0x40000000) +#define MCF5282_FEC_EIMR_BABT (0x20000000) +#define MCF5282_FEC_EIMR_GRA (0x10000000) +#define MCF5282_FEC_EIMR_TXF (0x08000000) +#define MCF5282_FEC_EIMR_TXB (0x04000000) +#define MCF5282_FEC_EIMR_RXF (0x02000000) +#define MCF5282_FEC_EIMR_RXB (0x01000000) +#define MCF5282_FEC_EIMR_MII (0x00800000) +#define MCF5282_FEC_EIMR_EBERR (0x00400000) +#define MCF5282_FEC_EIMR_LC (0x00200000) +#define MCF5282_FEC_EIMR_RL (0x00100000) +#define MCF5282_FEC_EIMR_UN (0x00080000) + +#define MCF5282_FEC_RDAR_R_DES_ACTIVE (0x01000000) + +#define MCF5282_FEC_TDAR_X_DES_ACTIVE (0x01000000) + +#define MCF5282_FEC_ECR_ETHER_EN (0x00000002) +#define MCF5282_FEC_ECR_RESET (0x00000001) + +#define MCF5282_FEC_MMFR_ST (0x40000000) +#define MCF5282_FEC_MMFR_OP_RD (0x20000000) +#define MCF5282_FEC_MMFR_OP_WR (0x10000000) +#define MCF5282_FEC_MMFR_PA(x) (((x)&0x1F)<<23) +#define MCF5282_FEC_MMFR_RA(x) (((x)&0x1F)<<18) +#define MCF5282_FEC_MMFR_TA (0x00020000) +#define MCF5282_FEC_MMFR_DATA(x) (((x)&0xFFFF)) + +#define MCF5282_FEC_MSCR_DIS_PREAMBLE (0x00000008) +#define MCF5282_FEC_MSCR_MII_SPEED(x) (((x)&0x1F)<<1) + +#define MCF5282_FEC_MIBC_MIB_DISABLE (0x80000000) +#define MCF5282_FEC_MIBC_MIB_IDLE (0x40000000) + +#define MCF5282_FEC_RCR_MAX_FL(x) (((x)&0x07FF)<<16) +#define MCF5282_FEC_RCR_FCE (0x00000020) +#define MCF5282_FEC_RCR_BC_REJ (0x00000010) +#define MCF5282_FEC_RCR_PROM (0x00000008) +#define MCF5282_FEC_RCR_MII_MODE (0x00000004) +#define MCF5282_FEC_RCR_DRT (0x00000002) +#define MCF5282_FEC_RCR_LOOP (0x00000001) + +#define MCF5282_FEC_TCR_RFC_PAUSE (0x00000010) +#define MCF5282_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF5282_FEC_TCR_FDEN (0x00000004) +#define MCF5282_FEC_TCR_HBC (0x00000002) +#define MCF5282_FEC_TCR_GTS (0x00000001) + +#define MCF5282_FEC_PALR_BYTE0(x) (((x)&0xFF)<<24) +#define MCF5282_FEC_PALR_BYTE1(x) (((x)&0xFF)<<16) +#define MCF5282_FEC_PALR_BYTE2(x) (((x)&0xFF)<<8) +#define MCF5282_FEC_PALR_BYTE3(x) (((x)&0xFF)) + +#define MCF5282_FEC_PAUR_BYTE4(x) (((x)&0xFF)<<24) +#define MCF5282_FEC_PAUR_BYTE5(x) (((x)&0xFF)<<16) + +#define MCF5282_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)) + +#define MCF5282_FEC_TFWR_X_WMRK_64 (0x00000001) +#define MCF5282_FEC_TFWR_X_WMRK_128 (0x00000002) +#define MCF5282_FEC_TFWR_X_WMRK_192 (0x00000003) + +#define MCF5282_FEC_EMRBR_R_BUF_SIZE(x) (((x)&7F)<<4) + +#define MCF5282_FEC_TxBD_R 0x8000 +#define MCF5282_FEC_TxBD_BUSY 0x4000 +#define MCF5282_FEC_TxBD_TO1 0x4000 +#define MCF5282_FEC_TxBD_W 0x2000 +#define MCF5282_FEC_TxBD_TO2 0x1000 +#define MCF5282_FEC_TxBD_FIRST 0x1000 +#define MCF5282_FEC_TxBD_L 0x0800 +#define MCF5282_FEC_TxBD_TC 0x0400 +#define MCF5282_FEC_TxBD_DEF 0x0200 +#define MCF5282_FEC_TxBD_HB 0x0100 +#define MCF5282_FEC_TxBD_LC 0x0080 +#define MCF5282_FEC_TxBD_RL 0x0040 +#define MCF5282_FEC_TxBD_UN 0x0002 +#define MCF5282_FEC_TxBD_CSL 0x0001 + +#define MCF5282_FEC_RxBD_E 0x8000 +#define MCF5282_FEC_RxBD_INUSE 0x4000 +#define MCF5282_FEC_RxBD_R01 0x4000 +#define MCF5282_FEC_RxBD_W 0x2000 +#define MCF5282_FEC_RxBD_R02 0x1000 +#define MCF5282_FEC_RxBD_L 0x0800 +#define MCF5282_FEC_RxBD_M 0x0100 +#define MCF5282_FEC_RxBD_BC 0x0080 +#define MCF5282_FEC_RxBD_MC 0x0040 +#define MCF5282_FEC_RxBD_LG 0x0020 +#define MCF5282_FEC_RxBD_NO 0x0010 +#define MCF5282_FEC_RxBD_CR 0x0004 +#define MCF5282_FEC_RxBD_OV 0x0002 +#define MCF5282_FEC_RxBD_TR 0x0001 + +/********************************************************************* +* +* General Purpose I/O (GPIO) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_GPIO_PORTA (*(vuint8 *)(void *)(&__IPSBAR[0x100000])) +#define MCF5282_GPIO_PORTB (*(vuint8 *)(void *)(&__IPSBAR[0x100001])) +#define MCF5282_GPIO_PORTC (*(vuint8 *)(void *)(&__IPSBAR[0x100002])) +#define MCF5282_GPIO_PORTD (*(vuint8 *)(void *)(&__IPSBAR[0x100003])) +#define MCF5282_GPIO_PORTE (*(vuint8 *)(void *)(&__IPSBAR[0x100004])) +#define MCF5282_GPIO_PORTF (*(vuint8 *)(void *)(&__IPSBAR[0x100005])) +#define MCF5282_GPIO_PORTG (*(vuint8 *)(void *)(&__IPSBAR[0x100006])) +#define MCF5282_GPIO_PORTH (*(vuint8 *)(void *)(&__IPSBAR[0x100007])) +#define MCF5282_GPIO_PORTJ (*(vuint8 *)(void *)(&__IPSBAR[0x100008])) +#define MCF5282_GPIO_PORTDD (*(vuint8 *)(void *)(&__IPSBAR[0x100009])) +#define MCF5282_GPIO_PORTEH (*(vuint8 *)(void *)(&__IPSBAR[0x10000A])) +#define MCF5282_GPIO_PORTEL (*(vuint8 *)(void *)(&__IPSBAR[0x10000B])) +#define MCF5282_GPIO_PORTAS (*(vuint8 *)(void *)(&__IPSBAR[0x10000C])) +#define MCF5282_GPIO_PORTQS (*(vuint8 *)(void *)(&__IPSBAR[0x10000D])) +#define MCF5282_GPIO_PORTSD (*(vuint8 *)(void *)(&__IPSBAR[0x10000E])) +#define MCF5282_GPIO_PORTTC (*(vuint8 *)(void *)(&__IPSBAR[0x10000F])) +#define MCF5282_GPIO_PORTTD (*(vuint8 *)(void *)(&__IPSBAR[0x100010])) +#define MCF5282_GPIO_PORTUA (*(vuint8 *)(void *)(&__IPSBAR[0x100011])) + +#define MCF5282_GPIO_DDRA (*(vuint8 *)(void *)(&__IPSBAR[0x100014])) +#define MCF5282_GPIO_DDRB (*(vuint8 *)(void *)(&__IPSBAR[0x100015])) +#define MCF5282_GPIO_DDRC (*(vuint8 *)(void *)(&__IPSBAR[0x100016])) +#define MCF5282_GPIO_DDRD (*(vuint8 *)(void *)(&__IPSBAR[0x100017])) +#define MCF5282_GPIO_DDRE (*(vuint8 *)(void *)(&__IPSBAR[0x100018])) +#define MCF5282_GPIO_DDRF (*(vuint8 *)(void *)(&__IPSBAR[0x100019])) +#define MCF5282_GPIO_DDRG (*(vuint8 *)(void *)(&__IPSBAR[0x10001A])) +#define MCF5282_GPIO_DDRH (*(vuint8 *)(void *)(&__IPSBAR[0x10001B])) +#define MCF5282_GPIO_DDRJ (*(vuint8 *)(void *)(&__IPSBAR[0x10001C])) +#define MCF5282_GPIO_DDRDD (*(vuint8 *)(void *)(&__IPSBAR[0x10001D])) +#define MCF5282_GPIO_DDREH (*(vuint8 *)(void *)(&__IPSBAR[0x10001E])) +#define MCF5282_GPIO_DDREL (*(vuint8 *)(void *)(&__IPSBAR[0x10001F])) +#define MCF5282_GPIO_DDRAS (*(vuint8 *)(void *)(&__IPSBAR[0x100020])) +#define MCF5282_GPIO_DDRQS (*(vuint8 *)(void *)(&__IPSBAR[0x100021])) +#define MCF5282_GPIO_DDRSD (*(vuint8 *)(void *)(&__IPSBAR[0x100022])) +#define MCF5282_GPIO_DDRTC (*(vuint8 *)(void *)(&__IPSBAR[0x100023])) +#define MCF5282_GPIO_DDRTD (*(vuint8 *)(void *)(&__IPSBAR[0x100024])) +#define MCF5282_GPIO_DDRUA (*(vuint8 *)(void *)(&__IPSBAR[0x100025])) + +#define MCF5282_GPIO_PORTAP (*(vuint8 *)(void *)(&__IPSBAR[0x100028])) +#define MCF5282_GPIO_PORTBP (*(vuint8 *)(void *)(&__IPSBAR[0x100029])) +#define MCF5282_GPIO_PORTCP (*(vuint8 *)(void *)(&__IPSBAR[0x10002A])) +#define MCF5282_GPIO_PORTDP (*(vuint8 *)(void *)(&__IPSBAR[0x10002B])) +#define MCF5282_GPIO_PORTEP (*(vuint8 *)(void *)(&__IPSBAR[0x10002C])) +#define MCF5282_GPIO_PORTFP (*(vuint8 *)(void *)(&__IPSBAR[0x10002D])) +#define MCF5282_GPIO_PORTGP (*(vuint8 *)(void *)(&__IPSBAR[0x10002E])) +#define MCF5282_GPIO_PORTHP (*(vuint8 *)(void *)(&__IPSBAR[0x10002F])) +#define MCF5282_GPIO_PORTJP (*(vuint8 *)(void *)(&__IPSBAR[0x100030])) +#define MCF5282_GPIO_PORTDDP (*(vuint8 *)(void *)(&__IPSBAR[0x100031])) +#define MCF5282_GPIO_PORTEHP (*(vuint8 *)(void *)(&__IPSBAR[0x100032])) +#define MCF5282_GPIO_PORTELP (*(vuint8 *)(void *)(&__IPSBAR[0x100033])) +#define MCF5282_GPIO_PORTASP (*(vuint8 *)(void *)(&__IPSBAR[0x100034])) +#define MCF5282_GPIO_PORTQSP (*(vuint8 *)(void *)(&__IPSBAR[0x100035])) +#define MCF5282_GPIO_PORTSDP (*(vuint8 *)(void *)(&__IPSBAR[0x100036])) +#define MCF5282_GPIO_PORTTCP (*(vuint8 *)(void *)(&__IPSBAR[0x100037])) +#define MCF5282_GPIO_PORTTDP (*(vuint8 *)(void *)(&__IPSBAR[0x100038])) +#define MCF5282_GPIO_PORTUAP (*(vuint8 *)(void *)(&__IPSBAR[0x100039])) + +#define MCF5282_GPIO_SETA (*(vuint8 *)(void *)(&__IPSBAR[0x100028])) +#define MCF5282_GPIO_SETB (*(vuint8 *)(void *)(&__IPSBAR[0x100029])) +#define MCF5282_GPIO_SETC (*(vuint8 *)(void *)(&__IPSBAR[0x10002A])) +#define MCF5282_GPIO_SETD (*(vuint8 *)(void *)(&__IPSBAR[0x10002B])) +#define MCF5282_GPIO_SETE (*(vuint8 *)(void *)(&__IPSBAR[0x10002C])) +#define MCF5282_GPIO_SETF (*(vuint8 *)(void *)(&__IPSBAR[0x10002D])) +#define MCF5282_GPIO_SETG (*(vuint8 *)(void *)(&__IPSBAR[0x10002E])) +#define MCF5282_GPIO_SETH (*(vuint8 *)(void *)(&__IPSBAR[0x10002F])) +#define MCF5282_GPIO_SETJ (*(vuint8 *)(void *)(&__IPSBAR[0x100030])) +#define MCF5282_GPIO_SETDD (*(vuint8 *)(void *)(&__IPSBAR[0x100031])) +#define MCF5282_GPIO_SETEH (*(vuint8 *)(void *)(&__IPSBAR[0x100032])) +#define MCF5282_GPIO_SETEL (*(vuint8 *)(void *)(&__IPSBAR[0x100033])) +#define MCF5282_GPIO_SETAS (*(vuint8 *)(void *)(&__IPSBAR[0x100034])) +#define MCF5282_GPIO_SETQS (*(vuint8 *)(void *)(&__IPSBAR[0x100035])) +#define MCF5282_GPIO_SETSD (*(vuint8 *)(void *)(&__IPSBAR[0x100036])) +#define MCF5282_GPIO_SETTC (*(vuint8 *)(void *)(&__IPSBAR[0x100037])) +#define MCF5282_GPIO_SETTD (*(vuint8 *)(void *)(&__IPSBAR[0x100038])) +#define MCF5282_GPIO_SETUA (*(vuint8 *)(void *)(&__IPSBAR[0x100039])) + +#define MCF5282_GPIO_CLRA (*(vuint8 *)(void *)(&__IPSBAR[0x10003C])) +#define MCF5282_GPIO_CLRB (*(vuint8 *)(void *)(&__IPSBAR[0x10003D])) +#define MCF5282_GPIO_CLRC (*(vuint8 *)(void *)(&__IPSBAR[0x10003E])) +#define MCF5282_GPIO_CLRD (*(vuint8 *)(void *)(&__IPSBAR[0x10003F])) +#define MCF5282_GPIO_CLRE (*(vuint8 *)(void *)(&__IPSBAR[0x100040])) +#define MCF5282_GPIO_CLRF (*(vuint8 *)(void *)(&__IPSBAR[0x100041])) +#define MCF5282_GPIO_CLRG (*(vuint8 *)(void *)(&__IPSBAR[0x100042])) +#define MCF5282_GPIO_CLRH (*(vuint8 *)(void *)(&__IPSBAR[0x100043])) +#define MCF5282_GPIO_CLRJ (*(vuint8 *)(void *)(&__IPSBAR[0x100044])) +#define MCF5282_GPIO_CLRDD (*(vuint8 *)(void *)(&__IPSBAR[0x100045])) +#define MCF5282_GPIO_CLREH (*(vuint8 *)(void *)(&__IPSBAR[0x100046])) +#define MCF5282_GPIO_CLREL (*(vuint8 *)(void *)(&__IPSBAR[0x100047])) +#define MCF5282_GPIO_CLRAS (*(vuint8 *)(void *)(&__IPSBAR[0x100048])) +#define MCF5282_GPIO_CLRQS (*(vuint8 *)(void *)(&__IPSBAR[0x100049])) +#define MCF5282_GPIO_CLRSD (*(vuint8 *)(void *)(&__IPSBAR[0x10004A])) +#define MCF5282_GPIO_CLRTC (*(vuint8 *)(void *)(&__IPSBAR[0x10004B])) +#define MCF5282_GPIO_CLRTD (*(vuint8 *)(void *)(&__IPSBAR[0x10004C])) +#define MCF5282_GPIO_CLRUA (*(vuint8 *)(void *)(&__IPSBAR[0x10004D])) + +#define MCF5282_GPIO_PBCDPAR (*(vuint8 *)(void *)(&__IPSBAR[0x100050])) +#define MCF5282_GPIO_PFPAR (*(vuint8 *)(void *)(&__IPSBAR[0x100051])) +#define MCF5282_GPIO_PEPAR (*(vuint16 *)(void *)(&__IPSBAR[0x100052])) +#define MCF5282_GPIO_PJPAR (*(vuint8 *)(void *)(&__IPSBAR[0x100054])) +#define MCF5282_GPIO_PSDPAR (*(vuint8 *)(void *)(&__IPSBAR[0x100055])) +#define MCF5282_GPIO_PASPAR (*(vuint16 *)(void *)(&__IPSBAR[0x100056])) +#define MCF5282_GPIO_PEHLPAR (*(vuint8 *)(void *)(&__IPSBAR[0x100058])) +#define MCF5282_GPIO_PQSPAR (*(vuint8 *)(void *)(&__IPSBAR[0x100059])) +#define MCF5282_GPIO_PTCPAR (*(vuint8 *)(void *)(&__IPSBAR[0x10005A])) +#define MCF5282_GPIO_PTDPAR (*(vuint8 *)(void *)(&__IPSBAR[0x10005B])) +#define MCF5282_GPIO_PUAPAR (*(vuint8 *)(void *)(&__IPSBAR[0x10005C])) + +/* Bit level definitions and macros */ +#define MCF5282_GPIO_PORTx7 (0x80) +#define MCF5282_GPIO_PORTx6 (0x40) +#define MCF5282_GPIO_PORTx5 (0x20) +#define MCF5282_GPIO_PORTx4 (0x10) +#define MCF5282_GPIO_PORTx3 (0x08) +#define MCF5282_GPIO_PORTx2 (0x04) +#define MCF5282_GPIO_PORTx1 (0x02) +#define MCF5282_GPIO_PORTx0 (0x01) +#define MCF5282_GPIO_PORTx(x) (0x01<