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grlib/l2c: Fix whitespace

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No functional change
This commit is contained in:
Martin Åberg
2024-01-16 15:06:26 +01:00
committed by Kinsey Moore
parent e5854b2a69
commit ed55634d51
1 changed files with 84 additions and 84 deletions
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168
bsps/shared/grlib/l2c/l2c.c
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@@ -52,11 +52,11 @@
#ifdef DEBUG #ifdef DEBUG
#define DBG(x...) printf(x) #define DBG(x...) printf(x)
#else #else
#define DBG(x...) #define DBG(x...)
#endif #endif
/* /*
* L2CACHE CTRL register fields * L2CACHE CTRL register fields
*/ */
#define L2C_CTRL_EN (0x1 << L2C_CTRL_EN_BIT) #define L2C_CTRL_EN (0x1 << L2C_CTRL_EN_BIT)
#define L2C_CTRL_EDAC (0x1 << L2C_CTRL_EDAC_BIT) #define L2C_CTRL_EDAC (0x1 << L2C_CTRL_EDAC_BIT)
@@ -83,7 +83,7 @@
#define L2C_CTRL_HP_BIT 0 #define L2C_CTRL_HP_BIT 0
/* /*
* L2CACHE STATUS register fields * L2CACHE STATUS register fields
*/ */
#define L2C_STAT_LS (0x1 << L2C_STAT_LS_BIT) #define L2C_STAT_LS (0x1 << L2C_STAT_LS_BIT)
#define L2C_STAT_AT (0x1 << L2C_STAT_AT_BIT) #define L2C_STAT_AT (0x1 << L2C_STAT_AT_BIT)
@@ -102,7 +102,7 @@
#define L2C_STAT_WAY_BIT 0 #define L2C_STAT_WAY_BIT 0
/* /*
* L2CACHE MTRR register fields * L2CACHE MTRR register fields
*/ */
#define L2C_MTRR_ADDR (0x3fff << L2C_MTRR_ADDR_BIT) #define L2C_MTRR_ADDR (0x3fff << L2C_MTRR_ADDR_BIT)
#define L2C_MTRR_ACC (0x3 << L2C_MTRR_ACC_BIT) #define L2C_MTRR_ACC (0x3 << L2C_MTRR_ACC_BIT)
@@ -127,7 +127,7 @@
#define REG_READ(addr) (*(volatile unsigned int *)(addr)) #define REG_READ(addr) (*(volatile unsigned int *)(addr))
/* /*
* L2CACHE FLUSHMEM register fields * L2CACHE FLUSHMEM register fields
*/ */
#define L2C_FLUSH_ADDR (0x7ffffff << L2C_FLUSH_ADDR_BIT) #define L2C_FLUSH_ADDR (0x7ffffff << L2C_FLUSH_ADDR_BIT)
#define L2C_FLUSH_DI (0x1 << L2C_FLUSH_DI_BIT) #define L2C_FLUSH_DI (0x1 << L2C_FLUSH_DI_BIT)
@@ -145,7 +145,7 @@
#define L2C_FLUSH_FMODE_INV_WB_ALL (0x7 << L2C_FLUSH_FMODE_BIT) #define L2C_FLUSH_FMODE_INV_WB_ALL (0x7 << L2C_FLUSH_FMODE_BIT)
/* /*
* L2CACHE FLUSSETINDEX register fields * L2CACHE FLUSSETINDEX register fields
*/ */
#define L2C_FLUSHSI_INDEX (0xffff << L2C_FLUSHSI_INDEX_BIT) #define L2C_FLUSHSI_INDEX (0xffff << L2C_FLUSHSI_INDEX_BIT)
#define L2C_FLUSHSI_TAG (0x3fffff << L2C_FLUSHSI_TAG_BIT) #define L2C_FLUSHSI_TAG (0x3fffff << L2C_FLUSHSI_TAG_BIT)
@@ -175,7 +175,7 @@
#define L2C_FLUSHSI_FMODE_WAY_UPDATE_WB_ALL (0x3 << L2C_FLUSHSI_FMODE_BIT) #define L2C_FLUSHSI_FMODE_WAY_UPDATE_WB_ALL (0x3 << L2C_FLUSHSI_FMODE_BIT)
/* /*
* L2CACHE ERROR register fields * L2CACHE ERROR register fields
*/ */
#define L2C_ERROR_AHBM (0xf << L2C_ERROR_AHBM_BIT) #define L2C_ERROR_AHBM (0xf << L2C_ERROR_AHBM_BIT)
#define L2C_ERROR_SCRUB (0x1 << L2C_ERROR_SCRUB_BIT) #define L2C_ERROR_SCRUB (0x1 << L2C_ERROR_SCRUB_BIT)
@@ -222,34 +222,34 @@
#define L2C_ERROR_RST_BIT 0 #define L2C_ERROR_RST_BIT 0
/* /*
* L2CACHE DATA CHECK BITS register fields * L2CACHE DATA CHECK BITS register fields
*/ */
#define L2C_DCB_CB (0xfffffff << L2C_DCB_CB_BIT) #define L2C_DCB_CB (0xfffffff << L2C_DCB_CB_BIT)
#define L2C_DCB_CB_BIT 0 #define L2C_DCB_CB_BIT 0
/* /*
* L2CACHE SCRUB register fields * L2CACHE SCRUB register fields
*/ */
#define L2C_SCRUB_INDEX (0xffff << L2C_SCRUB_INDEX_BIT) #define L2C_SCRUB_INDEX (0xffff << L2C_SCRUB_INDEX_BIT)
#define L2C_SCRUB_WAY (0x3 << L2C_SCRUB_WAY_BIT) #define L2C_SCRUB_WAY (0x3 << L2C_SCRUB_WAY_BIT)
#define L2C_SCRUB_PEN (0x1 << L2C_SCRUB_PEN_BIT) #define L2C_SCRUB_PEN (0x1 << L2C_SCRUB_PEN_BIT)
#define L2C_SCRUB_EN (0x1 << L2C_SCRUB_EN_BIT) #define L2C_SCRUB_EN (0x1 << L2C_SCRUB_EN_BIT)
#define L2C_SCRUB_INDEX_BIT 16 #define L2C_SCRUB_INDEX_BIT 16
#define L2C_SCRUB_WAY_BIT 2 #define L2C_SCRUB_WAY_BIT 2
#define L2C_SCRUB_PEN_BIT 1 #define L2C_SCRUB_PEN_BIT 1
#define L2C_SCRUB_EN_BIT 0 #define L2C_SCRUB_EN_BIT 0
/* /*
* L2CACHE SCRUBDELAY register fields * L2CACHE SCRUBDELAY register fields
*/ */
#define L2C_SCRUB_DEL (0xffff << L2C_SCRUB_DEL_BIT) #define L2C_SCRUB_DEL (0xffff << L2C_SCRUB_DEL_BIT)
#define L2C_SCRUB_DEL_BIT 0 #define L2C_SCRUB_DEL_BIT 0
/* /*
* L2CACHE ERROR INJECT register fields * L2CACHE ERROR INJECT register fields
*/ */
#define L2C_ERRINJ_ADDR (0x3fffffff << L2C_ERRINJ_ADDR_BIT) #define L2C_ERRINJ_ADDR (0x3fffffff << L2C_ERRINJ_ADDR_BIT)
#define L2C_ERRINJ_EN (0x1 << L2C_ERRINJ_EN_BIT) #define L2C_ERRINJ_EN (0x1 << L2C_ERRINJ_EN_BIT)
@@ -258,7 +258,7 @@
#define L2C_ERRINJ_EN_BIT 0 #define L2C_ERRINJ_EN_BIT 0
/* /*
* L2CACHE ACCESS CONTROL register fields * L2CACHE ACCESS CONTROL register fields
*/ */
#define L2C_ACCCTRL_DSC (0x1 << L2C_ACCCTRL_DSC_BIT) #define L2C_ACCCTRL_DSC (0x1 << L2C_ACCCTRL_DSC_BIT)
#define L2C_ACCCTRL_SH (0x1 << L2C_ACCCTRL_SH_BIT) #define L2C_ACCCTRL_SH (0x1 << L2C_ACCCTRL_SH_BIT)
@@ -286,7 +286,7 @@
#ifdef TEST_L2CACHE #ifdef TEST_L2CACHE
/* /*
* L2CACHE TAG fields * L2CACHE TAG fields
*/ */
#define L2C_TAG_TAG (0xfffffc << L2C_TAG_TAG_BIT) #define L2C_TAG_TAG (0xfffffc << L2C_TAG_TAG_BIT)
#define L2C_TAG_VALID (0x3 << L2C_TAG_VALID_BIT) #define L2C_TAG_VALID (0x3 << L2C_TAG_VALID_BIT)
@@ -326,7 +326,7 @@ struct l2cache_priv {
}; };
/* /*
* L2CACHE internal prototypes * L2CACHE internal prototypes
*/ */
/* -Register access functions */ /* -Register access functions */
STATIC INLINE int l2cache_reg_ctrl_enable(void); STATIC INLINE int l2cache_reg_ctrl_enable(void);
@@ -338,7 +338,7 @@ STATIC INLINE int l2cache_reg_ctrl_iway(int way);
STATIC INLINE int l2cache_reg_ctrl_writep(int policy); STATIC INLINE int l2cache_reg_ctrl_writep(int policy);
STATIC INLINE unsigned int l2cache_reg_ctrl(void); STATIC INLINE unsigned int l2cache_reg_ctrl(void);
STATIC INLINE unsigned int l2cache_reg_status(void); STATIC INLINE unsigned int l2cache_reg_status(void);
STATIC INLINE int l2cache_reg_mtrr_set(int index, unsigned int addr, STATIC INLINE int l2cache_reg_mtrr_set(int index, unsigned int addr,
unsigned int mask, int options); unsigned int mask, int options);
UNUSED STATIC INLINE unsigned int l2cache_reg_mtrr_get(int index); UNUSED STATIC INLINE unsigned int l2cache_reg_mtrr_get(int index);
STATIC INLINE int l2cache_reg_flushmem(unsigned int addr, int options); STATIC INLINE int l2cache_reg_flushmem(unsigned int addr, int options);
@@ -378,7 +378,7 @@ int l2cache_init1(struct drvmgr_dev *dev);
void l2cache_isr(void *arg); void l2cache_isr(void *arg);
/* /*
* L2CACHE static members * L2CACHE static members
*/ */
static struct l2cache_priv *l2cachepriv = NULL; static struct l2cache_priv *l2cachepriv = NULL;
#ifdef DEBUG #ifdef DEBUG
@@ -387,14 +387,14 @@ static char * repl_names[4] = {"LRU","Random","Master-Idx-1","Master-IDx-2"};
/* L2CACHE DRIVER */ /* L2CACHE DRIVER */
struct drvmgr_drv_ops l2cache_ops = struct drvmgr_drv_ops l2cache_ops =
{ {
.init = {l2cache_init1, NULL, NULL, NULL}, .init = {l2cache_init1, NULL, NULL, NULL},
.remove = NULL, .remove = NULL,
.info = NULL .info = NULL
}; };
struct amba_dev_id l2cache_ids[] = struct amba_dev_id l2cache_ids[] =
{ {
{VENDOR_GAISLER, GAISLER_L2CACHE}, {VENDOR_GAISLER, GAISLER_L2CACHE},
{0, 0} /* Mark end of table */ {0, 0} /* Mark end of table */
@@ -442,7 +442,7 @@ STATIC int l2cache_init(struct l2cache_priv *priv)
/* Initialize L2CACHE status */ /* Initialize L2CACHE status */
unsigned int status = l2cache_reg_status(); unsigned int status = l2cache_reg_status();
priv->ways = (status & L2C_STAT_WAY) + 1; priv->ways = (status & L2C_STAT_WAY) + 1;
priv->waysize = priv->waysize =
((status & L2C_STAT_WAYSIZE) >> L2C_STAT_WAYSIZE_BIT) * 1024; ((status & L2C_STAT_WAYSIZE) >> L2C_STAT_WAYSIZE_BIT) * 1024;
priv->linesize = ((status & L2C_STAT_LS)? 64 : 32); priv->linesize = ((status & L2C_STAT_LS)? 64 : 32);
priv->index = ((priv->waysize)/(priv->linesize)); priv->index = ((priv->waysize)/(priv->linesize));
@@ -464,7 +464,7 @@ STATIC int l2cache_init(struct l2cache_priv *priv)
}else{ }else{
l2cache_reg_accctrl_split_disable(); l2cache_reg_accctrl_split_disable();
} }
priv->split_support = priv->split_support =
((split_new ^ split_old) >> L2C_ACCCTRL_SPLIT_BIT) & 1; ((split_new ^ split_old) >> L2C_ACCCTRL_SPLIT_BIT) & 1;
DBG("L2CACHE driver initialized\n"); DBG("L2CACHE driver initialized\n");
@@ -472,7 +472,7 @@ STATIC int l2cache_init(struct l2cache_priv *priv)
return 0; return 0;
} }
/* Called when a core is found with the AMBA device and vendor ID /* Called when a core is found with the AMBA device and vendor ID
* given in l2cache_ids[]. IRQ, Console does not work here * given in l2cache_ids[]. IRQ, Console does not work here
*/ */
int l2cache_init1(struct drvmgr_dev *dev) int l2cache_init1(struct drvmgr_dev *dev)
@@ -528,8 +528,8 @@ STATIC INLINE int l2cache_reg_ctrl_repl(int policy)
struct l2cache_priv *priv = l2cachepriv; struct l2cache_priv *priv = l2cachepriv;
unsigned int ctrl = REG_READ(&priv->regs->control); unsigned int ctrl = REG_READ(&priv->regs->control);
REG_WRITE(&priv->regs->control, REG_WRITE(&priv->regs->control,
((ctrl & ~(L2C_CTRL_REPL)) | ((ctrl & ~(L2C_CTRL_REPL)) |
((policy << L2C_CTRL_REPL_BIT) & L2C_CTRL_REPL)) ((policy << L2C_CTRL_REPL_BIT) & L2C_CTRL_REPL))
); );
return 0; return 0;
@@ -540,8 +540,8 @@ STATIC INLINE int l2cache_reg_ctrl_iway(int way)
struct l2cache_priv *priv = l2cachepriv; struct l2cache_priv *priv = l2cachepriv;
unsigned int ctrl = REG_READ(&priv->regs->control); unsigned int ctrl = REG_READ(&priv->regs->control);
REG_WRITE(&priv->regs->control, REG_WRITE(&priv->regs->control,
((ctrl & ~(L2C_CTRL_IWAY)) | ((ctrl & ~(L2C_CTRL_IWAY)) |
((way << L2C_CTRL_IWAY_BIT) & L2C_CTRL_IWAY)) ((way << L2C_CTRL_IWAY_BIT) & L2C_CTRL_IWAY))
); );
return 0; return 0;
@@ -552,7 +552,7 @@ STATIC INLINE int l2cache_reg_ctrl_writep(int policy)
struct l2cache_priv *priv = l2cachepriv; struct l2cache_priv *priv = l2cachepriv;
unsigned int ctrl = REG_READ(&priv->regs->control); unsigned int ctrl = REG_READ(&priv->regs->control);
REG_WRITE(&priv->regs->control, REG_WRITE(&priv->regs->control,
((ctrl & ~(L2C_CTRL_WP)) | ((policy << L2C_CTRL_WP_BIT) & L2C_CTRL_WP)) ((ctrl & ~(L2C_CTRL_WP)) | ((policy << L2C_CTRL_WP_BIT) & L2C_CTRL_WP))
); );
return 0; return 0;
@@ -564,8 +564,8 @@ STATIC INLINE int l2cache_reg_ctrl_locked_set(int locked)
unsigned int ctrl = REG_READ(&priv->regs->control); unsigned int ctrl = REG_READ(&priv->regs->control);
ctrl = (ctrl & ~(L2C_CTRL_LOCK)); ctrl = (ctrl & ~(L2C_CTRL_LOCK));
REG_WRITE(&priv->regs->control, REG_WRITE(&priv->regs->control,
ctrl | ctrl |
((locked << L2C_CTRL_LOCK_BIT) & L2C_CTRL_LOCK)); ((locked << L2C_CTRL_LOCK_BIT) & L2C_CTRL_LOCK));
return 0; return 0;
} }
@@ -575,8 +575,8 @@ STATIC INLINE int l2cache_reg_ctrl_edac_set(int edac)
struct l2cache_priv *priv = l2cachepriv; struct l2cache_priv *priv = l2cachepriv;
unsigned int ctrl = REG_READ(&priv->regs->control); unsigned int ctrl = REG_READ(&priv->regs->control);
REG_WRITE(&priv->regs->control, REG_WRITE(&priv->regs->control,
(ctrl & ~(L2C_CTRL_EDAC)) | (ctrl & ~(L2C_CTRL_EDAC)) |
(edac? L2C_CTRL_EDAC:0)); (edac? L2C_CTRL_EDAC:0));
return 0; return 0;
} }
@@ -595,14 +595,14 @@ STATIC INLINE unsigned int l2cache_reg_status(void)
return REG_READ(&priv->regs->status); return REG_READ(&priv->regs->status);
} }
STATIC INLINE int l2cache_reg_mtrr_set(int index, unsigned int addr, STATIC INLINE int l2cache_reg_mtrr_set(int index, unsigned int addr,
unsigned int mask, int options) unsigned int mask, int options)
{ {
struct l2cache_priv *priv = l2cachepriv; struct l2cache_priv *priv = l2cachepriv;
/* Set mtrr */ /* Set mtrr */
addr = addr & L2C_MTRR_ADDR; addr = addr & L2C_MTRR_ADDR;
mask = (mask >> 16) & L2C_MTRR_MASK; mask = (mask >> 16) & L2C_MTRR_MASK;
options = ((options & ~(L2C_MTRR_ADDR)) & ~(L2C_MTRR_MASK)); options = ((options & ~(L2C_MTRR_ADDR)) & ~(L2C_MTRR_MASK));
unsigned int mtrr = 0 | addr | mask | options; unsigned int mtrr = 0 | addr | mask | options;
REG_WRITE(&priv->regs->mtrr[index], mtrr); REG_WRITE(&priv->regs->mtrr[index], mtrr);
@@ -672,7 +672,7 @@ STATIC INLINE int l2cache_reg_error_irqmask(int mask)
struct l2cache_priv *priv = l2cachepriv; struct l2cache_priv *priv = l2cachepriv;
unsigned int ctrl = REG_READ(&priv->regs->error_status_control); unsigned int ctrl = REG_READ(&priv->regs->error_status_control);
REG_WRITE(&priv->regs->error_status_control, REG_WRITE(&priv->regs->error_status_control,
(ctrl & ~(L2C_ERROR_IRQM)) | (mask & L2C_ERROR_IRQM)); (ctrl & ~(L2C_ERROR_IRQM)) | (mask & L2C_ERROR_IRQM));
return 0; return 0;
} }
@@ -700,7 +700,7 @@ STATIC INLINE int l2cache_reg_scrub_enable(int delay)
accc | L2C_ACCCTRL_DSC | L2C_ACCCTRL_SH); accc | L2C_ACCCTRL_DSC | L2C_ACCCTRL_SH);
unsigned int ctrl = REG_READ(&priv->regs->scrub_control_status); unsigned int ctrl = REG_READ(&priv->regs->scrub_control_status);
REG_WRITE(&priv->regs->scrub_delay, REG_WRITE(&priv->regs->scrub_delay,
(delay << L2C_SCRUB_DEL_BIT) & L2C_SCRUB_DEL); (delay << L2C_SCRUB_DEL_BIT) & L2C_SCRUB_DEL);
REG_WRITE(&priv->regs->scrub_control_status, ctrl | L2C_SCRUB_EN); REG_WRITE(&priv->regs->scrub_control_status, ctrl | L2C_SCRUB_EN);
return 0; return 0;
@@ -719,7 +719,7 @@ STATIC INLINE int l2cache_reg_scrub_line(int way, int index)
{ {
struct l2cache_priv *priv = l2cachepriv; struct l2cache_priv *priv = l2cachepriv;
REG_WRITE(&priv->regs->scrub_control_status, REG_WRITE(&priv->regs->scrub_control_status,
((index << L2C_SCRUB_INDEX_BIT) & L2C_SCRUB_INDEX) | ((index << L2C_SCRUB_INDEX_BIT) & L2C_SCRUB_INDEX) |
((way << L2C_SCRUB_WAY_BIT) & L2C_SCRUB_WAY) | ((way << L2C_SCRUB_WAY_BIT) & L2C_SCRUB_WAY) |
L2C_SCRUB_PEN); L2C_SCRUB_PEN);
@@ -779,7 +779,7 @@ STATIC INLINE int l2cache_reg_error_dcb(unsigned int cb)
{ {
struct l2cache_priv *priv = l2cachepriv; struct l2cache_priv *priv = l2cachepriv;
REG_WRITE(&priv->regs->data_check_bit, (cb & L2C_DCB_CB)); REG_WRITE(&priv->regs->data_check_bit, (cb & L2C_DCB_CB));
return 0; return 0;
} }
@@ -787,8 +787,8 @@ STATIC INLINE int l2cache_reg_error_inject(unsigned int addr)
{ {
struct l2cache_priv *priv = l2cachepriv; struct l2cache_priv *priv = l2cachepriv;
REG_WRITE(&priv->regs->error_injection, REG_WRITE(&priv->regs->error_injection,
(addr & L2C_ERRINJ_ADDR) | L2C_ERRINJ_EN); (addr & L2C_ERRINJ_ADDR) | L2C_ERRINJ_EN);
return 0; return 0;
} }
@@ -862,7 +862,7 @@ int l2cache_lookup(uint32_t addr, int * way)
uint32_t exptag = l2cache_get_tag(addr); uint32_t exptag = l2cache_get_tag(addr);
int index = l2cache_get_index(addr); int index = l2cache_get_index(addr);
/* Check all tags in the set */ /* Check all tags in the set */
for(i=0; i< priv->ways; i++){ for(i=0; i< priv->ways; i++){
ret = l2cache_diag_tag(i, index, &gottag); ret = l2cache_diag_tag(i, index, &gottag);
if (ret != L2CACHE_ERR_OK){ if (ret != L2CACHE_ERR_OK){
@@ -878,13 +878,13 @@ int l2cache_lookup(uint32_t addr, int * way)
if (way){ if (way){
*way = i; *way = i;
} }
DBG("L2CACHE lookup: index=%d, tag=0x%08x HIT way=%d.\n", DBG("L2CACHE lookup: index=%d, tag=0x%08x HIT way=%d.\n",
index, (unsigned int) exptag, i); index, (unsigned int) exptag, i);
return L2CACHE_HIT; return L2CACHE_HIT;
} }
} }
} }
DBG("L2CACHE lookup: index=%d, tag=0x%08x MISS.\n", DBG("L2CACHE lookup: index=%d, tag=0x%08x MISS.\n",
index, (unsigned int) exptag); index, (unsigned int) exptag);
/* MISS! */ /* MISS! */
return L2CACHE_MISS; return L2CACHE_MISS;
@@ -990,7 +990,7 @@ int l2cache_error_inject_address( uint32_t addr, uint32_t mask)
/* Inject error */ /* Inject error */
l2cache_reg_error_inject(addr); l2cache_reg_error_inject(addr);
DBG("L2CACHE error injected in 0x%08x (0x%08x).\n", DBG("L2CACHE error injected in 0x%08x (0x%08x).\n",
(unsigned int) addr, (unsigned int) mask); (unsigned int) addr, (unsigned int) mask);
return L2CACHE_ERR_OK; return L2CACHE_ERR_OK;
@@ -1048,8 +1048,8 @@ int l2cache_disable(int flush)
return L2CACHE_ERR_NOINIT; return L2CACHE_ERR_NOINIT;
} }
if ((flush < 0) || if ((flush < 0) ||
(flush > (flush >
(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT)) (L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
){ ){
DBG("L2CACHE wrong flush option.\n"); DBG("L2CACHE wrong flush option.\n");
@@ -1137,8 +1137,8 @@ int l2cache_flush(int flush)
return L2CACHE_ERR_NOINIT; return L2CACHE_ERR_NOINIT;
} }
if ((flush < 0) || if ((flush < 0) ||
(flush > (flush >
(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT)) (L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
){ ){
DBG("L2CACHE wrong flush option.\n"); DBG("L2CACHE wrong flush option.\n");
@@ -1181,8 +1181,8 @@ int l2cache_flush_address(uint32_t addr, int size, int flush)
return L2CACHE_ERR_NOINIT; return L2CACHE_ERR_NOINIT;
} }
if ((flush < 0) || if ((flush < 0) ||
(flush > (flush >
(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT)) (L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
){ ){
DBG("L2CACHE wrong flush option.\n"); DBG("L2CACHE wrong flush option.\n");
@@ -1228,7 +1228,7 @@ int l2cache_flush_address(uint32_t addr, int size, int flush)
if (flush & L2CACHE_OPTIONS_FLUSH_WAIT){ if (flush & L2CACHE_OPTIONS_FLUSH_WAIT){
l2cache_flushwait(); l2cache_flushwait();
} }
DBG("L2CACHE address range flushed\n"); DBG("L2CACHE address range flushed\n");
return L2CACHE_ERR_OK; return L2CACHE_ERR_OK;
} }
@@ -1244,8 +1244,8 @@ int l2cache_flush_line(int way, int index, int flush)
return L2CACHE_ERR_NOINIT; return L2CACHE_ERR_NOINIT;
} }
if ((flush < 0) || if ((flush < 0) ||
(flush > (flush >
(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT)) (L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
){ ){
DBG("L2CACHE wrong flush option.\n"); DBG("L2CACHE wrong flush option.\n");
@@ -1266,7 +1266,7 @@ int l2cache_flush_line(int way, int index, int flush)
case L2CACHE_OPTIONS_FLUSH_NONE: case L2CACHE_OPTIONS_FLUSH_NONE:
break; break;
case L2CACHE_OPTIONS_FLUSH_INV_WBACK: case L2CACHE_OPTIONS_FLUSH_INV_WBACK:
l2cache_reg_flushline(way, index, l2cache_reg_flushline(way, index,
L2C_FLUSHSI_FMODE_SET_INV_WB_ONE); L2C_FLUSHSI_FMODE_SET_INV_WB_ONE);
break; break;
case L2CACHE_OPTIONS_FLUSH_WRITEBACK: case L2CACHE_OPTIONS_FLUSH_WRITEBACK:
@@ -1297,8 +1297,8 @@ int l2cache_flush_way(int way, int flush)
return L2CACHE_ERR_NOINIT; return L2CACHE_ERR_NOINIT;
} }
if ((flush < 0) || if ((flush < 0) ||
(flush > (flush >
(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT)) (L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
){ ){
DBG("L2CACHE wrong flush option.\n"); DBG("L2CACHE wrong flush option.\n");
@@ -1358,17 +1358,17 @@ int l2cache_fill_way(int way, uint32_t tag, int options, int flush)
/* Perform the Way-flush */ /* Perform the Way-flush */
flags = ((options & L2CACHE_OPTIONS_FETCH)? L2C_FLUSHSI_FL:0) | flags = ((options & L2CACHE_OPTIONS_FETCH)? L2C_FLUSHSI_FL:0) |
((options & L2CACHE_OPTIONS_VALID)? L2C_FLUSHSI_VB:0) | ((options & L2CACHE_OPTIONS_VALID)? L2C_FLUSHSI_VB:0) |
((options & L2CACHE_OPTIONS_DIRTY)? L2C_FLUSHSI_DB:0); ((options & L2CACHE_OPTIONS_DIRTY)? L2C_FLUSHSI_DB:0);
/*DBG("L2CACHE lock way: Locked=%d, way=%d, option=0x%04x\n", /*DBG("L2CACHE lock way: Locked=%d, way=%d, option=0x%04x\n",
* locked, way, flags);*/ * locked, way, flags);*/
switch(flush & 0x3){ switch(flush & 0x3){
case L2CACHE_OPTIONS_FLUSH_NONE: case L2CACHE_OPTIONS_FLUSH_NONE:
break; break;
case L2CACHE_OPTIONS_FLUSH_INVALIDATE: case L2CACHE_OPTIONS_FLUSH_INVALIDATE:
l2cache_reg_flushway(tag, way, l2cache_reg_flushway(tag, way,
flags | L2C_FLUSHSI_FMODE_WAY_UPDATE); flags | L2C_FLUSHSI_FMODE_WAY_UPDATE);
break; break;
case L2CACHE_OPTIONS_FLUSH_WRITEBACK: case L2CACHE_OPTIONS_FLUSH_WRITEBACK:
@@ -1376,7 +1376,7 @@ int l2cache_fill_way(int way, uint32_t tag, int options, int flush)
break; break;
case L2CACHE_OPTIONS_FLUSH_INV_WBACK: case L2CACHE_OPTIONS_FLUSH_INV_WBACK:
default: default:
l2cache_reg_flushway(tag, way, l2cache_reg_flushway(tag, way,
flags | L2C_FLUSHSI_FMODE_WAY_UPDATE_WB_ALL); flags | L2C_FLUSHSI_FMODE_WAY_UPDATE_WB_ALL);
break; break;
} }
@@ -1420,7 +1420,7 @@ int l2cache_lock_way(uint32_t tag, int options, int flush, int enable)
/* Check L2C status */ /* Check L2C status */
enabled = l2cache_ctrl_status(); enabled = l2cache_ctrl_status();
/* Disable L2C */ /* Disable L2C */
ret = l2cache_disable(flush); ret = l2cache_disable(flush);
if (ret < 0){ if (ret < 0){
@@ -1434,7 +1434,7 @@ int l2cache_lock_way(uint32_t tag, int options, int flush, int enable)
/* Perform the Way-flush */ /* Perform the Way-flush */
flags = ((options & L2CACHE_OPTIONS_FETCH)? L2C_FLUSHSI_FL:0) | flags = ((options & L2CACHE_OPTIONS_FETCH)? L2C_FLUSHSI_FL:0) |
((options & L2CACHE_OPTIONS_VALID)? L2C_FLUSHSI_VB:0) | ((options & L2CACHE_OPTIONS_VALID)? L2C_FLUSHSI_VB:0) |
((options & L2CACHE_OPTIONS_DIRTY)? L2C_FLUSHSI_DB:0); ((options & L2CACHE_OPTIONS_DIRTY)? L2C_FLUSHSI_DB:0);
/*DBG("L2CACHE lock way: Locked=%d, way=%d, option=0x%04x\n", /*DBG("L2CACHE lock way: Locked=%d, way=%d, option=0x%04x\n",
@@ -1444,7 +1444,7 @@ int l2cache_lock_way(uint32_t tag, int options, int flush, int enable)
case L2CACHE_OPTIONS_FLUSH_NONE: case L2CACHE_OPTIONS_FLUSH_NONE:
break; break;
case L2CACHE_OPTIONS_FLUSH_INVALIDATE: case L2CACHE_OPTIONS_FLUSH_INVALIDATE:
l2cache_reg_flushway(tag, way, l2cache_reg_flushway(tag, way,
flags | L2C_FLUSHSI_FMODE_WAY_UPDATE); flags | L2C_FLUSHSI_FMODE_WAY_UPDATE);
break; break;
case L2CACHE_OPTIONS_FLUSH_WRITEBACK: case L2CACHE_OPTIONS_FLUSH_WRITEBACK:
@@ -1452,7 +1452,7 @@ int l2cache_lock_way(uint32_t tag, int options, int flush, int enable)
break; break;
case L2CACHE_OPTIONS_FLUSH_INV_WBACK: case L2CACHE_OPTIONS_FLUSH_INV_WBACK:
default: default:
l2cache_reg_flushway(tag, way, l2cache_reg_flushway(tag, way,
flags | L2C_FLUSHSI_FMODE_WAY_UPDATE_WB_ALL); flags | L2C_FLUSHSI_FMODE_WAY_UPDATE_WB_ALL);
break; break;
} }
@@ -1502,9 +1502,9 @@ int l2cache_unlock()
/* Setup L2CACHE: /* Setup L2CACHE:
* Parameters: * Parameters:
* -options: Can be: * -options: Can be:
*/ */
int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options, int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options,
int flush) int flush)
{ {
struct l2cache_priv * priv = l2cachepriv; struct l2cache_priv * priv = l2cachepriv;
@@ -1544,16 +1544,16 @@ int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options,
/* Decode options */ /* Decode options */
flags = 0 | flags = 0 |
(options & L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH? (options & L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH?
L2C_MTRR_WRITETHROUGH : L2C_MTRR_WRITETHROUGH :
L2C_MTRR_UNCACHED) | L2C_MTRR_UNCACHED) |
(options & L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE? (options & L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE?
L2C_MTRR_WRITEPROT_ENABLE : L2C_MTRR_WRITEPROT_ENABLE :
L2C_MTRR_WRITEPROT_DISABLE) | L2C_MTRR_WRITEPROT_DISABLE) |
L2C_MTRR_ACCESSCONTROL_ENABLE; L2C_MTRR_ACCESSCONTROL_ENABLE;
/* Configure mtrr */ /* Configure mtrr */
l2cache_reg_mtrr_set(index, addr, mask, flags); l2cache_reg_mtrr_set(index, addr, mask, flags);
/* Enable cache again (if needed) */ /* Enable cache again (if needed) */
if (enabled){ if (enabled){
@@ -1561,9 +1561,9 @@ int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options,
} }
DBG("MTRR[%d] succesfully configured for 0x%08x (mask 0x%08x), " DBG("MTRR[%d] succesfully configured for 0x%08x (mask 0x%08x), "
"access=%s, wprot=%s\n", "access=%s, wprot=%s\n",
index, (unsigned int) addr, (unsigned int) mask, index, (unsigned int) addr, (unsigned int) mask,
(options & L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH? (options & L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH?
"WRITETHROUGH":"UNCACHED"), "WRITETHROUGH":"UNCACHED"),
(options & L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE? "ENABLE":"DISABLE") (options & L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE? "ENABLE":"DISABLE")
); );
@@ -1573,7 +1573,7 @@ int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options,
/* Setup L2CACHE: /* Setup L2CACHE:
* Parameters: * Parameters:
* -options: Can be: * -options: Can be:
*/ */
int l2cache_mtrr_disable(int index) int l2cache_mtrr_disable(int index)
{ {
@@ -1595,7 +1595,7 @@ int l2cache_mtrr_disable(int index)
} }
/* Configure mtrr */ /* Configure mtrr */
l2cache_reg_mtrr_set(index, 0, 0, L2C_MTRR_ACCESSCONTROL_DISABLE); l2cache_reg_mtrr_set(index, 0, 0, L2C_MTRR_ACCESSCONTROL_DISABLE);
DBG("MTRR[%d] disabled\n", index); DBG("MTRR[%d] disabled\n", index);
@@ -1623,14 +1623,14 @@ int l2cache_print(void)
" MTRR:%d, FT:%s, Locked:%d, Split:%s\n" " MTRR:%d, FT:%s, Locked:%d, Split:%s\n"
" REPL:%s, WP:%s, EDAC:%s, Enabled:%s\n" " REPL:%s, WP:%s, EDAC:%s, Enabled:%s\n"
" Scrub:%s, S-Delay:%d\n", " Scrub:%s, S-Delay:%d\n",
priv->ways, priv->ways,
priv->waysize, priv->waysize,
priv->linesize, priv->linesize,
(priv->index * priv->ways), (priv->index * priv->ways),
priv->mtrr, priv->mtrr,
(priv->ft_support? "Available":"N/A"), (priv->ft_support? "Available":"N/A"),
L2CACHE_LOCKED_WAYS(status), L2CACHE_LOCKED_WAYS(status),
(priv->split_support? (L2CACHE_SPLIT_ENABLED(status)? (priv->split_support? (L2CACHE_SPLIT_ENABLED(status)?
"Enabled":"Disabled"):"N/A"), "Enabled":"Disabled"):"N/A"),
repl_names[L2CACHE_REPL(status)], repl_names[L2CACHE_REPL(status)],
(L2CACHE_WRITETHROUGH(status)? "Write-through":"Write-back"), (L2CACHE_WRITETHROUGH(status)? "Write-through":"Write-back"),
@@ -1990,7 +1990,7 @@ int l2cache_isr_register(l2cache_isr_t isr, void * arg, int options)
/* First time registering an ISR */ /* First time registering an ISR */
if (priv->isr == NULL){ if (priv->isr == NULL){
/* Install and Enable L2CACHE interrupt handler */ /* Install and Enable L2CACHE interrupt handler */
drvmgr_interrupt_register(priv->dev, 0, priv->devname, l2cache_isr, drvmgr_interrupt_register(priv->dev, 0, priv->devname, l2cache_isr,
priv); priv);
} }