forked from Imagelibrary/rtems
grlib/l2c: Fix whitespace
No functional change
This commit is contained in:
Martin Åberg
committed by
Kinsey Moore
Kinsey Moore
parent
e5854b2a69
commit
ed55634d51
@@ -52,11 +52,11 @@
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#ifdef DEBUG
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#define DBG(x...) printf(x)
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#else
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#define DBG(x...)
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#define DBG(x...)
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#endif
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/*
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* L2CACHE CTRL register fields
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* L2CACHE CTRL register fields
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*/
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#define L2C_CTRL_EN (0x1 << L2C_CTRL_EN_BIT)
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#define L2C_CTRL_EDAC (0x1 << L2C_CTRL_EDAC_BIT)
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@@ -83,7 +83,7 @@
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#define L2C_CTRL_HP_BIT 0
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/*
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* L2CACHE STATUS register fields
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* L2CACHE STATUS register fields
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*/
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#define L2C_STAT_LS (0x1 << L2C_STAT_LS_BIT)
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#define L2C_STAT_AT (0x1 << L2C_STAT_AT_BIT)
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@@ -102,7 +102,7 @@
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#define L2C_STAT_WAY_BIT 0
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/*
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* L2CACHE MTRR register fields
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* L2CACHE MTRR register fields
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*/
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#define L2C_MTRR_ADDR (0x3fff << L2C_MTRR_ADDR_BIT)
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#define L2C_MTRR_ACC (0x3 << L2C_MTRR_ACC_BIT)
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@@ -127,7 +127,7 @@
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#define REG_READ(addr) (*(volatile unsigned int *)(addr))
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/*
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* L2CACHE FLUSHMEM register fields
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* L2CACHE FLUSHMEM register fields
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*/
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#define L2C_FLUSH_ADDR (0x7ffffff << L2C_FLUSH_ADDR_BIT)
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#define L2C_FLUSH_DI (0x1 << L2C_FLUSH_DI_BIT)
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@@ -145,7 +145,7 @@
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#define L2C_FLUSH_FMODE_INV_WB_ALL (0x7 << L2C_FLUSH_FMODE_BIT)
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/*
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* L2CACHE FLUSSETINDEX register fields
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* L2CACHE FLUSSETINDEX register fields
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*/
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#define L2C_FLUSHSI_INDEX (0xffff << L2C_FLUSHSI_INDEX_BIT)
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#define L2C_FLUSHSI_TAG (0x3fffff << L2C_FLUSHSI_TAG_BIT)
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@@ -175,7 +175,7 @@
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#define L2C_FLUSHSI_FMODE_WAY_UPDATE_WB_ALL (0x3 << L2C_FLUSHSI_FMODE_BIT)
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/*
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* L2CACHE ERROR register fields
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* L2CACHE ERROR register fields
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*/
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#define L2C_ERROR_AHBM (0xf << L2C_ERROR_AHBM_BIT)
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#define L2C_ERROR_SCRUB (0x1 << L2C_ERROR_SCRUB_BIT)
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@@ -222,34 +222,34 @@
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#define L2C_ERROR_RST_BIT 0
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/*
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* L2CACHE DATA CHECK BITS register fields
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* L2CACHE DATA CHECK BITS register fields
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*/
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#define L2C_DCB_CB (0xfffffff << L2C_DCB_CB_BIT)
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#define L2C_DCB_CB_BIT 0
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#define L2C_DCB_CB_BIT 0
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/*
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* L2CACHE SCRUB register fields
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* L2CACHE SCRUB register fields
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*/
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#define L2C_SCRUB_INDEX (0xffff << L2C_SCRUB_INDEX_BIT)
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#define L2C_SCRUB_WAY (0x3 << L2C_SCRUB_WAY_BIT)
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#define L2C_SCRUB_PEN (0x1 << L2C_SCRUB_PEN_BIT)
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#define L2C_SCRUB_EN (0x1 << L2C_SCRUB_EN_BIT)
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#define L2C_SCRUB_INDEX_BIT 16
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#define L2C_SCRUB_INDEX_BIT 16
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#define L2C_SCRUB_WAY_BIT 2
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#define L2C_SCRUB_PEN_BIT 1
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#define L2C_SCRUB_EN_BIT 0
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/*
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* L2CACHE SCRUBDELAY register fields
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* L2CACHE SCRUBDELAY register fields
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*/
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#define L2C_SCRUB_DEL (0xffff << L2C_SCRUB_DEL_BIT)
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#define L2C_SCRUB_DEL_BIT 0
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#define L2C_SCRUB_DEL_BIT 0
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/*
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* L2CACHE ERROR INJECT register fields
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* L2CACHE ERROR INJECT register fields
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*/
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#define L2C_ERRINJ_ADDR (0x3fffffff << L2C_ERRINJ_ADDR_BIT)
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#define L2C_ERRINJ_EN (0x1 << L2C_ERRINJ_EN_BIT)
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@@ -258,7 +258,7 @@
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#define L2C_ERRINJ_EN_BIT 0
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/*
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* L2CACHE ACCESS CONTROL register fields
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* L2CACHE ACCESS CONTROL register fields
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*/
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#define L2C_ACCCTRL_DSC (0x1 << L2C_ACCCTRL_DSC_BIT)
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#define L2C_ACCCTRL_SH (0x1 << L2C_ACCCTRL_SH_BIT)
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@@ -286,7 +286,7 @@
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#ifdef TEST_L2CACHE
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/*
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* L2CACHE TAG fields
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* L2CACHE TAG fields
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*/
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#define L2C_TAG_TAG (0xfffffc << L2C_TAG_TAG_BIT)
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#define L2C_TAG_VALID (0x3 << L2C_TAG_VALID_BIT)
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@@ -326,7 +326,7 @@ struct l2cache_priv {
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};
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/*
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* L2CACHE internal prototypes
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* L2CACHE internal prototypes
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*/
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/* -Register access functions */
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STATIC INLINE int l2cache_reg_ctrl_enable(void);
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@@ -338,7 +338,7 @@ STATIC INLINE int l2cache_reg_ctrl_iway(int way);
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STATIC INLINE int l2cache_reg_ctrl_writep(int policy);
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STATIC INLINE unsigned int l2cache_reg_ctrl(void);
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STATIC INLINE unsigned int l2cache_reg_status(void);
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STATIC INLINE int l2cache_reg_mtrr_set(int index, unsigned int addr,
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STATIC INLINE int l2cache_reg_mtrr_set(int index, unsigned int addr,
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unsigned int mask, int options);
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UNUSED STATIC INLINE unsigned int l2cache_reg_mtrr_get(int index);
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STATIC INLINE int l2cache_reg_flushmem(unsigned int addr, int options);
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@@ -378,7 +378,7 @@ int l2cache_init1(struct drvmgr_dev *dev);
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void l2cache_isr(void *arg);
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/*
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* L2CACHE static members
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* L2CACHE static members
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*/
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static struct l2cache_priv *l2cachepriv = NULL;
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#ifdef DEBUG
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@@ -387,14 +387,14 @@ static char * repl_names[4] = {"LRU","Random","Master-Idx-1","Master-IDx-2"};
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/* L2CACHE DRIVER */
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struct drvmgr_drv_ops l2cache_ops =
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struct drvmgr_drv_ops l2cache_ops =
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{
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.init = {l2cache_init1, NULL, NULL, NULL},
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.remove = NULL,
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.info = NULL
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};
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struct amba_dev_id l2cache_ids[] =
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struct amba_dev_id l2cache_ids[] =
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{
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{VENDOR_GAISLER, GAISLER_L2CACHE},
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{0, 0} /* Mark end of table */
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@@ -442,7 +442,7 @@ STATIC int l2cache_init(struct l2cache_priv *priv)
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/* Initialize L2CACHE status */
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unsigned int status = l2cache_reg_status();
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priv->ways = (status & L2C_STAT_WAY) + 1;
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priv->waysize =
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priv->waysize =
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((status & L2C_STAT_WAYSIZE) >> L2C_STAT_WAYSIZE_BIT) * 1024;
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priv->linesize = ((status & L2C_STAT_LS)? 64 : 32);
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priv->index = ((priv->waysize)/(priv->linesize));
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@@ -464,7 +464,7 @@ STATIC int l2cache_init(struct l2cache_priv *priv)
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}else{
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l2cache_reg_accctrl_split_disable();
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}
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priv->split_support =
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priv->split_support =
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((split_new ^ split_old) >> L2C_ACCCTRL_SPLIT_BIT) & 1;
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DBG("L2CACHE driver initialized\n");
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@@ -472,7 +472,7 @@ STATIC int l2cache_init(struct l2cache_priv *priv)
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return 0;
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}
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/* Called when a core is found with the AMBA device and vendor ID
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/* Called when a core is found with the AMBA device and vendor ID
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* given in l2cache_ids[]. IRQ, Console does not work here
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*/
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int l2cache_init1(struct drvmgr_dev *dev)
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@@ -528,8 +528,8 @@ STATIC INLINE int l2cache_reg_ctrl_repl(int policy)
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struct l2cache_priv *priv = l2cachepriv;
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unsigned int ctrl = REG_READ(&priv->regs->control);
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REG_WRITE(&priv->regs->control,
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((ctrl & ~(L2C_CTRL_REPL)) |
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REG_WRITE(&priv->regs->control,
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((ctrl & ~(L2C_CTRL_REPL)) |
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((policy << L2C_CTRL_REPL_BIT) & L2C_CTRL_REPL))
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);
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return 0;
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@@ -540,8 +540,8 @@ STATIC INLINE int l2cache_reg_ctrl_iway(int way)
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struct l2cache_priv *priv = l2cachepriv;
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unsigned int ctrl = REG_READ(&priv->regs->control);
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REG_WRITE(&priv->regs->control,
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((ctrl & ~(L2C_CTRL_IWAY)) |
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REG_WRITE(&priv->regs->control,
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((ctrl & ~(L2C_CTRL_IWAY)) |
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((way << L2C_CTRL_IWAY_BIT) & L2C_CTRL_IWAY))
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);
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return 0;
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@@ -552,7 +552,7 @@ STATIC INLINE int l2cache_reg_ctrl_writep(int policy)
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struct l2cache_priv *priv = l2cachepriv;
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unsigned int ctrl = REG_READ(&priv->regs->control);
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REG_WRITE(&priv->regs->control,
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REG_WRITE(&priv->regs->control,
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((ctrl & ~(L2C_CTRL_WP)) | ((policy << L2C_CTRL_WP_BIT) & L2C_CTRL_WP))
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);
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return 0;
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@@ -564,8 +564,8 @@ STATIC INLINE int l2cache_reg_ctrl_locked_set(int locked)
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unsigned int ctrl = REG_READ(&priv->regs->control);
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ctrl = (ctrl & ~(L2C_CTRL_LOCK));
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REG_WRITE(&priv->regs->control,
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ctrl |
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REG_WRITE(&priv->regs->control,
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ctrl |
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((locked << L2C_CTRL_LOCK_BIT) & L2C_CTRL_LOCK));
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return 0;
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}
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@@ -575,8 +575,8 @@ STATIC INLINE int l2cache_reg_ctrl_edac_set(int edac)
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struct l2cache_priv *priv = l2cachepriv;
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unsigned int ctrl = REG_READ(&priv->regs->control);
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REG_WRITE(&priv->regs->control,
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(ctrl & ~(L2C_CTRL_EDAC)) |
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REG_WRITE(&priv->regs->control,
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(ctrl & ~(L2C_CTRL_EDAC)) |
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(edac? L2C_CTRL_EDAC:0));
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return 0;
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}
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@@ -595,14 +595,14 @@ STATIC INLINE unsigned int l2cache_reg_status(void)
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return REG_READ(&priv->regs->status);
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}
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STATIC INLINE int l2cache_reg_mtrr_set(int index, unsigned int addr,
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STATIC INLINE int l2cache_reg_mtrr_set(int index, unsigned int addr,
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unsigned int mask, int options)
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{
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struct l2cache_priv *priv = l2cachepriv;
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/* Set mtrr */
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addr = addr & L2C_MTRR_ADDR;
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mask = (mask >> 16) & L2C_MTRR_MASK;
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mask = (mask >> 16) & L2C_MTRR_MASK;
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options = ((options & ~(L2C_MTRR_ADDR)) & ~(L2C_MTRR_MASK));
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unsigned int mtrr = 0 | addr | mask | options;
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REG_WRITE(&priv->regs->mtrr[index], mtrr);
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@@ -672,7 +672,7 @@ STATIC INLINE int l2cache_reg_error_irqmask(int mask)
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struct l2cache_priv *priv = l2cachepriv;
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unsigned int ctrl = REG_READ(&priv->regs->error_status_control);
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REG_WRITE(&priv->regs->error_status_control,
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REG_WRITE(&priv->regs->error_status_control,
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(ctrl & ~(L2C_ERROR_IRQM)) | (mask & L2C_ERROR_IRQM));
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return 0;
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}
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@@ -700,7 +700,7 @@ STATIC INLINE int l2cache_reg_scrub_enable(int delay)
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accc | L2C_ACCCTRL_DSC | L2C_ACCCTRL_SH);
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unsigned int ctrl = REG_READ(&priv->regs->scrub_control_status);
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REG_WRITE(&priv->regs->scrub_delay,
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REG_WRITE(&priv->regs->scrub_delay,
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(delay << L2C_SCRUB_DEL_BIT) & L2C_SCRUB_DEL);
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REG_WRITE(&priv->regs->scrub_control_status, ctrl | L2C_SCRUB_EN);
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return 0;
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@@ -719,7 +719,7 @@ STATIC INLINE int l2cache_reg_scrub_line(int way, int index)
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{
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struct l2cache_priv *priv = l2cachepriv;
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REG_WRITE(&priv->regs->scrub_control_status,
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REG_WRITE(&priv->regs->scrub_control_status,
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((index << L2C_SCRUB_INDEX_BIT) & L2C_SCRUB_INDEX) |
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((way << L2C_SCRUB_WAY_BIT) & L2C_SCRUB_WAY) |
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L2C_SCRUB_PEN);
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@@ -779,7 +779,7 @@ STATIC INLINE int l2cache_reg_error_dcb(unsigned int cb)
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{
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struct l2cache_priv *priv = l2cachepriv;
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REG_WRITE(&priv->regs->data_check_bit, (cb & L2C_DCB_CB));
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REG_WRITE(&priv->regs->data_check_bit, (cb & L2C_DCB_CB));
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return 0;
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}
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@@ -787,8 +787,8 @@ STATIC INLINE int l2cache_reg_error_inject(unsigned int addr)
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{
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struct l2cache_priv *priv = l2cachepriv;
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REG_WRITE(&priv->regs->error_injection,
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(addr & L2C_ERRINJ_ADDR) | L2C_ERRINJ_EN);
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REG_WRITE(&priv->regs->error_injection,
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(addr & L2C_ERRINJ_ADDR) | L2C_ERRINJ_EN);
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return 0;
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}
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@@ -862,7 +862,7 @@ int l2cache_lookup(uint32_t addr, int * way)
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uint32_t exptag = l2cache_get_tag(addr);
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int index = l2cache_get_index(addr);
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/* Check all tags in the set */
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/* Check all tags in the set */
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for(i=0; i< priv->ways; i++){
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ret = l2cache_diag_tag(i, index, &gottag);
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if (ret != L2CACHE_ERR_OK){
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@@ -878,13 +878,13 @@ int l2cache_lookup(uint32_t addr, int * way)
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if (way){
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*way = i;
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}
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DBG("L2CACHE lookup: index=%d, tag=0x%08x HIT way=%d.\n",
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DBG("L2CACHE lookup: index=%d, tag=0x%08x HIT way=%d.\n",
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index, (unsigned int) exptag, i);
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return L2CACHE_HIT;
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}
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}
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}
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DBG("L2CACHE lookup: index=%d, tag=0x%08x MISS.\n",
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DBG("L2CACHE lookup: index=%d, tag=0x%08x MISS.\n",
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index, (unsigned int) exptag);
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/* MISS! */
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return L2CACHE_MISS;
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@@ -990,7 +990,7 @@ int l2cache_error_inject_address( uint32_t addr, uint32_t mask)
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/* Inject error */
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l2cache_reg_error_inject(addr);
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DBG("L2CACHE error injected in 0x%08x (0x%08x).\n",
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DBG("L2CACHE error injected in 0x%08x (0x%08x).\n",
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(unsigned int) addr, (unsigned int) mask);
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return L2CACHE_ERR_OK;
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@@ -1048,8 +1048,8 @@ int l2cache_disable(int flush)
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return L2CACHE_ERR_NOINIT;
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}
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if ((flush < 0) ||
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(flush >
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if ((flush < 0) ||
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(flush >
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(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
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){
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DBG("L2CACHE wrong flush option.\n");
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@@ -1137,8 +1137,8 @@ int l2cache_flush(int flush)
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return L2CACHE_ERR_NOINIT;
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}
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if ((flush < 0) ||
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(flush >
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if ((flush < 0) ||
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(flush >
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(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
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){
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DBG("L2CACHE wrong flush option.\n");
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@@ -1181,8 +1181,8 @@ int l2cache_flush_address(uint32_t addr, int size, int flush)
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return L2CACHE_ERR_NOINIT;
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}
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if ((flush < 0) ||
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(flush >
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if ((flush < 0) ||
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(flush >
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(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
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){
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DBG("L2CACHE wrong flush option.\n");
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@@ -1228,7 +1228,7 @@ int l2cache_flush_address(uint32_t addr, int size, int flush)
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if (flush & L2CACHE_OPTIONS_FLUSH_WAIT){
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l2cache_flushwait();
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}
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DBG("L2CACHE address range flushed\n");
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return L2CACHE_ERR_OK;
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}
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@@ -1244,8 +1244,8 @@ int l2cache_flush_line(int way, int index, int flush)
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return L2CACHE_ERR_NOINIT;
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}
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if ((flush < 0) ||
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(flush >
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if ((flush < 0) ||
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(flush >
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(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
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){
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DBG("L2CACHE wrong flush option.\n");
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@@ -1266,7 +1266,7 @@ int l2cache_flush_line(int way, int index, int flush)
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case L2CACHE_OPTIONS_FLUSH_NONE:
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break;
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case L2CACHE_OPTIONS_FLUSH_INV_WBACK:
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l2cache_reg_flushline(way, index,
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l2cache_reg_flushline(way, index,
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L2C_FLUSHSI_FMODE_SET_INV_WB_ONE);
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break;
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case L2CACHE_OPTIONS_FLUSH_WRITEBACK:
|
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@@ -1297,8 +1297,8 @@ int l2cache_flush_way(int way, int flush)
|
||||
return L2CACHE_ERR_NOINIT;
|
||||
}
|
||||
|
||||
if ((flush < 0) ||
|
||||
(flush >
|
||||
if ((flush < 0) ||
|
||||
(flush >
|
||||
(L2CACHE_OPTIONS_FLUSH_INVALIDATE | L2CACHE_OPTIONS_FLUSH_WAIT))
|
||||
){
|
||||
DBG("L2CACHE wrong flush option.\n");
|
||||
@@ -1358,17 +1358,17 @@ int l2cache_fill_way(int way, uint32_t tag, int options, int flush)
|
||||
|
||||
/* Perform the Way-flush */
|
||||
flags = ((options & L2CACHE_OPTIONS_FETCH)? L2C_FLUSHSI_FL:0) |
|
||||
((options & L2CACHE_OPTIONS_VALID)? L2C_FLUSHSI_VB:0) |
|
||||
((options & L2CACHE_OPTIONS_VALID)? L2C_FLUSHSI_VB:0) |
|
||||
((options & L2CACHE_OPTIONS_DIRTY)? L2C_FLUSHSI_DB:0);
|
||||
|
||||
/*DBG("L2CACHE lock way: Locked=%d, way=%d, option=0x%04x\n",
|
||||
/*DBG("L2CACHE lock way: Locked=%d, way=%d, option=0x%04x\n",
|
||||
* locked, way, flags);*/
|
||||
|
||||
switch(flush & 0x3){
|
||||
case L2CACHE_OPTIONS_FLUSH_NONE:
|
||||
break;
|
||||
case L2CACHE_OPTIONS_FLUSH_INVALIDATE:
|
||||
l2cache_reg_flushway(tag, way,
|
||||
l2cache_reg_flushway(tag, way,
|
||||
flags | L2C_FLUSHSI_FMODE_WAY_UPDATE);
|
||||
break;
|
||||
case L2CACHE_OPTIONS_FLUSH_WRITEBACK:
|
||||
@@ -1376,7 +1376,7 @@ int l2cache_fill_way(int way, uint32_t tag, int options, int flush)
|
||||
break;
|
||||
case L2CACHE_OPTIONS_FLUSH_INV_WBACK:
|
||||
default:
|
||||
l2cache_reg_flushway(tag, way,
|
||||
l2cache_reg_flushway(tag, way,
|
||||
flags | L2C_FLUSHSI_FMODE_WAY_UPDATE_WB_ALL);
|
||||
break;
|
||||
}
|
||||
@@ -1420,7 +1420,7 @@ int l2cache_lock_way(uint32_t tag, int options, int flush, int enable)
|
||||
|
||||
/* Check L2C status */
|
||||
enabled = l2cache_ctrl_status();
|
||||
|
||||
|
||||
/* Disable L2C */
|
||||
ret = l2cache_disable(flush);
|
||||
if (ret < 0){
|
||||
@@ -1434,7 +1434,7 @@ int l2cache_lock_way(uint32_t tag, int options, int flush, int enable)
|
||||
|
||||
/* Perform the Way-flush */
|
||||
flags = ((options & L2CACHE_OPTIONS_FETCH)? L2C_FLUSHSI_FL:0) |
|
||||
((options & L2CACHE_OPTIONS_VALID)? L2C_FLUSHSI_VB:0) |
|
||||
((options & L2CACHE_OPTIONS_VALID)? L2C_FLUSHSI_VB:0) |
|
||||
((options & L2CACHE_OPTIONS_DIRTY)? L2C_FLUSHSI_DB:0);
|
||||
|
||||
/*DBG("L2CACHE lock way: Locked=%d, way=%d, option=0x%04x\n",
|
||||
@@ -1444,7 +1444,7 @@ int l2cache_lock_way(uint32_t tag, int options, int flush, int enable)
|
||||
case L2CACHE_OPTIONS_FLUSH_NONE:
|
||||
break;
|
||||
case L2CACHE_OPTIONS_FLUSH_INVALIDATE:
|
||||
l2cache_reg_flushway(tag, way,
|
||||
l2cache_reg_flushway(tag, way,
|
||||
flags | L2C_FLUSHSI_FMODE_WAY_UPDATE);
|
||||
break;
|
||||
case L2CACHE_OPTIONS_FLUSH_WRITEBACK:
|
||||
@@ -1452,7 +1452,7 @@ int l2cache_lock_way(uint32_t tag, int options, int flush, int enable)
|
||||
break;
|
||||
case L2CACHE_OPTIONS_FLUSH_INV_WBACK:
|
||||
default:
|
||||
l2cache_reg_flushway(tag, way,
|
||||
l2cache_reg_flushway(tag, way,
|
||||
flags | L2C_FLUSHSI_FMODE_WAY_UPDATE_WB_ALL);
|
||||
break;
|
||||
}
|
||||
@@ -1502,9 +1502,9 @@ int l2cache_unlock()
|
||||
|
||||
/* Setup L2CACHE:
|
||||
* Parameters:
|
||||
* -options: Can be:
|
||||
* -options: Can be:
|
||||
*/
|
||||
int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options,
|
||||
int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options,
|
||||
int flush)
|
||||
{
|
||||
struct l2cache_priv * priv = l2cachepriv;
|
||||
@@ -1544,16 +1544,16 @@ int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options,
|
||||
|
||||
/* Decode options */
|
||||
flags = 0 |
|
||||
(options & L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH?
|
||||
L2C_MTRR_WRITETHROUGH :
|
||||
(options & L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH?
|
||||
L2C_MTRR_WRITETHROUGH :
|
||||
L2C_MTRR_UNCACHED) |
|
||||
(options & L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE?
|
||||
L2C_MTRR_WRITEPROT_ENABLE :
|
||||
(options & L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE?
|
||||
L2C_MTRR_WRITEPROT_ENABLE :
|
||||
L2C_MTRR_WRITEPROT_DISABLE) |
|
||||
L2C_MTRR_ACCESSCONTROL_ENABLE;
|
||||
|
||||
/* Configure mtrr */
|
||||
l2cache_reg_mtrr_set(index, addr, mask, flags);
|
||||
l2cache_reg_mtrr_set(index, addr, mask, flags);
|
||||
|
||||
/* Enable cache again (if needed) */
|
||||
if (enabled){
|
||||
@@ -1561,9 +1561,9 @@ int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options,
|
||||
}
|
||||
|
||||
DBG("MTRR[%d] succesfully configured for 0x%08x (mask 0x%08x), "
|
||||
"access=%s, wprot=%s\n",
|
||||
index, (unsigned int) addr, (unsigned int) mask,
|
||||
(options & L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH?
|
||||
"access=%s, wprot=%s\n",
|
||||
index, (unsigned int) addr, (unsigned int) mask,
|
||||
(options & L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH?
|
||||
"WRITETHROUGH":"UNCACHED"),
|
||||
(options & L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE? "ENABLE":"DISABLE")
|
||||
);
|
||||
@@ -1573,7 +1573,7 @@ int l2cache_mtrr_enable(int index, uint32_t addr, uint32_t mask, int options,
|
||||
|
||||
/* Setup L2CACHE:
|
||||
* Parameters:
|
||||
* -options: Can be:
|
||||
* -options: Can be:
|
||||
*/
|
||||
int l2cache_mtrr_disable(int index)
|
||||
{
|
||||
@@ -1595,7 +1595,7 @@ int l2cache_mtrr_disable(int index)
|
||||
}
|
||||
|
||||
/* Configure mtrr */
|
||||
l2cache_reg_mtrr_set(index, 0, 0, L2C_MTRR_ACCESSCONTROL_DISABLE);
|
||||
l2cache_reg_mtrr_set(index, 0, 0, L2C_MTRR_ACCESSCONTROL_DISABLE);
|
||||
|
||||
DBG("MTRR[%d] disabled\n", index);
|
||||
|
||||
@@ -1623,14 +1623,14 @@ int l2cache_print(void)
|
||||
" MTRR:%d, FT:%s, Locked:%d, Split:%s\n"
|
||||
" REPL:%s, WP:%s, EDAC:%s, Enabled:%s\n"
|
||||
" Scrub:%s, S-Delay:%d\n",
|
||||
priv->ways,
|
||||
priv->waysize,
|
||||
priv->linesize,
|
||||
(priv->index * priv->ways),
|
||||
priv->mtrr,
|
||||
priv->ways,
|
||||
priv->waysize,
|
||||
priv->linesize,
|
||||
(priv->index * priv->ways),
|
||||
priv->mtrr,
|
||||
(priv->ft_support? "Available":"N/A"),
|
||||
L2CACHE_LOCKED_WAYS(status),
|
||||
(priv->split_support? (L2CACHE_SPLIT_ENABLED(status)?
|
||||
(priv->split_support? (L2CACHE_SPLIT_ENABLED(status)?
|
||||
"Enabled":"Disabled"):"N/A"),
|
||||
repl_names[L2CACHE_REPL(status)],
|
||||
(L2CACHE_WRITETHROUGH(status)? "Write-through":"Write-back"),
|
||||
@@ -1990,7 +1990,7 @@ int l2cache_isr_register(l2cache_isr_t isr, void * arg, int options)
|
||||
/* First time registering an ISR */
|
||||
if (priv->isr == NULL){
|
||||
/* Install and Enable L2CACHE interrupt handler */
|
||||
drvmgr_interrupt_register(priv->dev, 0, priv->devname, l2cache_isr,
|
||||
drvmgr_interrupt_register(priv->dev, 0, priv->devname, l2cache_isr,
|
||||
priv);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user