From ecaa0f8e938df48d17af96d6d9a2afec591b6cab Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 19 Dec 2024 16:25:19 -0600 Subject: [PATCH] SPARC64: Remove obsolete architecture Updates rtems/rtos/rtems#5021 --- bsps/sparc64/include/arch/arch.h | 65 -- bsps/sparc64/include/arch/boot.h | 98 -- bsps/sparc64/include/arch/mm/cache_spec.h | 58 -- bsps/sparc64/include/arch/mm/doxygen.h | 23 - bsps/sparc64/include/arch/mm/frame.h | 51 - bsps/sparc64/include/arch/mm/mmu.h | 52 - bsps/sparc64/include/arch/mm/page.h | 84 -- bsps/sparc64/include/arch/mm/sun4u/frame.h | 87 -- bsps/sparc64/include/arch/mm/sun4u/mmu.h | 123 --- bsps/sparc64/include/arch/mm/sun4u/page.h | 84 -- bsps/sparc64/include/arch/mm/sun4u/tlb.h | 693 ------------- bsps/sparc64/include/arch/mm/sun4u/tte.h | 104 -- bsps/sparc64/include/arch/mm/tlb.h | 51 - bsps/sparc64/include/arch/mm/tte.h | 51 - bsps/sparc64/include/arch/regdef.h | 67 -- bsps/sparc64/include/arch/stack.h | 72 -- bsps/sparc64/include/arch/sun4u/arch.h | 47 - bsps/sparc64/include/asm.h | 32 - bsps/sparc64/include/boot/align.h | 48 - bsps/sparc64/include/boot/balloc.h | 52 - bsps/sparc64/include/boot/gentypes.h | 44 - bsps/sparc64/include/boot/main.h | 75 -- bsps/sparc64/include/boot/ofw.h | 117 --- bsps/sparc64/include/boot/ofw_tree.h | 61 -- bsps/sparc64/include/boot/ofwarch.h | 41 - bsps/sparc64/include/boot/register.h | 39 - bsps/sparc64/include/boot/types.h | 44 - bsps/sparc64/include/genarch/ofw/ofw_tree.h | 88 -- bsps/sparc64/include/kernel/align.h | 59 -- bsps/sparc64/include/traptable.h | 40 - bsps/sparc64/niagara/README.md | 74 -- bsps/sparc64/niagara/config/niagara.cfg | 16 - bsps/sparc64/niagara/include/bsp.h | 80 -- bsps/sparc64/niagara/include/bsp/irq.h | 1 - bsps/sparc64/niagara/include/tm27.h | 1 - bsps/sparc64/niagara/start/bspclean.c | 39 - bsps/sparc64/niagara/start/bspinit.S | 54 - bsps/sparc64/niagara/start/m5op.h | 90 -- bsps/sparc64/niagara/start/m5op_sparc.S | 153 --- bsps/sparc64/niagara/start/m5ops.h | 83 -- bsps/sparc64/shared/clock/ckinit.c | 136 --- bsps/sparc64/shared/console/conscfg.c | 115 --- bsps/sparc64/shared/doxygen.h | 15 - bsps/sparc64/shared/helenos/LICENSE.md | 13 - bsps/sparc64/shared/helenos/README.md | 52 - .../shared/helenos/boot/genarch/balloc.c | 72 -- .../sparc64/shared/helenos/boot/genarch/ofw.c | 464 --------- .../shared/helenos/boot/genarch/ofw_tree.c | 255 ----- .../shared/helenos/boot/sparc64/loader/main.c | 441 -------- .../helenos/boot/sparc64/loader/ofwarch.c | 182 ---- .../helenos/boot/sparc64/loader/ofwasm.S | 62 -- .../shared/helenos/kernel/sparc64/src/cache.S | 49 - .../kernel/sparc64/src/sun4u/takemmu.S | 505 ---------- bsps/sparc64/shared/start/halt.S | 36 - bsps/sparc64/shared/start/linkcmds | 201 ---- bsps/sparc64/shared/start/setvec.c | 57 -- bsps/sparc64/shared/start/start.S | 144 --- bsps/sparc64/shared/start/trap_table.S | 174 ---- bsps/sparc64/usiii/README.md | 63 -- bsps/sparc64/usiii/config/usiii.cfg | 16 - bsps/sparc64/usiii/include/bsp.h | 81 -- bsps/sparc64/usiii/include/bsp/irq.h | 1 - bsps/sparc64/usiii/include/tm27.h | 1 - bsps/sparc64/usiii/start/bspinit.S | 72 -- cpukit/score/cpu/sparc64/README.md | 14 - cpukit/score/cpu/sparc64/context.S | 327 ------ cpukit/score/cpu/sparc64/cpu.c | 359 ------- cpukit/score/cpu/sparc64/include/rtems/asm.h | 115 --- .../cpu/sparc64/include/rtems/score/cpu.h | 946 ------------------ .../cpu/sparc64/include/rtems/score/cpuimpl.h | 106 -- .../cpu/sparc64/include/rtems/score/sparc64.h | 361 ------- cpukit/score/cpu/sparc64/interrupt.S | 561 ----------- .../sparc64/sparc64-exception-frame-print.c | 37 - cpukit/score/cpu/sparc64/sparc64-syscall.S | 145 --- cpukit/score/cpu/sparc64/sparc64-syscall.h | 18 - spec/build/bsps/sparc64/grp.yml | 61 -- spec/build/bsps/sparc64/niagara/abi.yml | 19 - .../build/bsps/sparc64/niagara/bspniagara.yml | 63 -- spec/build/bsps/sparc64/start.yml | 14 - spec/build/bsps/sparc64/usiii/abi.yml | 20 - spec/build/bsps/sparc64/usiii/bspusiii.yml | 67 -- .../bsps/sparc64/usiii/optclkfastidle.yml | 16 - spec/build/cpukit/cpusparc64.yml | 30 - spec/build/cpukit/librtemscpu.yml | 2 - 84 files changed, 9629 deletions(-) delete mode 100644 bsps/sparc64/include/arch/arch.h delete mode 100644 bsps/sparc64/include/arch/boot.h delete mode 100644 bsps/sparc64/include/arch/mm/cache_spec.h delete mode 100644 bsps/sparc64/include/arch/mm/doxygen.h delete mode 100644 bsps/sparc64/include/arch/mm/frame.h delete mode 100644 bsps/sparc64/include/arch/mm/mmu.h delete mode 100644 bsps/sparc64/include/arch/mm/page.h delete mode 100644 bsps/sparc64/include/arch/mm/sun4u/frame.h delete mode 100644 bsps/sparc64/include/arch/mm/sun4u/mmu.h delete mode 100644 bsps/sparc64/include/arch/mm/sun4u/page.h delete mode 100644 bsps/sparc64/include/arch/mm/sun4u/tlb.h delete mode 100644 bsps/sparc64/include/arch/mm/sun4u/tte.h delete mode 100644 bsps/sparc64/include/arch/mm/tlb.h delete mode 100644 bsps/sparc64/include/arch/mm/tte.h delete mode 100644 bsps/sparc64/include/arch/regdef.h delete mode 100644 bsps/sparc64/include/arch/stack.h delete mode 100644 bsps/sparc64/include/arch/sun4u/arch.h delete mode 100644 bsps/sparc64/include/asm.h delete mode 100644 bsps/sparc64/include/boot/align.h delete mode 100644 bsps/sparc64/include/boot/balloc.h delete mode 100644 bsps/sparc64/include/boot/gentypes.h delete mode 100644 bsps/sparc64/include/boot/main.h delete mode 100644 bsps/sparc64/include/boot/ofw.h delete mode 100644 bsps/sparc64/include/boot/ofw_tree.h delete mode 100644 bsps/sparc64/include/boot/ofwarch.h delete mode 100644 bsps/sparc64/include/boot/register.h delete mode 100644 bsps/sparc64/include/boot/types.h delete mode 100644 bsps/sparc64/include/genarch/ofw/ofw_tree.h delete mode 100644 bsps/sparc64/include/kernel/align.h delete mode 100644 bsps/sparc64/include/traptable.h delete mode 100644 bsps/sparc64/niagara/README.md delete mode 100644 bsps/sparc64/niagara/config/niagara.cfg delete mode 100644 bsps/sparc64/niagara/include/bsp.h delete mode 100644 bsps/sparc64/niagara/include/bsp/irq.h delete mode 100644 bsps/sparc64/niagara/include/tm27.h delete mode 100644 bsps/sparc64/niagara/start/bspclean.c delete mode 100644 bsps/sparc64/niagara/start/bspinit.S delete mode 100644 bsps/sparc64/niagara/start/m5op.h delete mode 100644 bsps/sparc64/niagara/start/m5op_sparc.S delete mode 100644 bsps/sparc64/niagara/start/m5ops.h delete mode 100644 bsps/sparc64/shared/clock/ckinit.c delete mode 100644 bsps/sparc64/shared/console/conscfg.c delete mode 100644 bsps/sparc64/shared/doxygen.h delete mode 100644 bsps/sparc64/shared/helenos/LICENSE.md delete mode 100644 bsps/sparc64/shared/helenos/README.md delete mode 100644 bsps/sparc64/shared/helenos/boot/genarch/balloc.c delete mode 100644 bsps/sparc64/shared/helenos/boot/genarch/ofw.c delete mode 100644 bsps/sparc64/shared/helenos/boot/genarch/ofw_tree.c delete mode 100644 bsps/sparc64/shared/helenos/boot/sparc64/loader/main.c delete mode 100644 bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwarch.c delete mode 100644 bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwasm.S delete mode 100644 bsps/sparc64/shared/helenos/kernel/sparc64/src/cache.S delete mode 100644 bsps/sparc64/shared/helenos/kernel/sparc64/src/sun4u/takemmu.S delete mode 100644 bsps/sparc64/shared/start/halt.S delete mode 100644 bsps/sparc64/shared/start/linkcmds delete mode 100644 bsps/sparc64/shared/start/setvec.c delete mode 100644 bsps/sparc64/shared/start/start.S delete mode 100644 bsps/sparc64/shared/start/trap_table.S delete mode 100644 bsps/sparc64/usiii/README.md delete mode 100644 bsps/sparc64/usiii/config/usiii.cfg delete mode 100644 bsps/sparc64/usiii/include/bsp.h delete mode 100644 bsps/sparc64/usiii/include/bsp/irq.h delete mode 100644 bsps/sparc64/usiii/include/tm27.h delete mode 100644 bsps/sparc64/usiii/start/bspinit.S delete mode 100644 cpukit/score/cpu/sparc64/README.md delete mode 100644 cpukit/score/cpu/sparc64/context.S delete mode 100644 cpukit/score/cpu/sparc64/cpu.c delete mode 100644 cpukit/score/cpu/sparc64/include/rtems/asm.h delete mode 100644 cpukit/score/cpu/sparc64/include/rtems/score/cpu.h delete mode 100644 cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h delete mode 100644 cpukit/score/cpu/sparc64/include/rtems/score/sparc64.h delete mode 100644 cpukit/score/cpu/sparc64/interrupt.S delete mode 100644 cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c delete mode 100644 cpukit/score/cpu/sparc64/sparc64-syscall.S delete mode 100644 cpukit/score/cpu/sparc64/sparc64-syscall.h delete mode 100644 spec/build/bsps/sparc64/grp.yml delete mode 100644 spec/build/bsps/sparc64/niagara/abi.yml delete mode 100644 spec/build/bsps/sparc64/niagara/bspniagara.yml delete mode 100644 spec/build/bsps/sparc64/start.yml delete mode 100644 spec/build/bsps/sparc64/usiii/abi.yml delete mode 100644 spec/build/bsps/sparc64/usiii/bspusiii.yml delete mode 100644 spec/build/bsps/sparc64/usiii/optclkfastidle.yml delete mode 100644 spec/build/cpukit/cpusparc64.yml diff --git a/bsps/sparc64/include/arch/arch.h b/bsps/sparc64/include/arch/arch.h deleted file mode 100644 index 08598b4edb..0000000000 --- a/bsps/sparc64/include/arch/arch.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64 - * @{ - */ -/** - * @file - * @brief Various sparc64-specific macros. - */ - -#ifndef KERN_sparc64_ARCH_H_ -#define KERN_sparc64_ARCH_H_ - -#include - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#else -#error "No SUN model defined" -#endif - -#define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ -#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ - -#define NWINDOWS 8 /** Number of register window sets. */ - -#ifndef __ASM__ - -extern void arch_pre_main(void); - -#endif /* __ASM__ */ - - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/boot.h b/bsps/sparc64/include/arch/boot.h deleted file mode 100644 index e95880d248..0000000000 --- a/bsps/sparc64/include/arch/boot.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_BOOT_H_ -#define KERN_sparc64_BOOT_H_ - -#if 0 -#define VMA 0x400000 -#endif -#define VMA 0x4000 -#define LMA VMA - -#ifndef __ASM__ -#ifndef __LINKER__ - -#include -#include -#include - -#define TASKMAP_MAX_RECORDS 32 -#define MEMMAP_MAX_RECORDS 32 - -#define BOOTINFO_TASK_NAME_BUFLEN 32 - -typedef struct { - void * addr; - uint32_t size; - char name[BOOTINFO_TASK_NAME_BUFLEN]; -} utask_t; - -typedef struct { - uint32_t count; - utask_t tasks[TASKMAP_MAX_RECORDS]; -} taskmap_t; - -typedef struct { - uintptr_t start; - uint32_t size; -} memzone_t; - -typedef struct { - uint32_t total; - uint32_t count; - memzone_t zones[MEMMAP_MAX_RECORDS]; -} memmap_t; - -/** Bootinfo structure. - * - * Must be in sync with bootinfo structure used by the boot loader. - */ -typedef struct { - uintptr_t physmem_start; - taskmap_t taskmap; - memmap_t memmap; - ballocs_t ballocs; - ofw_tree_node_t *ofw_root; -} bootinfo_t; - -extern bootinfo_t bootinfo; - -#endif -#endif - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/cache_spec.h b/bsps/sparc64/include/arch/mm/cache_spec.h deleted file mode 100644 index ab92e09f03..0000000000 --- a/bsps/sparc64/include/arch/mm/cache_spec.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2008 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_CACHE_SPEC_H_ -#define KERN_sparc64_CACHE_SPEC_H_ - -/* - * The following macros are valid for the following processors: - * - * UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III, - * UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+ - * - * Should we support other UltraSPARC processors, we need to make sure that - * the macros are defined correctly for them. - */ - -#if defined (US) -#define DCACHE_SIZE (16 * 1024) -#elif defined (US3) -#define DCACHE_SIZE (64 * 1024) -#endif -#define DCACHE_LINE_SIZE 32 - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/doxygen.h b/bsps/sparc64/include/arch/mm/doxygen.h deleted file mode 100644 index fbdb721d20..0000000000 --- a/bsps/sparc64/include/arch/mm/doxygen.h +++ /dev/null @@ -1,23 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSImplDoxygen - * - * @brief This header file defines sparc64-specific groups. - */ - -/** - * @defgroup RTEMSBSPsSPARC64mm MM - * - * @ingroup RTEMSBSPsSPARC64 - * - * @brief MM - */ - -/** - * @defgroup RTEMSBSPsSPARC64Generic Generic - * - * @ingroup RTEMSBSPsSPARC64 - * - * @brief Generic - */ diff --git a/bsps/sparc64/include/arch/mm/frame.h b/bsps/sparc64/include/arch/mm/frame.h deleted file mode 100644 index 35f092b31b..0000000000 --- a/bsps/sparc64/include/arch/mm/frame.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_FRAME_H_ -#define KERN_sparc64_FRAME_H_ - -#include - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#else -#error "No SUN model defined" -#endif - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/mmu.h b/bsps/sparc64/include/arch/mm/mmu.h deleted file mode 100644 index 30489e0823..0000000000 --- a/bsps/sparc64/include/arch/mm/mmu.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_MMU_H_ -#define KERN_sparc64_MMU_H_ - -#include - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#else -#error "No SUN model defined" -#endif - - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/page.h b/bsps/sparc64/include/arch/mm/page.h deleted file mode 100644 index 8e578059c3..0000000000 --- a/bsps/sparc64/include/arch/mm/page.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_PAGE_H_ -#define KERN_sparc64_PAGE_H_ - -#include - -/* - * On the TLB and TSB level, we still use 8K pages, which are supported by the - * MMU. - */ -#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH -#define MMU_PAGE_SIZE MMU_FRAME_SIZE - -/* - * On the page table level, we use 16K pages. 16K pages are not supported by - * the MMU but we emulate them with pairs of 8K pages. - */ -#define PAGE_WIDTH FRAME_WIDTH -#define PAGE_SIZE FRAME_SIZE - -#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) - -#ifdef KERNEL - -#ifndef __ASM__ - -#include - -extern uintptr_t physmem_base; - -#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) -#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) - -typedef union { - uintptr_t address; - struct { - uint64_t vpn : 51; /**< Virtual Page Number. */ - unsigned offset : 13; /**< Offset. */ - } __attribute__ ((packed)); -} page_address_t; - -extern void page_arch_init(void); - -#endif /* !def __ASM__ */ - -#endif /* KERNEL */ - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/frame.h b/bsps/sparc64/include/arch/mm/sun4u/frame.h deleted file mode 100644 index 5b45430917..0000000000 --- a/bsps/sparc64/include/arch/mm/sun4u/frame.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_SUN4U_FRAME_H_ -#define KERN_sparc64_SUN4U_FRAME_H_ - -/* - * Page size supported by the MMU. - * For 8K there is the nasty illegal virtual aliasing problem. - * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. - */ -#define MMU_FRAME_WIDTH 13 /* 8K */ -#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) - -/* - * Page size exported to the generic memory management subsystems. - * This page size is not directly supported by the MMU, but we can emulate - * each 16K page with a pair of adjacent 8K pages. - */ -#define FRAME_WIDTH 14 /* 16K */ -#define FRAME_SIZE (1 << FRAME_WIDTH) - -#ifdef KERNEL -#ifndef __ASM__ - -#include - -union frame_address { - uintptr_t address; - struct { -#if defined (US) - unsigned : 23; - uint64_t pfn : 28; /**< Physical Frame Number. */ -#elif defined (US3) - unsigned : 21; - uint64_t pfn : 30; /**< Physical Frame Number. */ -#endif - unsigned offset : 13; /**< Offset. */ - } __attribute__ ((packed)); -}; - -typedef union frame_address frame_address_t; - -extern uintptr_t last_frame; -extern uintptr_t end_of_identity; - -extern void frame_arch_init(void); -#define physmem_print() - -#endif -#endif - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/mmu.h b/bsps/sparc64/include/arch/mm/sun4u/mmu.h deleted file mode 100644 index 91235c6450..0000000000 --- a/bsps/sparc64/include/arch/mm/sun4u/mmu.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4u_MMU_H_ -#define KERN_sparc64_sun4u_MMU_H_ - -#if defined(US) -/* LSU Control Register ASI. */ -#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ -#endif - -/* I-MMU ASIs. */ -#define ASI_IMMU 0x50 -#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 -#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 -#define ASI_ITLB_DATA_IN_REG 0x54 -#define ASI_ITLB_DATA_ACCESS_REG 0x55 -#define ASI_ITLB_TAG_READ_REG 0x56 -#define ASI_IMMU_DEMAP 0x57 - -/* Virtual Addresses within ASI_IMMU. */ -#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ -#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ -#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ -#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ -#if defined (US3) -#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ -#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ -#endif - - -/* D-MMU ASIs. */ -#define ASI_DMMU 0x58 -#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 -#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a -#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b -#define ASI_DTLB_DATA_IN_REG 0x5c -#define ASI_DTLB_DATA_ACCESS_REG 0x5d -#define ASI_DTLB_TAG_READ_REG 0x5e -#define ASI_DMMU_DEMAP 0x5f - -/* Virtual Addresses within ASI_DMMU. */ -#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ -#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ -#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ -#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ -#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ -#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ -#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ -#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ -#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ -#if defined (US3) -#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ -#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ -#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ -#endif - -#ifndef __ASM__ - -#include -#include -#include - -#if defined(US) -/** LSU Control Register. */ -typedef union { - uint64_t value; - struct { - unsigned : 23; - unsigned pm : 8; - unsigned vm : 8; - unsigned pr : 1; - unsigned pw : 1; - unsigned vr : 1; - unsigned vw : 1; - unsigned : 1; - unsigned fm : 16; - unsigned dm : 1; /**< D-MMU enable. */ - unsigned im : 1; /**< I-MMU enable. */ - unsigned dc : 1; /**< D-Cache enable. */ - unsigned ic : 1; /**< I-Cache enable. */ - - } __attribute__ ((packed)); -} lsu_cr_reg_t; -#endif /* US */ - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/page.h b/bsps/sparc64/include/arch/mm/sun4u/page.h deleted file mode 100644 index 8e578059c3..0000000000 --- a/bsps/sparc64/include/arch/mm/sun4u/page.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_PAGE_H_ -#define KERN_sparc64_PAGE_H_ - -#include - -/* - * On the TLB and TSB level, we still use 8K pages, which are supported by the - * MMU. - */ -#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH -#define MMU_PAGE_SIZE MMU_FRAME_SIZE - -/* - * On the page table level, we use 16K pages. 16K pages are not supported by - * the MMU but we emulate them with pairs of 8K pages. - */ -#define PAGE_WIDTH FRAME_WIDTH -#define PAGE_SIZE FRAME_SIZE - -#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) - -#ifdef KERNEL - -#ifndef __ASM__ - -#include - -extern uintptr_t physmem_base; - -#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) -#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) - -typedef union { - uintptr_t address; - struct { - uint64_t vpn : 51; /**< Virtual Page Number. */ - unsigned offset : 13; /**< Offset. */ - } __attribute__ ((packed)); -} page_address_t; - -extern void page_arch_init(void); - -#endif /* !def __ASM__ */ - -#endif /* KERNEL */ - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/tlb.h b/bsps/sparc64/include/arch/mm/sun4u/tlb.h deleted file mode 100644 index c983e53f46..0000000000 --- a/bsps/sparc64/include/arch/mm/sun4u/tlb.h +++ /dev/null @@ -1,693 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TLB_sun4u_H_ -#define KERN_sparc64_TLB_sun4u_H_ - -#if defined (US) -#define ITLB_ENTRY_COUNT 64 -#define DTLB_ENTRY_COUNT 64 -#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT -#endif - -/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ -#if defined (US3) -#define DTLB_MAX_LOCKED_ENTRIES 16 -#endif - -#define MEM_CONTEXT_KERNEL 0 -#define MEM_CONTEXT_TEMP 1 - -/** Page sizes. */ -#define PAGESIZE_8K 0 -#define PAGESIZE_64K 1 -#define PAGESIZE_512K 2 -#define PAGESIZE_4M 3 - -/** Bit width of the TLB-locked portion of kernel address space. */ -#define KERNEL_PAGE_WIDTH 22 /* 4M */ - -/* TLB Demap Operation types. */ -#define TLB_DEMAP_PAGE 0 -#define TLB_DEMAP_CONTEXT 1 -#if defined (US3) -#define TLB_DEMAP_ALL 2 -#endif - -#define TLB_DEMAP_TYPE_SHIFT 6 - -/* TLB Demap Operation Context register encodings. */ -#define TLB_DEMAP_PRIMARY 0 -#define TLB_DEMAP_SECONDARY 1 -#define TLB_DEMAP_NUCLEUS 2 - -/* There are more TLBs in one MMU in US3, their codes are defined here. */ -#if defined (US3) -/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ -#define TLB_DSMALL 0 -#define TLB_DBIG_0 2 -#define TLB_DBIG_1 3 - -/* I-MMU: one small (16-entry) TLB and one big TLB */ -#define TLB_ISMALL 0 -#define TLB_IBIG 2 -#endif - -#define TLB_DEMAP_CONTEXT_SHIFT 4 - -/* TLB Tag Access shifts */ -#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 -#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) -#define TLB_TAG_ACCESS_VPN_SHIFT 13 - -#ifndef __ASM__ - -#include -#include -#include -#include -#include -#include -#include -#include - -union tlb_context_reg { - uint64_t v; - struct { - unsigned long : 51; - unsigned context : 13; /**< Context/ASID. */ - } __attribute__ ((packed)); -}; -typedef union tlb_context_reg tlb_context_reg_t; - -/** I-/D-TLB Data In/Access Register type. */ -typedef tte_data_t tlb_data_t; - -/** I-/D-TLB Data Access Address in Alternate Space. */ - -#if defined (US) - -union tlb_data_access_addr { - uint64_t value; - struct { - uint64_t : 55; - unsigned tlb_entry : 6; - unsigned : 3; - } __attribute__ ((packed)); -}; -typedef union tlb_data_access_addr dtlb_data_access_addr_t; -typedef union tlb_data_access_addr dtlb_tag_read_addr_t; -typedef union tlb_data_access_addr itlb_data_access_addr_t; -typedef union tlb_data_access_addr itlb_tag_read_addr_t; - -#elif defined (US3) - -/* - * In US3, I-MMU and D-MMU have different formats of the data - * access register virtual address. In the corresponding - * structures the member variable for the entry number is - * called "local_tlb_entry" - it contrasts with the "tlb_entry" - * for the US data access register VA structure. The rationale - * behind this is to prevent careless mistakes in the code - * caused by setting only the entry number and not the TLB - * number in the US3 code (when taking the code from US). - */ - -union dtlb_data_access_addr { - uint64_t value; - struct { - uint64_t : 45; - unsigned : 1; - unsigned tlb_number : 2; - unsigned : 4; - unsigned local_tlb_entry : 9; - unsigned : 3; - } __attribute__ ((packed)); -}; -typedef union dtlb_data_access_addr dtlb_data_access_addr_t; -typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; - -union itlb_data_access_addr { - uint64_t value; - struct { - uint64_t : 45; - unsigned : 1; - unsigned tlb_number : 2; - unsigned : 6; - unsigned local_tlb_entry : 7; - unsigned : 3; - } __attribute__ ((packed)); -}; -typedef union itlb_data_access_addr itlb_data_access_addr_t; -typedef union itlb_data_access_addr itlb_tag_read_addr_t; - -#endif - -/** I-/D-TLB Tag Read Register. */ -union tlb_tag_read_reg { - uint64_t value; - struct { - uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ - unsigned context : 13; /**< Context identifier. */ - } __attribute__ ((packed)); -}; -typedef union tlb_tag_read_reg tlb_tag_read_reg_t; -typedef union tlb_tag_read_reg tlb_tag_access_reg_t; - - -/** TLB Demap Operation Address. */ -union tlb_demap_addr { - uint64_t value; - struct { - uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ -#if defined (US) - unsigned : 6; /**< Ignored. */ - unsigned type : 1; /**< The type of demap operation. */ -#elif defined (US3) - unsigned : 5; /**< Ignored. */ - unsigned type: 2; /**< The type of demap operation. */ -#endif - unsigned context : 2; /**< Context register selection. */ - unsigned : 4; /**< Zero. */ - } __attribute__ ((packed)); -}; -typedef union tlb_demap_addr tlb_demap_addr_t; - -/** TLB Synchronous Fault Status Register. */ -union tlb_sfsr_reg { - uint64_t value; - struct { -#if defined (US) - unsigned long : 40; /**< Implementation dependent. */ - unsigned asi : 8; /**< ASI. */ - unsigned : 2; - unsigned ft : 7; /**< Fault type. */ -#elif defined (US3) - unsigned long : 39; /**< Implementation dependent. */ - unsigned nf : 1; /**< Non-faulting load. */ - unsigned asi : 8; /**< ASI. */ - unsigned tm : 1; /**< I-TLB miss. */ - unsigned : 3; /**< Reserved. */ - unsigned ft : 5; /**< Fault type. */ -#endif - unsigned e : 1; /**< Side-effect bit. */ - unsigned ct : 2; /**< Context Register selection. */ - unsigned pr : 1; /**< Privilege bit. */ - unsigned w : 1; /**< Write bit. */ - unsigned ow : 1; /**< Overwrite bit. */ - unsigned fv : 1; /**< Fault Valid bit. */ - } __attribute__ ((packed)); -}; -typedef union tlb_sfsr_reg tlb_sfsr_reg_t; - -#if defined (US3) - -/* - * Functions for determining the number of entries in TLBs. They either return - * a constant value or a value based on the CPU autodetection. - */ - -/** - * Determine the number of entries in the DMMU's small TLB. - */ -static inline uint16_t tlb_dsmall_size(void) -{ - return 16; -} - -/** - * Determine the number of entries in each DMMU's big TLB. - */ -static inline uint16_t tlb_dbig_size(void) -{ - return 512; -} - -/** - * Determine the number of entries in the IMMU's small TLB. - */ -static inline uint16_t tlb_ismall_size(void) -{ - return 16; -} - -/** - * Determine the number of entries in the IMMU's big TLB. - */ -static inline uint16_t tlb_ibig_size(void) -{ - if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) - return 512; - else - return 128; -} - -#endif - -/** Read MMU Primary Context Register. - * - * @return Current value of Primary Context Register. - */ -static inline uint64_t mmu_primary_context_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); -} - -/** Write MMU Primary Context Register. - * - * @param v New value of Primary Context Register. - */ -static inline void mmu_primary_context_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); - flush_pipeline(); -} - -/** Read MMU Secondary Context Register. - * - * @return Current value of Secondary Context Register. - */ -static inline uint64_t mmu_secondary_context_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); -} - -/** Write MMU Primary Context Register. - * - * @param v New value of Primary Context Register. - */ -static inline void mmu_secondary_context_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); - flush_pipeline(); -} - -#if defined (US) - -/** Read IMMU TLB Data Access Register. - * - * @param entry TLB Entry index. - * - * @return Current value of specified IMMU TLB Data Access - * Register. - */ -static inline uint64_t itlb_data_access_read(size_t entry) -{ - itlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_entry = entry; - return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); -} - -/** Write IMMU TLB Data Access Register. - * - * @param entry TLB Entry index. - * @param value Value to be written. - */ -static inline void itlb_data_access_write(size_t entry, uint64_t value) -{ - itlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_entry = entry; - asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); - flush_pipeline(); -} - -/** Read DMMU TLB Data Access Register. - * - * @param entry TLB Entry index. - * - * @return Current value of specified DMMU TLB Data Access - * Register. - */ -static inline uint64_t dtlb_data_access_read(size_t entry) -{ - dtlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_entry = entry; - return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); -} - -/** Write DMMU TLB Data Access Register. - * - * @param entry TLB Entry index. - * @param value Value to be written. - */ -static inline void dtlb_data_access_write(size_t entry, uint64_t value) -{ - dtlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_entry = entry; - asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); - membar(); -} - -/** Read IMMU TLB Tag Read Register. - * - * @param entry TLB Entry index. - * - * @return Current value of specified IMMU TLB Tag Read Register. - */ -static inline uint64_t itlb_tag_read_read(size_t entry) -{ - itlb_tag_read_addr_t tag; - - tag.value = 0; - tag.tlb_entry = entry; - return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); -} - -/** Read DMMU TLB Tag Read Register. - * - * @param entry TLB Entry index. - * - * @return Current value of specified DMMU TLB Tag Read Register. - */ -static inline uint64_t dtlb_tag_read_read(size_t entry) -{ - dtlb_tag_read_addr_t tag; - - tag.value = 0; - tag.tlb_entry = entry; - return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); -} - -#elif defined (US3) - - -/** Read IMMU TLB Data Access Register. - * - * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) - * @param entry TLB Entry index. - * - * @return Current value of specified IMMU TLB Data Access - * Register. - */ -static inline uint64_t itlb_data_access_read(int tlb, size_t entry) -{ - itlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_number = tlb; - reg.local_tlb_entry = entry; - return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); -} - -/** Write IMMU TLB Data Access Register. - * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) - * @param entry TLB Entry index. - * @param value Value to be written. - */ -static inline void itlb_data_access_write(int tlb, size_t entry, - uint64_t value) -{ - itlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_number = tlb; - reg.local_tlb_entry = entry; - asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); - flush_pipeline(); -} - -/** Read DMMU TLB Data Access Register. - * - * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) - * @param entry TLB Entry index. - * - * @return Current value of specified DMMU TLB Data Access - * Register. - */ -static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) -{ - dtlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_number = tlb; - reg.local_tlb_entry = entry; - return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); -} - -/** Write DMMU TLB Data Access Register. - * - * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) - * @param entry TLB Entry index. - * @param value Value to be written. - */ -static inline void dtlb_data_access_write(int tlb, size_t entry, - uint64_t value) -{ - dtlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_number = tlb; - reg.local_tlb_entry = entry; - asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); - membar(); -} - -/** Read IMMU TLB Tag Read Register. - * - * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) - * @param entry TLB Entry index. - * - * @return Current value of specified IMMU TLB Tag Read Register. - */ -static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) -{ - itlb_tag_read_addr_t tag; - - tag.value = 0; - tag.tlb_number = tlb; - tag.local_tlb_entry = entry; - return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); -} - -/** Read DMMU TLB Tag Read Register. - * - * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) - * @param entry TLB Entry index. - * - * @return Current value of specified DMMU TLB Tag Read Register. - */ -static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) -{ - dtlb_tag_read_addr_t tag; - - tag.value = 0; - tag.tlb_number = tlb; - tag.local_tlb_entry = entry; - return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); -} - -#endif - - -/** Write IMMU TLB Tag Access Register. - * - * @param v Value to be written. - */ -static inline void itlb_tag_access_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); - flush_pipeline(); -} - -/** Read IMMU TLB Tag Access Register. - * - * @return Current value of IMMU TLB Tag Access Register. - */ -static inline uint64_t itlb_tag_access_read(void) -{ - return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); -} - -/** Write DMMU TLB Tag Access Register. - * - * @param v Value to be written. - */ -static inline void dtlb_tag_access_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); - membar(); -} - -/** Read DMMU TLB Tag Access Register. - * - * @return Current value of DMMU TLB Tag Access Register. - */ -static inline uint64_t dtlb_tag_access_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); -} - - -/** Write IMMU TLB Data in Register. - * - * @param v Value to be written. - */ -static inline void itlb_data_in_write(uint64_t v) -{ - asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); - flush_pipeline(); -} - -/** Write DMMU TLB Data in Register. - * - * @param v Value to be written. - */ -static inline void dtlb_data_in_write(uint64_t v) -{ - asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); - membar(); -} - -/** Read ITLB Synchronous Fault Status Register. - * - * @return Current content of I-SFSR register. - */ -static inline uint64_t itlb_sfsr_read(void) -{ - return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); -} - -/** Write ITLB Synchronous Fault Status Register. - * - * @param v New value of I-SFSR register. - */ -static inline void itlb_sfsr_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); - flush_pipeline(); -} - -/** Read DTLB Synchronous Fault Status Register. - * - * @return Current content of D-SFSR register. - */ -static inline uint64_t dtlb_sfsr_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); -} - -/** Write DTLB Synchronous Fault Status Register. - * - * @param v New value of D-SFSR register. - */ -static inline void dtlb_sfsr_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); - membar(); -} - -/** Read DTLB Synchronous Fault Address Register. - * - * @return Current content of D-SFAR register. - */ -static inline uint64_t dtlb_sfar_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); -} - -/** Perform IMMU TLB Demap Operation. - * - * @param type Selects between context and page demap (and entire MMU - * demap on US3). - * @param context_encoding Specifies which Context register has Context ID for - * demap. - * @param page Address which is on the page to be demapped. - */ -static inline void itlb_demap(int type, int context_encoding, uintptr_t page) -{ - tlb_demap_addr_t da; - page_address_t pg; - - da.value = 0; - pg.address = page; - - da.type = type; - da.context = context_encoding; - da.vpn = pg.vpn; - - /* da.value is the address within the ASI */ - asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); - - flush_pipeline(); -} - -/** Perform DMMU TLB Demap Operation. - * - * @param type Selects between context and page demap (and entire MMU - * demap on US3). - * @param context_encoding Specifies which Context register has Context ID for - * demap. - * @param page Address which is on the page to be demapped. - */ -static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) -{ - tlb_demap_addr_t da; - page_address_t pg; - - da.value = 0; - pg.address = page; - - da.type = type; - da.context = context_encoding; - da.vpn = pg.vpn; - - /* da.value is the address within the ASI */ - asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); - - membar(); -} - -extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); -extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); -extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); - -extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); - -extern void dump_sfsr_and_sfar(void); -extern void describe_dmmu_fault(void); - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/tte.h b/bsps/sparc64/include/arch/mm/sun4u/tte.h deleted file mode 100644 index ec006e2189..0000000000 --- a/bsps/sparc64/include/arch/mm/sun4u/tte.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4u_TTE_H_ -#define KERN_sparc64_sun4u_TTE_H_ - -#define TTE_G (1 << 0) -#define TTE_W (1 << 1) -#define TTE_P (1 << 2) -#define TTE_E (1 << 3) -#define TTE_CV (1 << 4) -#define TTE_CP (1 << 5) -#define TTE_L (1 << 6) - -#define TTE_V_SHIFT 63 -#define TTE_SIZE_SHIFT 61 - -#ifndef __ASM__ - -#include - -/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */ -#define VA_TAG_PAGE_SHIFT 22 - -/** Translation Table Entry - Tag. */ -union tte_tag { - uint64_t value; - struct { - unsigned g : 1; /**< Global. */ - unsigned : 2; /**< Reserved. */ - unsigned context : 13; /**< Context identifier. */ - unsigned : 6; /**< Reserved. */ - uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */ - } __attribute__ ((packed)); -}; - -typedef union tte_tag tte_tag_t; - -/** Translation Table Entry - Data. */ -union tte_data { - uint64_t value; - struct { - unsigned v : 1; /**< Valid. */ - unsigned size : 2; /**< Page size of this entry. */ - unsigned nfo : 1; /**< No-Fault-Only. */ - unsigned ie : 1; /**< Invert Endianness. */ - unsigned soft2 : 9; /**< Software defined field. */ -#if defined (US) - unsigned diag : 9; /**< Diagnostic data. */ - unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */ -#elif defined (US3) - unsigned : 7; /**< Reserved. */ - unsigned pfn : 30; /**< Physical Address bits, bits 42:13 */ -#endif - unsigned soft : 6; /**< Software defined field. */ - unsigned l : 1; /**< Lock. */ - unsigned cp : 1; /**< Cacheable in physically indexed cache. */ - unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ - unsigned e : 1; /**< Side-effect. */ - unsigned p : 1; /**< Privileged. */ - unsigned w : 1; /**< Writable. */ - unsigned g : 1; /**< Global. */ - } __attribute__ ((packed)); -}; - -typedef union tte_data tte_data_t; - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/tlb.h b/bsps/sparc64/include/arch/mm/tlb.h deleted file mode 100644 index 3e0ae3e423..0000000000 --- a/bsps/sparc64/include/arch/mm/tlb.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TLB_H_ -#define KERN_sparc64_TLB_H_ - -#include - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#else -#error "No SUN model defined" -#endif - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/mm/tte.h b/bsps/sparc64/include/arch/mm/tte.h deleted file mode 100644 index 5b28118d89..0000000000 --- a/bsps/sparc64/include/arch/mm/tte.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TTE_H_ -#define KERN_sparc64_TTE_H_ - -#include - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#else -#error "No SUN model defined" -#endif - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/regdef.h b/bsps/sparc64/include/arch/regdef.h deleted file mode 100644 index 5306cb9e83..0000000000 --- a/bsps/sparc64/include/arch/regdef.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_REGDEF_H_ -#define KERN_sparc64_REGDEF_H_ - -#define PSTATE_IE_BIT (1 << 1) -#define PSTATE_AM_BIT (1 << 3) - -#define PSTATE_AG_BIT (1 << 0) -#define PSTATE_IG_BIT (1 << 11) -#define PSTATE_MG_BIT (1 << 10) - -#define PSTATE_PRIV_BIT (1 << 2) -#define PSTATE_PEF_BIT (1 << 4) - -#define TSTATE_PSTATE_SHIFT 8 -#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT << TSTATE_PSTATE_SHIFT) -#define TSTATE_IE_BIT (PSTATE_IE_BIT << TSTATE_PSTATE_SHIFT) -#define TSTATE_PEF_BIT (PSTATE_PEF_BIT << TSTATE_PSTATE_SHIFT) - -#define TSTATE_CWP_MASK 0x1f - -#define WSTATE_NORMAL(n) (n) -#define WSTATE_OTHER(n) ((n) << 3) - -/* - * The following definitions concern the UPA_CONFIG register on US and the - * FIREPLANE_CONFIG register on US3. - */ -#define ICBUS_CONFIG_MID_SHIFT 17 - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/stack.h b/bsps/sparc64/include/arch/stack.h deleted file mode 100644 index 325167aad0..0000000000 --- a/bsps/sparc64/include/arch/stack.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_STACK_H_ -#define KERN_sparc64_STACK_H_ - -#define STACK_ITEM_SIZE 8 - -/** According to SPARC Compliance Definition, every stack frame is 16-byte aligned. */ -#define STACK_ALIGNMENT 16 - -/** - * 16-extended-word save area for %i[0-7] and %l[0-7] registers. - */ -#define STACK_WINDOW_SAVE_AREA_SIZE (16 * STACK_ITEM_SIZE) - -/** - * Six extended words for first six arguments. - */ -#define STACK_ARG_SAVE_AREA_SIZE (6 * STACK_ITEM_SIZE) - -/** - * By convention, the actual top of the stack is %sp + STACK_BIAS. - */ -#define STACK_BIAS 2047 - -/* - * Offsets of arguments on stack. - */ -#define STACK_ARG0 0 -#define STACK_ARG1 8 -#define STACK_ARG2 16 -#define STACK_ARG3 24 -#define STACK_ARG4 32 -#define STACK_ARG5 40 -#define STACK_ARG6 48 - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/arch/sun4u/arch.h b/bsps/sparc64/include/arch/sun4u/arch.h deleted file mode 100644 index 5da23c04d1..0000000000 --- a/bsps/sparc64/include/arch/sun4u/arch.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64 - * @{ - */ -/** - * @file - * @brief Various sun4u-specific macros. - */ - -#ifndef KERN_sparc64_sun4u_ARCH_H_ -#define KERN_sparc64_sun4u_ARCH_H_ - -#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ -#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ -#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/asm.h b/bsps/sparc64/include/asm.h deleted file mode 100644 index 6f9216574c..0000000000 --- a/bsps/sparc64/include/asm.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * asm.h - * - * Copyright 2010 Gedare Bloom - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - - -extern void halt( void ); - diff --git a/bsps/sparc64/include/boot/align.h b/bsps/sparc64/include/boot/align.h deleted file mode 100644 index 1f0f9562fd..0000000000 --- a/bsps/sparc64/include/boot/align.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64Generic - * @{ - */ -/** @file - */ - -#ifndef BOOT_ALIGN_H_ -#define BOOT_ALIGN_H_ - -/** Align to the nearest higher address. - * - * @param addr Address or size to be aligned. - * @param align Size of alignment, must be power of 2. - */ -#define ALIGN_UP(addr, align) (((addr) + ((align) - 1)) & ~((align) - 1)) - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/boot/balloc.h b/bsps/sparc64/include/boot/balloc.h deleted file mode 100644 index 8e502c0c58..0000000000 --- a/bsps/sparc64/include/boot/balloc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Modifications are made to compile for RTEMS. Move BALLOC_MAX_SIZE from - * asm.h to here. - * - */ - - -#ifndef BOOT_BALLOC_H_ -#define BOOT_BALLOC_H_ - -#include - -#define BALLOC_MAX_SIZE (128 * 1024) - -typedef struct { - uintptr_t base; - size_t size; -} ballocs_t; - -extern void balloc_init(ballocs_t *ball, uintptr_t base, uintptr_t kernel_base); -extern void *balloc(size_t size, size_t alignment); -extern void *balloc_rebase(void *ptr); - -#endif diff --git a/bsps/sparc64/include/boot/gentypes.h b/bsps/sparc64/include/boot/gentypes.h deleted file mode 100644 index bf2fcda064..0000000000 --- a/bsps/sparc64/include/boot/gentypes.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2006 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64Generic - * @{ - */ -/** @file - */ - -#ifndef BOOT_GENTYPES_H_ -#define BOOT_GENTYPES_H_ - -#include -#include - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/boot/main.h b/bsps/sparc64/include/boot/main.h deleted file mode 100644 index 5ddc814ac8..0000000000 --- a/bsps/sparc64/include/boot/main.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2005 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef BOOT_sparc64_MAIN_H_ -#define BOOT_sparc64_MAIN_H_ - -#include -#include -#include -#include - -#define KERNEL_VIRTUAL_ADDRESS 0x400000 - -#define TASKMAP_MAX_RECORDS 32 - -/** Size of buffer for storing task name in task_t. */ -#define BOOTINFO_TASK_NAME_BUFLEN 32 - -#define BSP_PROCESSOR 1 -#define AP_PROCESSOR 0 - -#define SUBARCH_US 1 -#define SUBARCH_US3 3 - -typedef struct { - void *addr; - uint32_t size; - char name[BOOTINFO_TASK_NAME_BUFLEN]; -} task_t; - -typedef struct { - uint32_t count; - task_t tasks[TASKMAP_MAX_RECORDS]; -} taskmap_t; - -typedef struct { - uintptr_t physmem_start; - taskmap_t taskmap; - memmap_t memmap; - ballocs_t ballocs; - ofw_tree_node_t *ofw_root; -} bootinfo_t; - -extern uint32_t silo_ramdisk_image; -extern uint32_t silo_ramdisk_size; - -extern void start(void); -extern void bootstrap(void); - -#endif diff --git a/bsps/sparc64/include/boot/ofw.h b/bsps/sparc64/include/boot/ofw.h deleted file mode 100644 index c562b675a2..0000000000 --- a/bsps/sparc64/include/boot/ofw.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2005 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef BOOT_OFW_H_ -#define BOOT_OFW_H_ - -#include -#include - -#define MEMMAP_MAX_RECORDS 32 -#define MAX_OFW_ARGS 12 - -#define OFW_TREE_PATH_MAX_LEN 256 -#define OFW_TREE_PROPERTY_MAX_NAMELEN 32 -#define OFW_TREE_PROPERTY_MAX_VALUELEN 64 - -typedef unative_t ofw_arg_t; -typedef unsigned int ihandle; -typedef unsigned int phandle; - -/** OpenFirmware command structure - * - */ -typedef struct { - ofw_arg_t service; /**< Command name. */ - ofw_arg_t nargs; /**< Number of in arguments. */ - ofw_arg_t nret; /**< Number of out arguments. */ - ofw_arg_t args[MAX_OFW_ARGS]; /**< List of arguments. */ -} ofw_args_t; - -typedef struct { - void *start; - uint32_t size; -} memzone_t; - -typedef struct { - uint32_t total; - uint32_t count; - memzone_t zones[MEMMAP_MAX_RECORDS]; -} memmap_t; - -typedef struct { - uint32_t info; - uint32_t addr_hi; - uint32_t addr_lo; -} pci_addr_t; - -typedef struct { - pci_addr_t addr; - uint32_t size_hi; - uint32_t size_lo; -} pci_reg_t; - -extern uintptr_t ofw_cif; - -extern phandle ofw_chosen; -extern ihandle ofw_stdout; -extern phandle ofw_root; -extern ihandle ofw_mmu; -extern phandle ofw_memory; - -extern void ofw_init(void); - -extern void ofw_write(const char *str, const int len); - -extern int ofw_get_property(const phandle device, const char *name, void *buf, const int buflen); -extern int ofw_get_proplen(const phandle device, const char *name); -extern int ofw_next_property(const phandle device, char *previous, char *buf); - -extern phandle ofw_get_child_node(const phandle node); -extern phandle ofw_get_peer_node(const phandle node); -extern phandle ofw_find_device(const char *name); - -extern int ofw_package_to_path(const phandle device, char *buf, const int buflen); - -extern int ofw(ofw_args_t *arg); -extern unsigned long ofw_call(const char *service, const int nargs, const int nret, ofw_arg_t *rets, ...); -extern void ofw_write(const char *str, const int len); -extern void ofw_read(void *str, const int len); -extern unsigned int ofw_get_address_cells(const phandle device); -extern unsigned int ofw_get_size_cells(const phandle device); -extern void *ofw_translate(const void *virt); -extern int ofw_translate_failed(ofw_arg_t flag); -extern void *ofw_claim_virt(const void *virt, const unsigned int len); -extern void *ofw_claim_phys(const void *virt, const unsigned int len); -extern void *ofw_claim_phys_any(const unsigned int len, const unsigned int alignment); -extern int ofw_map(const void *phys, const void *virt, const unsigned int size, const int mode); -extern int ofw_memmap(memmap_t *map); -extern void ofw_setup_screens(void); -extern void ofw_quiesce(void); - -#endif diff --git a/bsps/sparc64/include/boot/ofw_tree.h b/bsps/sparc64/include/boot/ofw_tree.h deleted file mode 100644 index 5872ade261..0000000000 --- a/bsps/sparc64/include/boot/ofw_tree.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef BOOT_OFW_TREE_H_ -#define BOOT_OFW_TREE_H_ - -#include -#include - - -/** Memory representation of OpenFirmware device tree node property. */ -typedef struct { - char name[OFW_TREE_PROPERTY_MAX_NAMELEN]; - size_t size; - void *value; -} ofw_tree_property_t; - -/** Memory representation of OpenFirmware device tree node. */ -typedef struct ofw_tree_node { - struct ofw_tree_node *parent; - struct ofw_tree_node *peer; - struct ofw_tree_node *child; - - uint32_t node_handle; /**< Old OpenFirmware node handle. */ - - char *da_name; /**< Disambigued name. */ - - unsigned int properties; /**< Number of properties. */ - ofw_tree_property_t *property; - - void *device; /**< Member used solely by the kernel. */ -} ofw_tree_node_t; - -extern ofw_tree_node_t *ofw_tree_build(void); - -#endif diff --git a/bsps/sparc64/include/boot/ofwarch.h b/bsps/sparc64/include/boot/ofwarch.h deleted file mode 100644 index 2d4f7643c0..0000000000 --- a/bsps/sparc64/include/boot/ofwarch.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef BOOT_sparc64_OFWARCH_H_ -#define BOOT_sparc64_OFWARCH_H_ - -#include "main.h" -#include "types.h" - -#define OFW_ADDRESS_CELLS 2 -#define OFW_SIZE_CELLS 2 - -extern int ofw_cpu(uint16_t mid_mask, uintptr_t physmem_start); -extern int ofw_get_physmem_start(uintptr_t *start); - -#endif diff --git a/bsps/sparc64/include/boot/register.h b/bsps/sparc64/include/boot/register.h deleted file mode 100644 index 61bf34ac66..0000000000 --- a/bsps/sparc64/include/boot/register.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef BOOT_sparc64_REGISTER_H_ -#define BOOT_sparc64_REGISTER_H_ - -#define PSTATE_IE_BIT 2 -#define PSTATE_PRIV_BIT 4 -#define PSTATE_AM_BIT 8 - -#define ASI_ICBUS_CONFIG 0x4a -#define ICBUS_CONFIG_MID_SHIFT 17 - -#endif diff --git a/bsps/sparc64/include/boot/types.h b/bsps/sparc64/include/boot/types.h deleted file mode 100644 index 095e25233d..0000000000 --- a/bsps/sparc64/include/boot/types.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2006 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef BOOT_sparc64_TYPES_H_ -#define BOOT_sparc64_TYPES_H_ - -#include - -typedef signed char int8_t; - -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; -typedef unsigned long uint64_t; - -typedef uint64_t uintptr_t; -typedef uint64_t unative_t; - -#endif diff --git a/bsps/sparc64/include/genarch/ofw/ofw_tree.h b/bsps/sparc64/include/genarch/ofw/ofw_tree.h deleted file mode 100644 index f62d545527..0000000000 --- a/bsps/sparc64/include/genarch/ofw/ofw_tree.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef KERN_OFW_TREE_H_ -#define KERN_OFW_TREE_H_ - -#include -#include - -#define OFW_TREE_PROPERTY_MAX_NAMELEN 32 - -/** Memory representation of OpenFirmware device tree node property. */ -typedef struct { - char name[OFW_TREE_PROPERTY_MAX_NAMELEN]; - size_t size; - void *value; -} ofw_tree_property_t; - -/** Memory representation of OpenFirmware device tree node. */ -typedef struct ofw_tree_node { - struct ofw_tree_node *parent; - struct ofw_tree_node *peer; - struct ofw_tree_node *child; - - uint32_t node_handle; /**< Old OpenFirmware node handle. */ - - char *da_name; /**< Disambigued name. */ - - unsigned int properties; /**< Number of properties. */ - ofw_tree_property_t *property; - - /** - * Pointer to a structure representing respective device. - * Its semantics is device dependent. - */ - void *device; -} ofw_tree_node_t; - -/* Walker for visiting OpenFirmware device tree nodes. */ -typedef bool (* ofw_tree_walker_t)(ofw_tree_node_t *, void *); - -extern void ofw_tree_init(ofw_tree_node_t *); -extern void ofw_tree_print(void); - -extern const char *ofw_tree_node_name(const ofw_tree_node_t *); -extern ofw_tree_node_t *ofw_tree_lookup(const char *); -extern ofw_tree_property_t *ofw_tree_getprop(const ofw_tree_node_t *, - const char *); -extern void ofw_tree_walk_by_device_type(const char *, ofw_tree_walker_t, - void *); - -extern ofw_tree_node_t *ofw_tree_find_child(ofw_tree_node_t *, const char *); -extern ofw_tree_node_t *ofw_tree_find_child_by_device_type(ofw_tree_node_t *, - const char *); - -extern ofw_tree_node_t *ofw_tree_find_peer_by_device_type(ofw_tree_node_t *, - const char *); -extern ofw_tree_node_t *ofw_tree_find_peer_by_name(ofw_tree_node_t *, - const char *); -extern ofw_tree_node_t *ofw_tree_find_node_by_handle(ofw_tree_node_t *, - uint32_t); - -#endif diff --git a/bsps/sparc64/include/kernel/align.h b/bsps/sparc64/include/kernel/align.h deleted file mode 100644 index e9b33ca222..0000000000 --- a/bsps/sparc64/include/kernel/align.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup RTEMSBSPsSPARC64Generic - * @ingroup others - * @{ - */ -/** - * @file - * @brief Macros for making values and addresses aligned. - */ - -#ifndef KERN_ALIGN_H_ -#define KERN_ALIGN_H_ - -/** Align to the nearest lower address. - * - * @param s Address or size to be aligned. - * @param a Size of alignment, must be power of 2. - */ -#define ALIGN_DOWN(s, a) ((s) & ~((a) - 1)) - - -/** Align to the nearest higher address. - * - * @param s Address or size to be aligned. - * @param a Size of alignment, must be power of 2. - */ -#define ALIGN_UP(s, a) (((s) + ((a) - 1)) & ~((a) - 1)) - -#endif - -/** @} - */ diff --git a/bsps/sparc64/include/traptable.h b/bsps/sparc64/include/traptable.h deleted file mode 100644 index c77fdd0b7b..0000000000 --- a/bsps/sparc64/include/traptable.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * traptable.h - * - * Copyright 2010 Gedare Bloom - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* This file can be included by assembly code */ - -#define ENTRY_SIZE (32) - -#define TABLE_SIZE (1024*ENTRY_SIZE) - -#ifndef ASM -extern void* real_trap_table; -extern void* trap_table[TABLE_SIZE]; -#endif - diff --git a/bsps/sparc64/niagara/README.md b/bsps/sparc64/niagara/README.md deleted file mode 100644 index b3a8fcdde3..0000000000 --- a/bsps/sparc64/niagara/README.md +++ /dev/null @@ -1,74 +0,0 @@ -niagara -======= -``` -BSP NAME: niagara -BOARD: -BUS: n/a -CPU FAMILY: SPARC V9 with UltraSPARC Architecture 2005 (a.k.a. sun4v) -CPU: UltraSPARC T1 (OpenSPARC T1) -COPROCESSORS: -MODE: n/a - -DEBUG MONITOR: -``` - -PERIPHERALS ------------ -``` -TIMERS: TICK and STICK registers (ASRs 4 and 24) - RESOLUTION: CPU clock resolution -SERIAL PORTS: -REAL-TIME CLOCK: -DMA: none -VIDEO: none -SCSI: none -NETWORKING: none -``` - -DRIVER INFORMATION ------------------- -``` -CLOCK DRIVER: -IOSUPP DRIVER: -SHMSUPP: -TIMER DRIVER: -TTY DRIVER: -``` - -STDIO ------ -``` -PORT: -ELECTRICAL: -BAUD: -BITS PER CHARACTER: -PARITY: -STOP BITS: -``` - - -Board description ------------------ -``` -clock rate: -bus width: -ROM: -RAM: -``` - -This BSP is designed to operate on the UltraSPARC T1 (Niagara) SPARC64 -and similar processors. - -This BSP has been run on the Simics simulator with the niagara target, which -simulates the OpenSPARC T1 Niagara implementation. - -This BSP has been run on the M5 simulator with the SPARC_FS target, which -simulates the OpenSPARC T1 Niagara implementation. - -Simics: -A commercially available simulator licensed by Virtutech. -https://www.simics.net/ - -M5: -An open-source simulator. -http://www.m5sim.org/wiki/index.php/Main_Page diff --git a/bsps/sparc64/niagara/config/niagara.cfg b/bsps/sparc64/niagara/config/niagara.cfg deleted file mode 100644 index bfa73aa686..0000000000 --- a/bsps/sparc64/niagara/config/niagara.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# -# Config file for the Niagara SPARC64 processor. -# -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=sparc64 - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = -mcpu=niagara - -# optimize flag: typically -g -O2 -CFLAGS_OPTIMIZE_V = -g -O2 -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/sparc64/niagara/include/bsp.h b/bsps/sparc64/niagara/include/bsp.h deleted file mode 100644 index 1dee8a835b..0000000000 --- a/bsps/sparc64/niagara/include/bsp.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @ingroup RTEMSBSPsSPARC64Niagara - * - * @brief Global BSP definitions. - */ - -/* bsp.h - * - * This include file contains all SPARC64 simulator definitions. - * - * COPYRIGHT (c) 1989-1998. On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef LIBBSP_SPARC64_NIAGARA_BSP_H -#define LIBBSP_SPARC64_NIAGARA_BSP_H - -/** - * @defgroup RTEMSBSPsSPARC64Niagara Niagara - * - * @ingroup RTEMSBSPsSPARC64 - * - * @brief Niagara - * - * @{ - */ - -#include -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* support for simulated clock tick */ -/* -void *clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body -*/ - -/* this should be defined somewhere */ -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif diff --git a/bsps/sparc64/niagara/include/bsp/irq.h b/bsps/sparc64/niagara/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/sparc64/niagara/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sparc64/niagara/include/tm27.h b/bsps/sparc64/niagara/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/bsps/sparc64/niagara/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sparc64/niagara/start/bspclean.c b/bsps/sparc64/niagara/start/bspclean.c deleted file mode 100644 index 6bff13e5c9..0000000000 --- a/bsps/sparc64/niagara/start/bspclean.c +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Copyright (c) 2014 Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include "m5op.h" - -void bsp_reset( rtems_fatal_source source, rtems_fatal_code code ) -{ - (void) source; - (void) code; - - m5_exit(0); - RTEMS_UNREACHABLE(); -} diff --git a/bsps/sparc64/niagara/start/bspinit.S b/bsps/sparc64/niagara/start/bspinit.S deleted file mode 100644 index 65f235c409..0000000000 --- a/bsps/sparc64/niagara/start/bspinit.S +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * bspinit.S - * - * COPYRIGHT (c) 2010 Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * - * BSP specific initialization for Sparc64 RTEMS -- sun4v BSP - * - * This code defines start code specific to the sun4v BSP - */ - -#include -#include - -#define STACK_WINDOW_SAVE_AREA_SIZE (16*8) - -.section .text - -PUBLIC(_BSP_init) - .global _BSP_init - SYM(_BSP_init): - - save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp - - - - ret - restore - diff --git a/bsps/sparc64/niagara/start/m5op.h b/bsps/sparc64/niagara/start/m5op.h deleted file mode 100644 index d349e4d6bc..0000000000 --- a/bsps/sparc64/niagara/start/m5op.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2003-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Ali Saidi - */ - -#ifndef __M5OP_H__ -#define __M5OP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -void arm(uint64_t address); -void quiesce(void); -void quiesceNs(uint64_t ns); -void quiesceCycle(uint64_t cycles); -uint64_t quiesceTime(void); -uint64_t rpns(void); -void wakeCPU(uint64_t cpuid); - -void m5_exit(uint64_t ns_delay); -void m5_fail(uint64_t ns_delay, uint64_t code); -uint64_t m5_initparam(void); -void m5_checkpoint(uint64_t ns_delay, uint64_t ns_period); -void m5_reset_stats(uint64_t ns_delay, uint64_t ns_period); -void m5_dump_stats(uint64_t ns_delay, uint64_t ns_period); -void m5_dumpreset_stats(uint64_t ns_delay, uint64_t ns_period); -uint64_t m5_readfile(void *buffer, uint64_t len, uint64_t offset); -uint64_t m5_writefile(void *buffer, uint64_t len, uint64_t offset, const char *filename); -void m5_debugbreak(void); -void m5_switchcpu(void); -void m5_addsymbol(uint64_t addr, char *symbol); -void m5_panic(void); -void m5_work_begin(uint64_t workid, uint64_t threadid); -void m5_work_end(uint64_t workid, uint64_t threadid); - -// These operations are for critical path annotation -void m5a_bsm(char *sm, const void *id, int flags); -void m5a_esm(char *sm); -void m5a_begin(int flags, char *st); -void m5a_end(void); -void m5a_q(const void *id, char *q, int count); -void m5a_dq(const void *id, char *q, int count); -void m5a_wf(const void *id, char *q, char *sm, int count); -void m5a_we(const void *id, char *q, char *sm, int count); -void m5a_ws(const void *id, char *q, char *sm); -void m5a_sq(const void *id, char *q, int count, int flags); -void m5a_aq(const void *id, char *q, int count); -void m5a_pq(const void *id, char *q, int count); -void m5a_l(char *lsm, const void *id, char *sm); -void m5a_identify(uint64_t id); -uint64_t m5a_getid(void); - -#define M5_AN_FL_NONE 0x0 -#define M5_AN_FL_BAD 0x2 -#define M5_AN_FL_LINK 0x10 -#define M5_AN_FL_RESET 0x20 - -#ifdef __cplusplus -} -#endif -#endif // __M5OP_H__ diff --git a/bsps/sparc64/niagara/start/m5op_sparc.S b/bsps/sparc64/niagara/start/m5op_sparc.S deleted file mode 100644 index 40248ff8bf..0000000000 --- a/bsps/sparc64/niagara/start/m5op_sparc.S +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2003-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Ali Saidi - */ - -#define m5_op 0x2 -#define m5_op3 0x37 - -#include "m5ops.h" - -#define INST(func, rs1, rs2, rd) \ - .long (m5_op) << 30 | (rd) << 25 | (m5_op3) << 19 | (func) << 7 | \ - (rs1) << 14 | (rs2) << 0; - - -#define LEAF(func) \ - .section ".text"; \ - .align 4; \ - .global func; \ - .type func, #function; \ -func: - -#define END(func) \ - .size func, (.-func) - -#define DEBUGBREAK INST(debugbreak_func, 0, 0, 0) -#define M5EXIT INST(exit_func, 0, 0, 0) -#define PANIC INST(panic_func, 0, 0, 0) -#define READFILE INST(readfile_func, 0, 0, 0) - -LEAF(m5_exit) - retl - M5EXIT -END(m5_exit) - -LEAF(m5_panic) - retl - PANIC -END(m5_panic) - -LEAF(m5_readfile) - retl - READFILE -END(m5_readfile) - -LEAF(m5_debugbreak) - retl - DEBUGBREAK -END(m5_debugbreak) - -/* !!!!!! All code below here just panics !!!!!! */ -LEAF(arm) - retl - PANIC -END(arm) - -LEAF(quiesce) - retl - PANIC -END(quiesce) - -LEAF(quiesceNs) - retl - PANIC -END(quiesceNs) - -LEAF(quiesceCycle) - retl - PANIC -END(quiesceCycle) - -LEAF(quiesceTime) - retl - PANIC -END(quiesceTime) - -LEAF(m5_initparam) - retl - PANIC -END(m5_initparam) - -LEAF(m5_loadsymbol) - retl - PANIC -END(m5_loadsymbol) - -LEAF(m5_reset_stats) - retl - PANIC -END(m5_reset_stats) - -LEAF(m5_dump_stats) - retl - PANIC -END(m5_dump_stats) - -LEAF(m5_dumpreset_stats) - retl - PANIC -END(m5_dumpreset_stats) - -LEAF(m5_checkpoint) - retl - PANIC -END(m5_checkpoint) - -LEAF(m5_switchcpu) - retl - PANIC -END(m5_switchcpu) - -LEAF(m5_addsymbol) - retl - PANIC -END(m5_addsymbol) - -LEAF(m5_anbegin) - retl - PANIC -END(m5_anbegin) - -LEAF(m5_anwait) - retl - PANIC -END(m5_anwait) - - diff --git a/bsps/sparc64/niagara/start/m5ops.h b/bsps/sparc64/niagara/start/m5ops.h deleted file mode 100644 index 8ff1ac42f1..0000000000 --- a/bsps/sparc64/niagara/start/m5ops.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2003-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Ali Saidi - */ - -#define arm_func 0x00 -#define quiesce_func 0x01 -#define quiescens_func 0x02 -#define quiescecycle_func 0x03 -#define quiescetime_func 0x04 -#define rpns_func 0x07 -#define wakecpu_func 0x09 -#define deprecated1_func 0x10 // obsolete ivlb -#define deprecated2_func 0x11 // obsolete ivle -#define deprecated3_func 0x20 // deprecated exit function -#define exit_func 0x21 -#define fail_func 0x22 -#define initparam_func 0x30 -#define loadsymbol_func 0x31 -#define resetstats_func 0x40 -#define dumpstats_func 0x41 -#define dumprststats_func 0x42 -#define ckpt_func 0x43 -#define writefile_func 0x4F -#define readfile_func 0x50 -#define debugbreak_func 0x51 -#define switchcpu_func 0x52 -#define addsymbol_func 0x53 -#define panic_func 0x54 - -#define reserved2_func 0x56 // Reserved for user -#define reserved3_func 0x57 // Reserved for user -#define reserved4_func 0x58 // Reserved for user -#define reserved5_func 0x59 // Reserved for user - -#define work_begin_func 0x5a -#define work_end_func 0x5b - -// These operations are for critical path annotation -#define annotate_func 0x55 -#define an_bsm 0x1 -#define an_esm 0x2 -#define an_begin 0x3 -#define an_end 0x4 -#define an_q 0x6 -#define an_dq 0x7 -#define an_wf 0x8 -#define an_we 0x9 -#define an_rq 0xA -#define an_ws 0xB -#define an_sq 0xC -#define an_aq 0xD -#define an_pq 0xE -#define an_l 0xF -#define an_identify 0x10 -#define an_getid 0x11 - diff --git a/bsps/sparc64/shared/clock/ckinit.c b/bsps/sparc64/shared/clock/ckinit.c deleted file mode 100644 index 82ac3b1995..0000000000 --- a/bsps/sparc64/shared/clock/ckinit.c +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* ckinit.c - * - * This file provides a template for the clock device driver initialization. - * - * Modified for sun4v - niagara - */ - -/* - * Copyright (c) 2010 Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include - -/* This is default frequency for simics simulator of niagara. Use the - * get_Frequency function to determine the CPU clock frequency at runtime. - */ -#define CPU_FREQ (5000000) - -uint64_t sparc64_cycles_per_tick; - -/* TICK_CMPR and STICK_CMPR trigger soft interrupt 14 */ -#define CLOCK_VECTOR SPARC_SYNCHRONOUS_TRAP(0x4E) - -static unsigned int get_Frequency(void) -{ - phandle root = ofw_find_device("/"); - unsigned int freq; - - if (ofw_get_property(root, "clock-frequency", &freq, sizeof(freq)) <= 0) { - printk("Unable to determine frequency, default: 0x%x\n",CPU_FREQ); - return CPU_FREQ; - } - - return freq; -} - -#define Clock_driver_support_at_tick(arg) \ - Clock_driver_support_at_tick_helper() - -static void Clock_driver_support_at_tick_helper(void) -{ - uint64_t tick_reg; - int bit_mask; - uint64_t pil_reg; - - bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14); - sparc64_clear_interrupt_bits(bit_mask); - - sparc64_get_pil(pil_reg); - if(pil_reg == 0xe) { /* 0xe is the tick compare interrupt (softint(14)) */ - pil_reg--; - sparc64_set_pil(pil_reg); /* enable the next timer interrupt */ - } - /* Note: sun4v uses stick_cmpr for clock driver for M5 simulator, which - * does not currently have tick_cmpr implemented */ - /* TODO: this could be more efficiently implemented as a single assembly - * inline */ -#if defined (SUN4U) - sparc64_read_tick(tick_reg); -#elif defined (SUN4V) - sparc64_read_stick(tick_reg); -#endif - tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */ - - tick_reg += sparc64_cycles_per_tick; - -#if defined (SUN4U) - sparc64_write_tick_cmpr(tick_reg); -#elif defined (SUN4V) - sparc64_write_stick_cmpr(tick_reg); -#endif -} - -#define Clock_driver_support_install_isr(_new) \ - set_vector( _new, CLOCK_VECTOR, 1 ) - -static void Clock_driver_support_initialize_hardware(void) -{ - uint64_t tick_reg; - int bit_mask; - - bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14); - sparc64_clear_interrupt_bits(bit_mask); - - sparc64_cycles_per_tick = - rtems_configuration_get_microseconds_per_tick()*(get_Frequency()/1000000); - -#if defined (SUN4U) - sparc64_read_tick(tick_reg); -#elif defined (SUN4V) - sparc64_read_stick(tick_reg); -#endif - - tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */ - tick_reg += sparc64_cycles_per_tick; - -#if defined (SUN4U) - sparc64_write_tick_cmpr(tick_reg); -#elif defined (SUN4V) - sparc64_write_stick_cmpr(tick_reg); -#endif -} - -#define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER - -#include "../../../shared/dev/clock/clockimpl.h" - diff --git a/bsps/sparc64/shared/console/conscfg.c b/bsps/sparc64/shared/console/conscfg.c deleted file mode 100644 index 560bdc05bf..0000000000 --- a/bsps/sparc64/shared/console/conscfg.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * COPYRIGHT (c) 2010 Eugen Leontie. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include - -#include - -#include - -#include - -static int sun4v_console_device_first_open(int major, int minor, void *arg) -{ - return 0; -} - -static ssize_t sun4v_console_poll_write(int minor, const char *buf, size_t n) -{ - ofw_write(buf, n); - return 0; -} - -static void sun4v_console_deviceInitialize (int minor) -{ - -} - -static int sun4v_console_poll_read(int minor){ - int a; - ofw_read(&a,1); - if ( a != 0 ) { - return a>>24; - } - return -1; -} - -static bool sun4v_console_deviceProbe (int minor){ - return true; -} - -/* - * Polled mode functions - */ -const console_fns pooled_functions={ - sun4v_console_deviceProbe, /* deviceProbe */ - sun4v_console_device_first_open, /* deviceFirstOpen */ - NULL, /* deviceLastClose */ - sun4v_console_poll_read, /* deviceRead */ - sun4v_console_poll_write, /* deviceWrite */ - sun4v_console_deviceInitialize, /* deviceInitialize */ - NULL, /* deviceWritePolled */ - NULL, /* deviceSetAttributes */ - NULL /* deviceOutputUsesInterrupts */ -}; - -const console_flow sun4v_console_console_flow = { - NULL, /* deviceStopRemoteTx */ - NULL /* deviceStartRemoteTx */ -}; - -console_tbl Console_Configuration_Ports[] = { - { - "/dev/ttyS0", /* sDeviceName */ - SERIAL_CUSTOM, /* deviceType */ - &pooled_functions, /* pDeviceFns */ - NULL, /* deviceProbe, assume it is there */ - &sun4v_console_console_flow, /* pDeviceFlow */ - 0, /* ulMargin */ - 0, /* ulHysteresis */ - (void *) NULL, /* pDeviceParams */ - 0, /* ulCtrlPort1 */ - 0, /* ulCtrlPort2 */ - 1, /* ulDataPort */ - NULL, /* getRegister */ - NULL, /* setRegister */ - NULL, /* unused */ /* getData */ - NULL, /* unused */ /* setData */ - 0, /* ulClock */ - 0 /* ulIntVector -- base for port */ - }, -}; - -/* - * Declare some information used by the console driver - */ - -#define NUM_CONSOLE_PORTS 1 - -unsigned long Console_Configuration_Count = NUM_CONSOLE_PORTS; - -/* putchar/getchar for printk */ - -static void bsp_out_char (char c) -{ - ofw_write(&c, 1); -} - -BSP_output_char_function_type BSP_output_char = bsp_out_char; - -static int bsp_in_char( void ){ - int tmp; - ofw_read( &tmp, 1 ); /* blocks */ - if( tmp != 0 ) { - return tmp>>24; - } - return -1; -} - -BSP_polling_getchar_function_type BSP_poll_char = bsp_in_char; - diff --git a/bsps/sparc64/shared/doxygen.h b/bsps/sparc64/shared/doxygen.h deleted file mode 100644 index 33fa0b3fe8..0000000000 --- a/bsps/sparc64/shared/doxygen.h +++ /dev/null @@ -1,15 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSImplDoxygen - * - * @brief This header file defines sparc64-specific groups. - */ - -/** - * @defgroup RTEMSBSPsSPARC64 SPARC64 - * - * @ingroup RTEMSBSPs - * - * @brief SPARC64 Board Support Packages. - */ diff --git a/bsps/sparc64/shared/helenos/LICENSE.md b/bsps/sparc64/shared/helenos/LICENSE.md deleted file mode 100644 index 3f5c785e26..0000000000 --- a/bsps/sparc64/shared/helenos/LICENSE.md +++ /dev/null @@ -1,13 +0,0 @@ -License -======= - -Copyright (C) 2001-2009 HelenOS project -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsps/sparc64/shared/helenos/README.md b/bsps/sparc64/shared/helenos/README.md deleted file mode 100644 index b80f68bcc4..0000000000 --- a/bsps/sparc64/shared/helenos/README.md +++ /dev/null @@ -1,52 +0,0 @@ -HelenOS -======= - -The sources in this directory are from the HelenOS project. -See: http://www.helenos.org - -These sources are from release 0.4.2 -See: http://www.helenos.org/releases/HelenOS-0.4.2.tar.bz2 - -Unless otherwise indicated, these files are licensed under a BSD-like -license without advertising clause. -See: http://www.helenos.org/license -Or the file LICENSE in this directory. - -Source modifications are mostly documented in the individual source code files. -Source that is removed is discarded by #ifdef 0 ... #endif blocks. - -The subdirectories here correspond to the following subdirectories in the -HelenOS source tree (as of release 0.4.2): - -boot -HelenOS-0.4.2/boot -Various subdirectories related to booting the sparc64 - -boot/genarch -HelenOS-0.4.2/boot/genarch - -boot/generic -HelenOS-0.4.2/boot/generic - -boot/include -Various .h files from the following directories: - HelenOS-0.4.2/boot/genarch - HelenOS-0.4.2/boot/generic - HelenOS-0.4.2/boot/arch/sparc64/loader - -boot/sparc64 -HelenOS-0.4.2/boot/arch/sparc64 - -kernel -HelenOS-0.4.2/kernel -Various subdirectories related to kernel code and services for the sparc64 - -kernel/genarch -HelenOS-0.4.2/kernel/genarch - -kernel/generic -HelenOS-0.4.2/kernel/generic - -kernel/sparc64 -HelenOS-0.4.2/kernel/arch/sparc64/ - diff --git a/bsps/sparc64/shared/helenos/boot/genarch/balloc.c b/bsps/sparc64/shared/helenos/boot/genarch/balloc.c deleted file mode 100644 index f4cb9dc1eb..0000000000 --- a/bsps/sparc64/shared/helenos/boot/genarch/balloc.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Modifications are made to compile for RTEMS. Removes asm.h and replaces - * the necessary defines in-line - * - */ - - -#include -#if 0 -#include -#endif -#include -#include - -static ballocs_t *ballocs; -static uintptr_t phys_base; - -void balloc_init(ballocs_t *ball, uintptr_t base, uintptr_t kernel_base) -{ - ballocs = ball; - phys_base = base; - ballocs->base = kernel_base; - ballocs->size = 0; -} - -void *balloc(size_t size, size_t alignment) -{ - /* Enforce minimal alignment. */ - alignment = ALIGN_UP(alignment, 4); - - uintptr_t addr = phys_base + ALIGN_UP(ballocs->size, alignment); - - if (ALIGN_UP(ballocs->size, alignment) + size > BALLOC_MAX_SIZE) - return NULL; - - ballocs->size = ALIGN_UP(ballocs->size, alignment) + size; - - return (void *) addr; -} - -void *balloc_rebase(void *ptr) -{ - return (void *) ((uintptr_t) ptr - phys_base + ballocs->base); -} diff --git a/bsps/sparc64/shared/helenos/boot/genarch/ofw.c b/bsps/sparc64/shared/helenos/boot/genarch/ofw.c deleted file mode 100644 index 2bbc490636..0000000000 --- a/bsps/sparc64/shared/helenos/boot/genarch/ofw.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * Copyright (c) 2005 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Modifications are made to compile for RTEMS. Removes asm.h and printf.h. - * Adds asm.h (rtems bsp). Adds ofw_read() and ofw_stdin variable. Uses - * printk instead of puts for error messages. - * - */ - -#include -#include - -#include -#include -#if 0 -#include -#include -#endif -#include -#include -#include - -#define RED(i) (((i) >> 5) & ((1 << 3) - 1)) -#define GREEN(i) (((i) >> 3) & ((1 << 2) - 1)) -#define BLUE(i) ((i) & ((1 << 3) - 1)) -#define CLIP(i) ((i) <= 255 ? (i) : 255) - -uintptr_t ofw_cif; - -phandle ofw_chosen; -ihandle ofw_stdout; -ihandle ofw_stdin; - -phandle ofw_root; -ihandle ofw_mmu; -ihandle ofw_memory_prop; -phandle ofw_memory; - -void ofw_init(void) -{ - ofw_chosen = ofw_find_device("/chosen"); - if (ofw_chosen == -1) - halt(); - - if (ofw_get_property(ofw_chosen, "stdout", &ofw_stdout, - sizeof(ofw_stdout)) <= 0) - ofw_stdout = 0; - - if (ofw_get_property(ofw_chosen, "stdin", &ofw_stdin, - sizeof(ofw_stdin)) <= 0) - ofw_stdin = 0; - - ofw_root = ofw_find_device("/"); - if (ofw_root == -1) { - printk("\r\nError: Unable to find / device, halted.\r\n"); - halt(); - } - - if (ofw_get_property(ofw_chosen, "mmu", &ofw_mmu, - sizeof(ofw_mmu)) <= 0) { - printk("\r\nError: Unable to get mmu property, halted.\r\n"); - halt(); - } - if (ofw_get_property(ofw_chosen, "memory", &ofw_memory_prop, - sizeof(ofw_memory_prop)) <= 0) { - printk("\r\nError: Unable to get memory property, halted.\r\n"); - halt(); - } - - ofw_memory = ofw_find_device("/memory"); - if (ofw_memory == -1) { - printk("\r\nError: Unable to find /memory device, halted.\r\n"); - halt(); - } -} - -/** Perform a call to OpenFirmware client interface. - * - * @param service String identifying the service requested. - * @param nargs Number of input arguments. - * @param nret Number of output arguments. This includes the return - * value. - * @param rets Buffer for output arguments or NULL. The buffer must - * accommodate nret - 1 items. - * - * @return Return value returned by the client interface. - * - */ -unsigned long -ofw_call(const char *service, const int nargs, const int nret, ofw_arg_t *rets, - ...) -{ - va_list list; - ofw_args_t args; - int i; - - args.service = (ofw_arg_t) service; - args.nargs = nargs; - args.nret = nret; - - va_start(list, rets); - for (i = 0; i < nargs; i++) - args.args[i] = va_arg(list, ofw_arg_t); - va_end(list); - - for (i = 0; i < nret; i++) - args.args[i + nargs] = 0; - - (void) ofw(&args); - - for (i = 1; i < nret; i++) - rets[i - 1] = args.args[i + nargs]; - - return args.args[nargs]; -} - -phandle ofw_find_device(const char *name) -{ - return ofw_call("finddevice", 1, 1, NULL, name); -} - -int ofw_get_property(const phandle device, const char *name, void *buf, - const int buflen) -{ - return ofw_call("getprop", 4, 1, NULL, device, name, buf, buflen); -} - -int ofw_get_proplen(const phandle device, const char *name) -{ - return ofw_call("getproplen", 2, 1, NULL, device, name); -} - -int ofw_next_property(const phandle device, char *previous, char *buf) -{ - return ofw_call("nextprop", 3, 1, NULL, device, previous, buf); -} - -int ofw_package_to_path(const phandle device, char *buf, const int buflen) -{ - return ofw_call("package-to-path", 3, 1, NULL, device, buf, buflen); -} - -unsigned int ofw_get_address_cells(const phandle device) -{ - unsigned int ret = 1; - - if (ofw_get_property(device, "#address-cells", &ret, sizeof(ret)) <= 0) - if (ofw_get_property(ofw_root, "#address-cells", &ret, - sizeof(ret)) <= 0) - ret = OFW_ADDRESS_CELLS; - - return ret; -} - -unsigned int ofw_get_size_cells(const phandle device) -{ - unsigned int ret; - - if (ofw_get_property(device, "#size-cells", &ret, sizeof(ret)) <= 0) - if (ofw_get_property(ofw_root, "#size-cells", &ret, - sizeof(ret)) <= 0) - ret = OFW_SIZE_CELLS; - - return ret; -} - -phandle ofw_get_child_node(const phandle node) -{ - return ofw_call("child", 1, 1, NULL, node); -} - -phandle ofw_get_peer_node(const phandle node) -{ - return ofw_call("peer", 1, 1, NULL, node); -} - -static ihandle ofw_open(const char *name) -{ - return ofw_call("open", 1, 1, NULL, name); -} - - -void ofw_write(const char *str, const int len) -{ - if (ofw_stdout == 0) - return; - - ofw_call("write", 3, 1, NULL, ofw_stdout, str, len); -} - -void ofw_read(void *str, const int len) -{ - if (ofw_stdin == 0) - return; - - ofw_call("read", 3, 1, NULL, ofw_stdin, str, len); -} - -void *ofw_translate(const void *virt) -{ - ofw_arg_t result[4]; - int shift; - - if (ofw_call("call-method", 4, 5, result, "translate", ofw_mmu, - virt, 0) != 0) { - printk("Error: MMU method translate() failed, halting.\n"); - halt(); - } - - if (ofw_translate_failed(result[0])) - return NULL; - - if (sizeof(unative_t) == 8) - shift = 32; - else - shift = 0; - - return (void *) ((result[2] << shift) | result[3]); -} - -void *ofw_claim_virt(const void *virt, const unsigned int len) -{ - ofw_arg_t retaddr; - - if (ofw_call("call-method", 5, 2, &retaddr, "claim", ofw_mmu, 0, len, - virt) != 0) { - printk("Error: MMU method claim() failed, halting.\n"); - halt(); - } - - return (void *) retaddr; -} - -static void *ofw_claim_phys_internal(const void *phys, const unsigned int len, const unsigned int alignment) -{ - /* - * Note that the return value check will help - * us to discover conflicts between OpenFirmware - * allocations and our use of physical memory. - * It is better to detect collisions here - * than to cope with weird errors later. - * - * So this is really not to make the loader - * more generic; it is here for debugging - * purposes. - */ - - if (sizeof(unative_t) == 8) { - ofw_arg_t retaddr[2]; - int shift = 32; - - if (ofw_call("call-method", 6, 3, retaddr, "claim", - ofw_memory_prop, alignment, len, ((uintptr_t) phys) >> shift, - ((uintptr_t) phys) & ((uint32_t) -1)) != 0) { - printk("Error: memory method claim() failed, halting.\n"); - halt(); - } - - return (void *) ((retaddr[0] << shift) | retaddr[1]); - } else { - ofw_arg_t retaddr[1]; - - if (ofw_call("call-method", 5, 2, retaddr, "claim", - ofw_memory_prop, alignment, len, (uintptr_t) phys) != 0) { - printk("Error: memory method claim() failed, halting.\n"); - halt(); - } - - return (void *) retaddr[0]; - } -} - -void *ofw_claim_phys(const void *phys, const unsigned int len) -{ - return ofw_claim_phys_internal(phys, len, 0); -} - -void *ofw_claim_phys_any(const unsigned int len, const unsigned int alignment) -{ - return ofw_claim_phys_internal(NULL, len, alignment); -} - -int ofw_map(const void *phys, const void *virt, const unsigned int size, const int mode) -{ - uintptr_t phys_hi, phys_lo; - - if (sizeof(unative_t) == 8) { - int shift = 32; - phys_hi = (uintptr_t) phys >> shift; - phys_lo = (uintptr_t) phys & 0xffffffff; - } else { - phys_hi = 0; - phys_lo = (uintptr_t) phys; - } - - return ofw_call("call-method", 7, 1, NULL, "map", ofw_mmu, mode, size, - virt, phys_hi, phys_lo); -} - -/** Save OpenFirmware physical memory map. - * - * @param map Memory map structure where the map will be saved. - * - * @return Zero on failure, non-zero on success. - */ -int ofw_memmap(memmap_t *map) -{ - unsigned int ac = ofw_get_address_cells(ofw_memory) / - (sizeof(uintptr_t) / sizeof(uint32_t)); - unsigned int sc = ofw_get_size_cells(ofw_memory) / - (sizeof(uintptr_t) / sizeof(uint32_t)); - - uintptr_t buf[((ac + sc) * MEMMAP_MAX_RECORDS)]; - int ret = ofw_get_property(ofw_memory, "reg", buf, sizeof(buf)); - if (ret <= 0) /* ret is the number of written bytes */ - return false; - - int pos; - map->total = 0; - map->count = 0; - for (pos = 0; (pos < ret / sizeof(uintptr_t)) && - (map->count < MEMMAP_MAX_RECORDS); pos += ac + sc) { - void *start = (void *) (buf[pos + ac - 1]); - unsigned int size = buf[pos + ac + sc - 1]; - - /* - * This is a hot fix of the issue which occurs on machines - * where there are holes in the physical memory (such as - * SunBlade 1500). Should we detect a hole in the physical - * memory, we will ignore any memory detected behind - * the hole and pretend the hole does not exist. - */ - if ((map->count > 0) && (map->zones[map->count - 1].start + - map->zones[map->count - 1].size < start)) - break; - - if (size > 0) { - map->zones[map->count].start = start; - map->zones[map->count].size = size; - map->count++; - map->total += size; - } - } - - return true; -} - -static void ofw_setup_screen(phandle handle) -{ - /* Check for device type */ - char device_type[OFW_TREE_PROPERTY_MAX_VALUELEN]; - if (ofw_get_property(handle, "device_type", device_type, OFW_TREE_PROPERTY_MAX_VALUELEN) <= 0) - return; - - device_type[OFW_TREE_PROPERTY_MAX_VALUELEN - 1] = '\0'; - if (strcmp(device_type, "display") != 0) - return; - - /* Check for 8 bit depth */ - uint32_t depth; - if (ofw_get_property(handle, "depth", &depth, sizeof(uint32_t)) <= 0) - depth = 0; - - /* Get device path */ - static char path[OFW_TREE_PATH_MAX_LEN + 1]; - size_t len = ofw_package_to_path(handle, path, OFW_TREE_PATH_MAX_LEN); - if (len == -1) - return; - - path[len] = '\0'; - - /* Open the display to initialize it */ - ihandle screen = ofw_open(path); - if (screen == -1) - return; - - if (depth == 8) { - /* Setup the palette so that the (inverted) 3:2:3 scheme is usable */ - unsigned int i; - for (i = 0; i < 256; i++) { - ofw_call("call-method", 6, 1, NULL, "color!", screen, - 255 - i, CLIP(BLUE(i) * 37), GREEN(i) * 85, CLIP(RED(i) * 37)); - } - } -} - -static void ofw_setup_screens_internal(phandle current) -{ - while ((current != 0) && (current != -1)) { - ofw_setup_screen(current); - - /* - * Recursively process the potential child node. - */ - phandle child = ofw_get_child_node(current); - if ((child != 0) && (child != -1)) - ofw_setup_screens_internal(child); - - /* - * Iteratively process the next peer node. - * Note that recursion is a bad idea here. - * Due to the topology of the OpenFirmware device tree, - * the nesting of peer nodes could be to wide and the - * risk of overflowing the stack is too real. - */ - phandle peer = ofw_get_peer_node(current); - if ((peer != 0) && (peer != -1)) { - current = peer; - /* - * Process the peer in next iteration. - */ - continue; - } - - /* - * No more peers on this level. - */ - break; - } -} - -/** Setup all screens which can be detected. - * - * Open all screens which can be detected and set up the palette for the 8-bit - * color depth configuration so that the 3:2:3 color scheme can be used. - * Check that setting the palette makes sense (the color depth is not greater - * than 8). - * - */ -void ofw_setup_screens(void) -{ - ofw_setup_screens_internal(ofw_root); -} - -void ofw_quiesce(void) -{ - ofw_call("quiesce", 0, 0, NULL); -} diff --git a/bsps/sparc64/shared/helenos/boot/genarch/ofw_tree.c b/bsps/sparc64/shared/helenos/boot/genarch/ofw_tree.c deleted file mode 100644 index d6770c093d..0000000000 --- a/bsps/sparc64/shared/helenos/boot/genarch/ofw_tree.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Modifications are made to compile for RTEMS. Removes asm.h and memstr.h. - * - */ - - -#include -#include -#include -#include -#include -#include -#if 0 -#include -#include -#endif - -static ofw_tree_node_t *ofw_tree_node_alloc(void) -{ - return balloc(sizeof(ofw_tree_node_t), sizeof(ofw_tree_node_t)); -} - -static ofw_tree_property_t *ofw_tree_properties_alloc(unsigned count) -{ - return balloc(count * sizeof(ofw_tree_property_t), - sizeof(ofw_tree_property_t)); -} - -static void *ofw_tree_space_alloc(size_t size) -{ - /* - * What we do here is a nasty hack :-) - * Problem: string property values that are allocated via this - * function typically do not contain the trailing '\0'. This - * is very uncomfortable for kernel, which is supposed to deal - * with the properties. - * Solution: when allocating space via this function, we always - * allocate space for the extra '\0' character that we store - * behind the requested memory. - */ - char *addr = balloc(size + 1, size); - if (addr) - addr[size] = '\0'; - - return addr; -} - -/** Transfer information from one OpenFirmware node into its memory - * representation. - * - * Transfer entire information from the OpenFirmware device tree 'current' node - * to its memory representation in 'current_node'. This function recursively - * processes all node's children. Node's peers are processed iteratively in - * order to prevent stack from overflowing. - * - * @param current_node Pointer to uninitialized ofw_tree_node structure that - * will become the memory represenation of 'current'. - * @param parent_node Parent ofw_tree_node structure or NULL in case of root - * node. - * @param current OpenFirmware phandle to the current device tree node. - * - */ -static void ofw_tree_node_process(ofw_tree_node_t *current_node, - ofw_tree_node_t *parent_node, phandle current) -{ - while (current_node) { - /* - * Initialize node. - */ - current_node->parent = (ofw_tree_node_t *) balloc_rebase(parent_node); - current_node->peer = NULL; - current_node->child = NULL; - current_node->node_handle = current; - current_node->properties = 0; - current_node->property = NULL; - current_node->device = NULL; - - /* - * Get the disambigued name. - */ - static char path[OFW_TREE_PATH_MAX_LEN + 1]; - size_t len = ofw_package_to_path(current, path, OFW_TREE_PATH_MAX_LEN); - if (len == -1) - return; - - path[len] = '\0'; - - /* Find last slash */ - int i; - for (i = len - 1; (i >= 0) && (path[i] != '/'); i--); - - /* Do not include the slash */ - i++; - len -= i; - - /* Add space for trailing '\0' */ - char *da_name = ofw_tree_space_alloc(len + 1); - if (!da_name) - return; - - memcpy(da_name, &path[i], len); - da_name[len] = '\0'; - current_node->da_name = (char *) balloc_rebase(da_name); - - /* - * Recursively process the potential child node. - */ - phandle child = ofw_get_child_node(current); - if ((child != 0) && (child != -1)) { - ofw_tree_node_t *child_node = ofw_tree_node_alloc(); - if (child_node) { - ofw_tree_node_process(child_node, current_node, - child); - current_node->child = - (ofw_tree_node_t *) balloc_rebase(child_node); - } - } - - /* - * Count properties. - */ - static char name[OFW_TREE_PROPERTY_MAX_NAMELEN]; - static char name2[OFW_TREE_PROPERTY_MAX_NAMELEN]; - name[0] = '\0'; - while (ofw_next_property(current, name, name2) == 1) { - current_node->properties++; - memcpy(name, name2, OFW_TREE_PROPERTY_MAX_NAMELEN); - } - - if (!current_node->properties) - return; - - /* - * Copy properties. - */ - ofw_tree_property_t *property = - ofw_tree_properties_alloc(current_node->properties); - if (!property) - return; - - name[0] = '\0'; - for (i = 0; ofw_next_property(current, name, name2) == 1; i++) { - if (i == current_node->properties) - break; - - memcpy(name, name2, OFW_TREE_PROPERTY_MAX_NAMELEN); - memcpy(property[i].name, name, OFW_TREE_PROPERTY_MAX_NAMELEN); - property[i].name[OFW_TREE_PROPERTY_MAX_NAMELEN - 1] = '\0'; - - size_t size = ofw_get_proplen(current, name); - property[i].size = size; - - if (size) { - void *buf = ofw_tree_space_alloc(size); - if (buf) { - /* - * Copy property value to memory node. - */ - (void) ofw_get_property(current, name, buf, size); - property[i].value = balloc_rebase(buf); - } - } else - property[i].value = NULL; - } - - /* Just in case we ran out of memory. */ - current_node->properties = i; - current_node->property = (ofw_tree_property_t *) balloc_rebase(property); - - - /* - * Iteratively process the next peer node. - * Note that recursion is a bad idea here. - * Due to the topology of the OpenFirmware device tree, - * the nesting of peer nodes could be to wide and the - * risk of overflowing the stack is too real. - */ - phandle peer = ofw_get_peer_node(current); - if ((peer != 0) && (peer != -1)) { - ofw_tree_node_t *peer_node = ofw_tree_node_alloc(); - if (peer_node) { - current_node->peer = (ofw_tree_node_t *) balloc_rebase(peer_node); - current_node = peer_node; - current = peer; - /* - * Process the peer in next iteration. - */ - continue; - } - } - - /* - * No more peers on this level. - */ - break; - } -} - -/** Construct memory representation of OpenFirmware device tree. - * - * @return NULL on failure or kernel pointer to the root node. - * - */ -ofw_tree_node_t *ofw_tree_build(void) -{ - ofw_tree_node_t *root = ofw_tree_node_alloc(); - if (root) - ofw_tree_node_process(root, NULL, ofw_root); - - /* - * The firmware client interface does not automatically include the - * "ssm" node in the list of children of "/". A nasty yet working - * solution is to explicitly stick "ssm" to the OFW tree. - */ - phandle ssm_node = ofw_find_device("/ssm@0,0"); - if (ssm_node != -1) { - ofw_tree_node_t *ssm = ofw_tree_node_alloc(); - if (ssm) { - ofw_tree_node_process(ssm, root, - ofw_find_device("/ssm@0,0")); - ssm->peer = root->child; - root->child = (ofw_tree_node_t *) balloc_rebase(ssm); - } - } - - return (ofw_tree_node_t *) balloc_rebase(root); -} diff --git a/bsps/sparc64/shared/helenos/boot/sparc64/loader/main.c b/bsps/sparc64/shared/helenos/boot/sparc64/loader/main.c deleted file mode 100644 index 75579ed44c..0000000000 --- a/bsps/sparc64/shared/helenos/boot/sparc64/loader/main.c +++ /dev/null @@ -1,441 +0,0 @@ -/* - * Copyright (c) 2005 Martin Decky - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Modifications are made to switch to using printk rather than printf, - * and to remove portions of the HelenOS bootstrap process that are - * unnecessary on RTEMS. The removed code is elided with #if 0 ... #endif - * blocks. - * - * Removes some header files. Adds back some missing defines. - */ - -#define RTEMS - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#if 0 -#include "asm.h" -#include -#include "_components.h" -#include -#include -#include -#endif - -#include - -#if 0 -#define PAGE_WIDTH 14 -#define PAGE_SIZE (1 << PAGE_WIDTH) -#endif - -static bootinfo_t bootinfo; -#if 0 -static component_t components[COMPONENTS]; -static char *release = STRING(RELEASE); - -#ifdef REVISION - static char *revision = ", revision " STRING(REVISION); -#else - static char *revision = ""; -#endif - -#ifdef TIMESTAMP - static char *timestamp = "\nBuilt on " STRING(TIMESTAMP); -#else - static char *timestamp = ""; -#endif -#endif - -#if 0 -/** UltraSPARC subarchitecture - 1 for US, 3 for US3, 0 for other */ -static uint8_t subarchitecture = 0; -#endif - -#if 0 -/** - * mask of the MID field inside the ICBUS_CONFIG register shifted by - * MID_SHIFT bits to the right - */ -static uint16_t mid_mask; -#endif - -#if 0 -/** Print version information. */ -static void version_print(void) -{ - printk("HelenOS SPARC64 Bootloader\nRelease %s%s%s\n" - "Copyright (c) 2006 HelenOS project\n", - release, revision, timestamp); -} -#endif - -/* the lowest ID (read from the VER register) of some US3 CPU model */ -#define FIRST_US3_CPU 0x14 - -/* the greatest ID (read from the VER register) of some US3 CPU model */ -#define LAST_US3_CPU 0x19 - -/* UltraSPARC IIIi processor implementation code */ -#define US_IIIi_CODE 0x15 - -/* max. length of the "compatible" property of the root node */ -#define COMPATIBLE_PROP_MAXLEN 64 - -/* - * HelenOS bootloader will use these constants to distinguish particular - * UltraSPARC architectures - */ -#define COMPATIBLE_SUN4U 10 -#define COMPATIBLE_SUN4V 20 - -/** US architecture. COMPATIBLE_SUN4U for sun4v, COMPATIBLE_SUN4V for sun4u */ -static uint8_t architecture; - -/** - * Detects the UltraSPARC architecture (sun4u and sun4v currently supported) - * by inspecting the property called "compatible" in the OBP root node. - */ -static void detect_architecture(void) -{ - phandle root = ofw_find_device("/"); - char compatible[COMPATIBLE_PROP_MAXLEN]; - - if (ofw_get_property(root, "compatible", compatible, - COMPATIBLE_PROP_MAXLEN) <= 0) { - printk("Unable to determine architecture, default: sun4u.\n"); - architecture = COMPATIBLE_SUN4U; - return; - } - - if (strcmp(compatible, "sun4v") == 0) { - architecture = COMPATIBLE_SUN4V; - } else { - /* - * As not all sun4u machines have "sun4u" in their "compatible" - * OBP property (e.g. Serengeti's OBP "compatible" property is - * "SUNW,Serengeti"), we will by default fallback to sun4u if - * an unknown value of the "compatible" property is encountered. - */ - architecture = COMPATIBLE_SUN4U; - } -} - -#if 0 -/** - * Detects the subarchitecture (US, US3) of the sun4u - * processor. Sets the global variables "subarchitecture" and "mid_mask" to - * correct values. - */ -static void detect_subarchitecture(void) -{ - uint64_t v; - asm volatile ( - "rdpr %%ver, %0\n" - : "=r" (v) - ); - - v = (v << 16) >> 48; - if ((v >= FIRST_US3_CPU) && (v <= LAST_US3_CPU)) { - subarchitecture = SUBARCH_US3; - if (v == US_IIIi_CODE) - mid_mask = (1 << 5) - 1; - else - mid_mask = (1 << 10) - 1; - } else if (v < FIRST_US3_CPU) { - subarchitecture = SUBARCH_US; - mid_mask = (1 << 5) - 1; - } else - printk("\nThis CPU is not supported by HelenOS."); -} -#endif - -#if 0 -/** - * Performs sun4u-specific initialization. The components are expected - * to be already copied and boot allocator initialized. - * - * @param base kernel base virtual address - * @param top virtual address above which the boot allocator - * can make allocations - */ -static void bootstrap_sun4u(void *base, unsigned int top) -{ - void *balloc_base; - /* - * Claim and map the physical memory for the boot allocator. - * Initialize the boot allocator. - */ - balloc_base = base + ALIGN_UP(top, PAGE_SIZE); - (void) ofw_claim_phys(bootinfo.physmem_start + balloc_base, - BALLOC_MAX_SIZE); - (void) ofw_map(bootinfo.physmem_start + balloc_base, balloc_base, - BALLOC_MAX_SIZE, -1); - balloc_init(&bootinfo.ballocs, (uintptr_t) balloc_base, - (uintptr_t) balloc_base); -#if 0 - printf("Setting up screens..."); - ofw_setup_screens(); - printf("done.\n"); -#endif -#if 0 - printf("Canonizing OpenFirmware device tree..."); -#endif - bootinfo.ofw_root = ofw_tree_build(); -#if 0 - printf("done.\n"); -#endif -#if 0 -#ifdef CONFIG_AP - printf("Checking for secondary processors..."); - if (!ofw_cpu(mid_mask, bootinfo.physmem_start)) - printf("Error: unable to get CPU properties\n"); - printf("done.\n"); -#endif -#endif -} -#endif - -#if 0 -/** - * * Performs sun4v-specific initialization. The components are expected - * * to be already copied and boot allocator initialized. - * */ -static void bootstrap_sun4v(void) -{ - /* - * When SILO booted, the OBP had established a virtual to physical - * memory mapping. This mapping is not an identity (because the - * physical memory starts on non-zero address) - this is not - * surprising. But! The mapping even does not map virtual address - * 0 onto the starting address of the physical memory, but onto an - * address which is 0x400000 bytes higher. The reason is that the - * OBP had already used the memory just at the beginning of the - * physical memory, so that memory cannot be used by SILO (nor - * bootloader). As for now, we solve it by a nasty workaround: - * we pretend that the physical memory starts 0x400000 bytes further - * than it actually does (and hence pretend that the physical memory - * is 0x400000 bytes smaller). Of course, the value 0x400000 will most - * probably depend on the machine and OBP version (the workaround now - * works on Simics). A solution would be to inspect the "available" - * property of the "/memory" node to find out which parts of memory - * are used by OBP and redesign the algorithm of copying - * kernel/init tasks/ramdisk from the bootable image to memory - * (which we must do anyway because of issues with claiming the memory - * on Serengeti). - */ - bootinfo.physmem_start += 0x400000; - bootinfo.memmap.zones[0].start += 0x400000; - bootinfo.memmap.zones[0].size -= 0x400000; -#if 0 - printf("The sun4v init finished."); -#endif -} -#endif - -void bootstrap(void) -{ -#if 0 - void *base = (void *) KERNEL_VIRTUAL_ADDRESS; - unsigned int top = 0; - unsigned int i; - unsigned int j; -#endif - - detect_architecture(); -#if 0 - init_components(components); -#endif - - if (!ofw_get_physmem_start(&bootinfo.physmem_start)) { - printk("Error: unable to get start of physical memory.\n"); - halt(); - } - - if (!ofw_memmap(&bootinfo.memmap)) { - printk("Error: unable to get memory map, halting.\n"); - halt(); - } - - if (bootinfo.memmap.total == 0) { - printk("Error: no memory detected, halting.\n"); - halt(); - } - - /* - * SILO for some reason adds 0x400000 and subtracts - * bootinfo.physmem_start to/from silo_ramdisk_image. - * We just need plain physical address so we fix it up. - */ - if (silo_ramdisk_image) { - silo_ramdisk_image += bootinfo.physmem_start; - silo_ramdisk_image -= 0x400000; - - /* Install 1:1 mapping for the RAM disk. */ - if (ofw_map((void *) ((uintptr_t) silo_ramdisk_image), - (void *) ((uintptr_t) silo_ramdisk_image), - silo_ramdisk_size, -1) != 0) { - printk("Failed to map RAM disk.\n"); - halt(); - } - } - - printk("\nMemory statistics (total %d MB, starting at %" PRIxPTR ")\n", - bootinfo.memmap.total >> 20, bootinfo.physmem_start); - printk(" %x: kernel entry point\n", KERNEL_VIRTUAL_ADDRESS); - printk(" %p: boot info structure\n", &bootinfo); - -#if 0 - /* - * Figure out destination address for each component. - * In this phase, we don't copy the components yet because we want to - * to be careful not to overwrite anything, especially the components - * which haven't been copied yet. - */ - bootinfo.taskmap.count = 0; - for (i = 0; i < COMPONENTS; i++) { - printf(" %P: %s image (size %d bytes)\n", components[i].start, - components[i].name, components[i].size); - top = ALIGN_UP(top, PAGE_SIZE); - if (i > 0) { - if (bootinfo.taskmap.count == TASKMAP_MAX_RECORDS) { - printf("Skipping superfluous components.\n"); - break; - } - - bootinfo.taskmap.tasks[bootinfo.taskmap.count].addr = - base + top; - bootinfo.taskmap.tasks[bootinfo.taskmap.count].size = - components[i].size; - strncpy(bootinfo.taskmap.tasks[ - bootinfo.taskmap.count].name, components[i].name, - BOOTINFO_TASK_NAME_BUFLEN); - bootinfo.taskmap.count++; - } - top += components[i].size; - } - - printf("\n"); - - /* Do not consider RAM disk */ - j = bootinfo.taskmap.count - 1; - - if (silo_ramdisk_image) { - /* Treat the RAM disk as the last bootinfo task. */ - if (bootinfo.taskmap.count == TASKMAP_MAX_RECORDS) { - printf("Skipping RAM disk.\n"); - goto skip_ramdisk; - } - - top = ALIGN_UP(top, PAGE_SIZE); - bootinfo.taskmap.tasks[bootinfo.taskmap.count].addr = - base + top; - bootinfo.taskmap.tasks[bootinfo.taskmap.count].size = - silo_ramdisk_size; - bootinfo.taskmap.count++; - printf("Copying RAM disk..."); - - /* - * Claim and map the whole ramdisk as it may exceed the area - * given to us by SILO. - */ - (void) ofw_claim_phys(base + top, silo_ramdisk_size); - (void) ofw_map(bootinfo.physmem_start + base + top, base + top, - silo_ramdisk_size, -1); - memmove(base + top, (void *) ((uintptr_t) silo_ramdisk_image), - silo_ramdisk_size); - - printf("done.\n"); - top += silo_ramdisk_size; - } -skip_ramdisk: - - /* - * Now we can proceed to copy the components. We do it in reverse order - * so that we don't overwrite anything even if the components overlap - * with base. - */ - printf("Copying tasks..."); - for (i = COMPONENTS - 1; i > 0; i--, j--) { - printf("%s ", components[i].name); - - /* - * At this point, we claim the physical memory that we are - * going to use. We should be safe in case of the virtual - * address space because the OpenFirmware, according to its - * SPARC binding, should restrict its use of virtual memory - * to addresses from [0xffd00000; 0xffefffff] and - * [0xfe000000; 0xfeffffff]. - * - * XXX We don't map this piece of memory. We simply rely on - * SILO to have it done for us already in this case. - */ - (void) ofw_claim_phys(bootinfo.physmem_start + - bootinfo.taskmap.tasks[j].addr, - ALIGN_UP(components[i].size, PAGE_SIZE)); - - memcpy((void *) bootinfo.taskmap.tasks[j].addr, - components[i].start, components[i].size); - - } - printf(".\n"); - - printf("Copying kernel..."); - (void) ofw_claim_phys(bootinfo.physmem_start + base, - ALIGN_UP(components[0].size, PAGE_SIZE)); - memcpy(base, components[0].start, components[0].size); - printf("done.\n"); - - /* perform architecture-specific initialization */ - if (architecture == COMPATIBLE_SUN4U) { - bootstrap_sun4u(base, top); - } else if (architecture == COMPATIBLE_SUN4V) { - bootstrap_sun4v(); - } else { - printf("Unknown architecture.\n"); - halt(); - } - - printf("Booting the kernel...\n"); - jump_to_kernel((void *) KERNEL_VIRTUAL_ADDRESS, - bootinfo.physmem_start | BSP_PROCESSOR, &bootinfo, - sizeof(bootinfo), subarchitecture); -#endif -} diff --git a/bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwarch.c b/bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwarch.c deleted file mode 100644 index 318b4dc305..0000000000 --- a/bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwarch.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2005 Martin Decky - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * @brief Architecture dependent parts of OpenFirmware interface. - */ - -/* - * Modifications are made to compile for RTEMS. Removes asm.h and printf.h. - * Removes write(). - * - */ - - -#include -#include -#include -#include -#include -#if 0 -#include "asm.h" -#include -#endif - -#if 0 /* contaminates libc */ -void write(const char *str, const int len) -{ - int i; - - for (i = 0; i < len; i++) { - if (str[i] == '\n') - ofw_write("\r", 1); - ofw_write(&str[i], 1); - } -} -#endif - -int ofw_translate_failed(ofw_arg_t flag) -{ - return flag != -1; -} - -/** - * Starts all CPUs represented by following siblings of the given node, - * except for the current CPU. - * - * @param child The first child of the OFW tree node whose children - * represent CPUs to be woken up. - * @param current_mid MID of the current CPU, the current CPU will - * (of course) not be woken up. - * @param physmem_start Starting address of the physical memory. - * - * @return Number of CPUs which have the same parent node as - * "child". - * - */ -static int wake_cpus_in_node(phandle child, uint64_t current_mid, - uintptr_t physmem_start) -{ - int cpus; - - for (cpus = 0; (child != 0) && (child != -1); - child = ofw_get_peer_node(child), cpus++) { - char type_name[OFW_TREE_PROPERTY_MAX_VALUELEN]; - - if (ofw_get_property(child, "device_type", type_name, - OFW_TREE_PROPERTY_MAX_VALUELEN) > 0) { - type_name[OFW_TREE_PROPERTY_MAX_VALUELEN - 1] = 0; - if (strcmp(type_name, "cpu") == 0) { - uint32_t mid; - - /* - * "upa-portid" for US, "portid" for US-III, - * "cpuid" for US-IV - */ - if ((ofw_get_property(child, "upa-portid", &mid, sizeof(mid)) <= 0) - && (ofw_get_property(child, "portid", &mid, sizeof(mid)) <= 0) - && (ofw_get_property(child, "cpuid", &mid, sizeof(mid)) <= 0)) - continue; - - if (current_mid != mid) { - /* - * Start secondary processor. - */ - (void) ofw_call("SUNW,start-cpu", 3, 1, - NULL, child, KERNEL_VIRTUAL_ADDRESS, - physmem_start | AP_PROCESSOR); - } - } - } - } - - return cpus; -} - -/** - * Finds out the current CPU's MID and wakes up all AP processors. - */ -int ofw_cpu(uint16_t mid_mask, uintptr_t physmem_start) -{ - /* Get the current CPU MID */ - uint64_t current_mid; - - asm volatile ( - "ldxa [%1] %2, %0\n" - : "=r" (current_mid) - : "r" (0), "i" (ASI_ICBUS_CONFIG) - ); - - current_mid >>= ICBUS_CONFIG_MID_SHIFT; - current_mid &= mid_mask; - - /* Wake up the CPUs */ - - phandle cpus_parent = ofw_find_device("/ssm@0,0"); - if ((cpus_parent == 0) || (cpus_parent == -1)) - cpus_parent = ofw_find_device("/"); - - phandle node = ofw_get_child_node(cpus_parent); - int cpus = wake_cpus_in_node(node, current_mid, physmem_start); - while ((node != 0) && (node != -1)) { - char name[OFW_TREE_PROPERTY_MAX_VALUELEN]; - - if (ofw_get_property(node, "name", name, - OFW_TREE_PROPERTY_MAX_VALUELEN) > 0) { - name[OFW_TREE_PROPERTY_MAX_VALUELEN - 1] = 0; - if (strcmp(name, "cmp") == 0) { - phandle subnode = ofw_get_child_node(node); - cpus += wake_cpus_in_node(subnode, - current_mid, physmem_start); - } - } - node = ofw_get_peer_node(node); - } - - return cpus; -} - -/** Get physical memory starting address. - * - * @param start Pointer to variable where the physical memory starting - * address will be stored. - * - * @return Non-zero on succes, zero on failure. - * - */ -int ofw_get_physmem_start(uintptr_t *start) -{ - uint32_t memreg[4]; - if (ofw_get_property(ofw_memory, "reg", &memreg, sizeof(memreg)) <= 0) - return 0; - - *start = (((uint64_t) memreg[0]) << 32) | memreg[1]; - return 1; -} diff --git a/bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwasm.S b/bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwasm.S deleted file mode 100644 index 4956175131..0000000000 --- a/bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwasm.S +++ /dev/null @@ -1,62 +0,0 @@ -# -# Copyright (c) 2006 Martin Decky -# Copyright (c) 2006 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -/* - * This code is originally in asm.S. This is the only function used from that - * file, so it has been relocated to this new file ofw.S which is not actually - * located in the HelenOS code base. - */ - -#include -#include - -.register %g2, #scratch -.register %g3, #scratch - -.text - -.global ofw -ofw: - save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp - set ofw_cif, %l0 - ldx [%l0], %l0 - - rdpr %pstate, %l1 - and %l1, ~PSTATE_AM_BIT, %l2 - wrpr %l2, 0, %pstate - - jmpl %l0, %o7 - mov %i0, %o0 - - clr %g4 ! correction for gcc's ABI change - - wrpr %l1, 0, %pstate - - ret - restore %o0, 0, %o0 diff --git a/bsps/sparc64/shared/helenos/kernel/sparc64/src/cache.S b/bsps/sparc64/shared/helenos/kernel/sparc64/src/cache.S deleted file mode 100644 index 0aff799c50..0000000000 --- a/bsps/sparc64/shared/helenos/kernel/sparc64/src/cache.S +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#define DCACHE_TAG_SHIFT 2 - -.register %g2, #scratch -.register %g3, #scratch - -/** Flush the whole D-cache. */ -.global dcache_flush -dcache_flush: - set (DCACHE_SIZE - DCACHE_LINE_SIZE), %g1 - stxa %g0, [%g1] ASI_DCACHE_TAG -0: membar #Sync - subcc %g1, DCACHE_LINE_SIZE, %g1 - bnz,pt %xcc, 0b - stxa %g0, [%g1] ASI_DCACHE_TAG - membar #Sync - retl - ! beware SF Erratum #51, do not put the MEMBAR here - nop diff --git a/bsps/sparc64/shared/helenos/kernel/sparc64/src/sun4u/takemmu.S b/bsps/sparc64/shared/helenos/kernel/sparc64/src/sun4u/takemmu.S deleted file mode 100644 index f8fa1c6a24..0000000000 --- a/bsps/sparc64/shared/helenos/kernel/sparc64/src/sun4u/takemmu.S +++ /dev/null @@ -1,505 +0,0 @@ -# -# Copyright (c) 2005 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -/* - * This file originally is sparc64/src/sun4u/start.S - * A lot of changes are made to the code, because we only need the relevant - * portions for taking over the D- and I-MMUs. - * - */ -#define RTEMS - -#include - -/* RTEMS: moved all of these to a common include directory */ -#if 0 -#include -#include -#include -#endif -#include -#include - -#include -#include -#include - -#if 0 -#ifdef CONFIG_SMP -#include -#endif -#endif - -.register %g2, #scratch -.register %g3, #scratch -#if defined (RTEMS) -.section BOOTSTRAP -#endif - -#if 0 -.section K_TEXT_START, "ax" - -#define BSP_FLAG 1 - -/* - * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on - * a given processor. - */ -#if defined (US) - #define PHYSMEM_ADDR_SIZE 41 -#elif defined (US3) - #define PHYSMEM_ADDR_SIZE 43 -#endif -#endif - -#if defined (RTEMS) - #define PHYSMEM_ADDR_SIZE 43 -#endif - -#if 0 -/* - * Here is where the kernel is passed control from the boot loader. - * - * The registers are expected to be in this state: - * - %o0 starting address of physical memory + bootstrap processor flag - * bits 63...1: physical memory starting address / 2 - * bit 0: non-zero on BSP processor, zero on AP processors - * - %o1 bootinfo structure address (BSP only) - * - %o2 bootinfo structure size (BSP only) - * - * Moreover, we depend on boot having established the following environment: - * - TLBs are on - * - identity mapping for the kernel image - */ -.global kernel_image_start -kernel_image_start: - mov BSP_FLAG, %l0 - and %o0, %l0, %l7 ! l7 <= bootstrap processor? - andn %o0, %l0, %l6 ! l6 <= start of physical memory - - ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. - srlx %l6, 13, %l5 - - ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] - sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 - srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 - - /* - * Setup basic runtime environment. - */ - - wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows - wrpr %g0, 0, %canrestore ! get rid of windows we will - ! never need again - wrpr %g0, 0, %otherwin ! make sure the window state is - ! consistent - wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window - ! traps for kernel - - wrpr %g0, 0, %wstate ! use default spill/fill trap - - wrpr %g0, 0, %tl ! TL = 0, primary context - ! register is used - - wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable - ! 32-bit address masking - - wrpr %g0, 0, %pil ! intialize %pil -#endif - -#if defined (RTEMS) - /* pass o0 as start of physical memory */ -.global _take_mmu -_take_mmu: - save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp - mov %i0, %l6 -#endif - - /* these are copied from above */ - ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. - srlx %l6, 13, %l5 - - ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] - sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 - srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 - - /* - * Switch to kernel trap table. - */ - sethi %hi(trap_table), %g1 - wrpr %g1, %lo(trap_table), %tba - - - /* - * Take over the DMMU by installing locked TTE entry identically - * mapping the first 4M of memory. - * - * In case of DMMU, no FLUSH instructions need to be issued. Because of - * that, the old DTLB contents can be demapped pretty straightforwardly - * and without causing any traps. - */ - - wr %g0, ASI_DMMU, %asi -/* -#define SET_TLB_DEMAP_CMD(r1, context_id) \ - set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ - TLB_DEMAP_CONTEXT_SHIFT), %r1 -*/ -/* - ! demap context 0 - SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) - stxa %g0, [%g1] ASI_DMMU_DEMAP - membar #Sync -*/ -#define SET_TLB_TAG(xVMA, r1, context) \ - set xVMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 - - ! write DTLB tag - SET_TLB_TAG(0x4000, g1, MEM_CONTEXT_KERNEL) - stxa %g1, [VA_DMMU_TAG_ACCESS] %asi - membar #Sync - -#ifdef CONFIG_VIRT_IDX_DCACHE -#define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm)) -#else /* CONFIG_VIRT_IDX_DCACHE */ -#define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm)) -#endif /* CONFIG_VIRT_IDX_DCACHE */ - -#define SET_TLB_DATA(r1, r2, imm) \ - set TTE_LOW_DATA(imm), %r1; \ - or %r1, %l5, %r1; \ - mov PAGESIZE_4M, %r2; \ - sllx %r2, TTE_SIZE_SHIFT, %r2; \ - or %r1, %r2, %r1; \ - mov 1, %r2; \ - sllx %r2, TTE_V_SHIFT, %r2; \ - or %r1, %r2, %r1; - - ! write DTLB data and install the kernel mapping - SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping - stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG - membar #Sync - - /* - * Because we cannot use global mappings (because we want to have - * separate 64-bit address spaces for both the kernel and the - * userspace), we prepare the identity mapping also in context 1. This - * step is required by the code installing the ITLB mapping. - */ -/* ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) - SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) - stxa %g1, [VA_DMMU_TAG_ACCESS] %asi - membar #Sync - - ! write DTLB data and install the kernel mapping in context 1 - SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping - stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG - membar #Sync -*/ - /* - * Now is time to take over the IMMU. Unfortunatelly, it cannot be done - * as easily as the DMMU, because the IMMU is mapping the code it - * executes. - * - * [ Note that brave experiments with disabling the IMMU and using the - * DMMU approach failed after a dozen of desparate days with only little - * success. ] - * - * The approach used here is inspired from OpenBSD. First, the kernel - * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and - * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped - * afterwards and replaced with the kernel permanent mapping. Finally, - * the kernel switches back to context 0 and demaps context 1. - * - * Moreover, the IMMU requires use of the FLUSH instructions. But that - * is OK because we always use operands with addresses already mapped by - * the taken over DTLB. - */ -#if 0 - set kernel_image_start, %g5 -#endif -#if defined (RTEMS) - set _take_mmu, %g5 -#endif -/* - ! write ITLB tag of context 1 - SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) - mov VA_DMMU_TAG_ACCESS, %g2 - stxa %g1, [%g2] ASI_IMMU - flush %g5 - - ! write ITLB data and install the temporary mapping in context 1 - SET_TLB_DATA(g1, g2, 0) ! use non-global mapping - stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG - flush %g5 - - ! switch to context 1 - mov MEM_CONTEXT_TEMP, %g1 - stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! - flush %g5 - - ! demap context 0 - SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) - stxa %g0, [%g1] ASI_IMMU_DEMAP - flush %g5 -*/ - ! write ITLB tag of context 0 - SET_TLB_TAG(0x4000, g1, MEM_CONTEXT_KERNEL) - mov VA_DMMU_TAG_ACCESS, %g2 - stxa %g1, [%g2] ASI_IMMU - flush %g5 - - ! write ITLB data and install the permanent kernel mapping in context 0 - SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping - stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG - flush %g5 - - ! GAB: add more mappings for dmmu in 4 MB chunks - SET_TLB_TAG(0x404000, g1, MEM_CONTEXT_KERNEL) - stxa %g1, [VA_DMMU_TAG_ACCESS] %asi - membar #Sync - set 0x400000, %g1 - add %g1, %l5, %l5 - SET_TLB_DATA(g1, g2, TTE_L | TTE_W) - stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG - membar #Sync - - SET_TLB_TAG(0x804000, g1, MEM_CONTEXT_KERNEL) - stxa %g1, [VA_DMMU_TAG_ACCESS] %asi - membar #Sync - set 0x400000, %g1 - add %g1, %l5, %l5 - SET_TLB_DATA(g1, g2, TTE_L | TTE_W) - stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG - membar #Sync - - SET_TLB_TAG(0xc04000, g1, MEM_CONTEXT_KERNEL) - stxa %g1, [VA_DMMU_TAG_ACCESS] %asi - membar #Sync - set 0x400000, %g1 - add %g1, %l5, %l5 - SET_TLB_DATA(g1, g2, TTE_L | TTE_W) - stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG - membar #Sync - - -/* - ! enter nucleus - using context 0 - wrpr %g0, 1, %tl - - ! demap context 1 - SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) - stxa %g0, [%g1] ASI_IMMU_DEMAP - flush %g5 - - ! set context 0 in the primary context register - stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! - flush %g5 - - ! leave nucleus - using primary context, i.e. context 0 - wrpr %g0, 0, %tl - - wrpr %g0, 0, %wstate ! default spill/fill trap -*/ -#if 0 - brz %l7, 1f ! skip if you are not the bootstrap CPU - nop - - /* - * Save physmem_base for use by the mm subsystem. - * %l6 contains starting physical address - */ - sethi %hi(physmem_base), %l4 - stx %l6, [%l4 + %lo(physmem_base)] - - /* - * Precompute kernel 8K TLB data template. - * %l5 contains starting physical address - * bits [(PHYSMEM_ADDR_SIZE - 1):13] - */ - sethi %hi(kernel_8k_tlb_data_template), %l4 - ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 - or %l3, %l5, %l3 - stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] -#endif - - /* - * Flush D-Cache. - */ - call dcache_flush - nop - -#if 0 - /* - * So far, we have not touched the stack. - * It is a good idea to set the kernel stack to a known state now. - */ - sethi %hi(temporary_boot_stack), %sp - or %sp, %lo(temporary_boot_stack), %sp - sub %sp, STACK_BIAS, %sp - - sethi %hi(bootinfo), %o0 - call memcpy ! copy bootinfo - or %o0, %lo(bootinfo), %o0 - - call arch_pre_main - nop - - call main_bsp - nop -#endif - -#if defined (RTEMS) - ret - restore -#endif - - /* Not reached. */ - -0: - ba %xcc, 0b - nop - -#if 0 -1: -#ifdef CONFIG_SMP - /* - * Determine the width of the MID and save its mask to %g3. The width - * is - * * 5 for US and US-IIIi, - * * 10 for US3 except US-IIIi. - */ -#if defined(US) - mov 0x1f, %g3 -#elif defined(US3) - mov 0x3ff, %g3 - rdpr %ver, %g2 - sllx %g2, 16, %g2 - srlx %g2, 48, %g2 - cmp %g2, IMPL_ULTRASPARCIII_I - move %xcc, 0x1f, %g3 -#endif - - /* - * Read MID from the processor. - */ - ldxa [%g0] ASI_ICBUS_CONFIG, %g1 - srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 - and %g1, %g3, %g1 - - /* - * Active loop for APs until the BSP picks them up. A processor cannot - * leave the loop until the global variable 'waking_up_mid' equals its - * MID. - */ - set waking_up_mid, %g2 -2: - ldx [%g2], %g3 - cmp %g3, %g1 - bne %xcc, 2b - nop - - /* - * Configure stack for the AP. - * The AP is expected to use the stack saved - * in the ctx global variable. - */ - set ctx, %g1 - add %g1, OFFSET_SP, %g1 - ldx [%g1], %o6 - - call main_ap - nop - - /* Not reached. */ -#endif - -0: - ba %xcc, 0b - nop - - -.section K_DATA_START, "aw", @progbits - -/* - * Create small stack to be used by the bootstrap processor. It is going to be - * used only for a very limited period of time, but we switch to it anyway, - * just to be sure we are properly initialized. - */ - -#define INITIAL_STACK_SIZE 1024 - -.align STACK_ALIGNMENT - .space INITIAL_STACK_SIZE -.align STACK_ALIGNMENT -temporary_boot_stack: - .space STACK_WINDOW_SAVE_AREA_SIZE - -#endif /* 0 */ - -.data - -.align 8 -.global physmem_base ! copy of the physical memory base address -physmem_base: - .quad 0 - -/* - * The fast_data_access_mmu_miss_data_hi label and the end_of_identity and - * kernel_8k_tlb_data_template variables are meant to stay together, - * aligned on 16B boundary. - */ -.global fast_data_access_mmu_miss_data_hi -.global end_of_identity -.global kernel_8k_tlb_data_template - -.align 16 -/* - * This label is used by the fast_data_access_MMU_miss trap handler. - */ -fast_data_access_mmu_miss_data_hi: -/* - * This variable is used by the fast_data_access_MMU_miss trap handler. - * In runtime, it is modified to contain the address of the end of physical - * memory. - */ -end_of_identity: - .quad -1 -/* - * This variable is used by the fast_data_access_MMU_miss trap handler. - * In runtime, it is further modified to reflect the starting address of - * physical memory. - */ -kernel_8k_tlb_data_template: -#ifdef CONFIG_VIRT_IDX_DCACHE - .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ - TTE_CV | TTE_P | TTE_W) -#else /* CONFIG_VIRT_IDX_DCACHE */ - .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ - TTE_P | TTE_W) -#endif /* CONFIG_VIRT_IDX_DCACHE */ diff --git a/bsps/sparc64/shared/start/halt.S b/bsps/sparc64/shared/start/halt.S deleted file mode 100644 index 53be7bde08..0000000000 --- a/bsps/sparc64/shared/start/halt.S +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Copyright (c) 2010. Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -.text - -PUBLIC(halt) - .global halt - SYM(halt): - b halt - nop diff --git a/bsps/sparc64/shared/start/linkcmds b/bsps/sparc64/shared/start/linkcmds deleted file mode 100644 index b25b635e25..0000000000 --- a/bsps/sparc64/shared/start/linkcmds +++ /dev/null @@ -1,201 +0,0 @@ -/* linkcmds - */ - -/* - * For alignment, SPARC v9 specifies that instructions are 4-byte aligned, - * and the worst-case alignment requirements for data are for quad-word - * accesses, which must be 16-byte aligned. - */ - -/* - * Declare some sizes. - */ -RamBase = DEFINED(RamBase) ? RamBase : 0x0; -RamSize = DEFINED(RamSize) ? RamSize : 4M; -RamEnd = RamBase + RamSize; -HeapSize = DEFINED(HeapSize) ? HeapSize : 1M; - -RAM_END = RamBase + RamSize; - -/* Default linker script, for normal executables */ -OUTPUT_FORMAT("elf64-sparc") -ENTRY(_start) -STARTUP(start.o) - -MEMORY -{ - ram : ORIGIN = 0x0, LENGTH = 12M -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - /* Internal text space or external memory */ - .text 0x4000 : AT (0x4000) - { - *(BOOTSTRAP); - *(.text*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - __start_set_sysctl_set = .; - *(set_sysctl_*); - __stop_set_sysctl_set = ABSOLUTE(.); - *(set_domain_*); - *(set_pseudo_*); - - *(.eh_frame) - . = ALIGN (16); - - *(.gnu.linkonce.t*) - *(.gcc_except_table*) - - /* - * C++ constructors - */ - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - - _rodata_start = . ; - *(.rodata*) - KEEP (*(SORT(.rtemsroset.*))) - *(.gnu.linkonce.r*) - _erodata = ALIGN( 0x10 ) ; - - *(.lit) - *(.shdata) - - . = ALIGN (16); - _endtext = . ; - _etext = . ; - } > ram - - .tdata : AT (ADDR (.text) + SIZEOF (.text)) { - _TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - _TLS_Data_end = .; - } > ram - .tbss : AT (ADDR (.tdata) + SIZEOF (.tdata)) { - _TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - _TLS_BSS_end = .; - } > ram - _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; - _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; - _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; - _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; - _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; - _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - - .rela.dyn : AT (ADDR (.tbss) + SIZEOF (.tbss)) - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - *(.rela.rtemsroset*) - *(.rela.rtemsrwset*) - } > ram - - .data : AT (ADDR (.rela.dyn) + SIZEOF (.rela.dyn)) - { - PROVIDE (__data_start = .) ; - data_start = . ; - _data_start = . ; - *(.data) - *(.data*) - KEEP (*(SORT(.rtemsrwset.*))) - *(.rodata) /* We need to include .rodata here if gcc is used */ - *(.rodata*) /* with -fdata-sections. */ - *(.gnu.linkonce.d*) - . = ALIGN(2); - edata = . ; - _edata = . ; - PROVIDE (__data_end = .) ; - } > ram - - /* XXX - __data_load_start = LOADADDR(.data); - __data_load_end = __data_load_start + SIZEOF(.data); - */ - . = ALIGN (16); - .dynamic : { *(.dynamic) } >ram - .jcr : { *(.jcr) } > ram - .got : { *(.got) } >ram - .plt : { *(.plt) } >ram - .dynrel : { *(.dynrel) } >ram - .shbss : { *(.shbss) } > ram - .bss : - { - FILL(0x00000000); - . = ALIGN(16); - __bss_start = ALIGN(0x8); - bss_start = .; - bss_start = .; - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - . = ALIGN (16); - end = .; - _end = .; - __end = .; - } > ram - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > ram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - PROVIDE (WorkAreaBase = .); - } > ram - - .heap : { - . += HeapSize; - PROVIDE (HeapBase = .); - . += HeapSize; - } > ram - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } -} - - diff --git a/bsps/sparc64/shared/start/setvec.c b/bsps/sparc64/shared/start/setvec.c deleted file mode 100644 index 12c7713285..0000000000 --- a/bsps/sparc64/shared/start/setvec.c +++ /dev/null @@ -1,57 +0,0 @@ -/* set_vector - * - * This routine installs an interrupt vector on the sun4v niagara - * - * INPUT PARAMETERS: - * handler - interrupt handler entry point - * vector - vector number - * type - 0 indicates raw hardware connect - * 1 indicates RTEMS interrupt connect - * - * OUTPUT PARAMETERS: NONE - * - * RETURNS: - * address of previous interrupt handler - * - * COPYRIGHT (c) 1989-1998. On-Line Applications Research Corporation (OAR). - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -) -{ - rtems_isr_entry previous_isr; - uint32_t real_trap; - uint32_t source; - int bit_mask; - - if ( type ) - rtems_interrupt_catch( handler, vector, &previous_isr ); - else - _CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr ); - - real_trap = SPARC_REAL_TRAP_NUMBER( vector ); - - /* check if this is an interrupt, if so, clear and unmask interrupts for - * this level - */ - /* Interrupts have real_trap numbers between 0x41 and 0x4F (levels 1 - 15) */ - if (real_trap >= 0x41 && real_trap <= 0x4F) { - source = real_trap - 0x40; - bit_mask = 1< -#include - -#define PSTATE_PRIV_BIT 4 - -.register %g2, #scratch -.register %g3, #scratch -.register %g6, #scratch -.register %g7, #scratch - -.section BOOTSTRAP, "ax" - -PUBLIC(_start) - .global _start - SYM(_start): - start: - b 1f - nop - - /* - * This header forces SILO to load the image at 0x4000. - * More precisely, SILO will think this is an old version of Linux. - */ - .ascii "HdrS" - .word 0 - .half 0 - .half 0 - .half 0 - .half 0 - .global silo_ramdisk_image - silo_ramdisk_image: - .word 0 - .global silo_ramdisk_size - silo_ramdisk_size: - .word 0 - - .align 8 - 1: - /* - * Disable interrupts and disable address masking. - */ - wrpr %g0, PSTATE_PRIV_BIT, %pstate - - wrpr %g0, SPARC_NUMBER_OF_REGISTER_WINDOWS - 2, %cansave ! set maximum saveable windows - wrpr %g0, 0, %canrestore ! get rid of windows we will never need again - wrpr %g0, 0, %otherwin ! make sure the window state is consistent - wrpr %g0, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel - - /* g4 needs to be cleared for gcc */ - mov %g0, %g4 - - /* Clear the bss */ - setx SYM(bss_start), %l0, %g2 ! g2 = start of bss - setx SYM(_end), %l0, %g3 ! g3 = end of bss -zerobss: - stx %g0, [%g2] - add %g2, 8, %g2 - cmp %g2, %g3 - bleu,a zerobss - nop - - /* Install stack */ - set SYM(_ISR_Stack_area_end), %sp - add %sp, -SPARC64_MINIMUM_STACK_FRAME_SIZE, %sp - add %sp, -STACK_BIAS, %sp - - /* BSP-specific pre-bootcard initializations */ - call SYM(_BSP_init) - nop - - setx ofw_cif, %l0, %l1 - - call ofw_init ! initialize OpenFirmware - stx %o4, [%l1] - - call bootstrap - nop - - - /* Set up ISR handler for interrupt enable/disable */ - setx SYM(syscall), %l0, %o1 - setx param_space, %l0, %o2 - call SYM(_CPU_ISR_install_raw_handler) - mov 0x100, %o0 - - /* Don't need to copy initialized data to RAM--link puts all in RAM already */ - - mov %g0, %o0 ! clear command line passed to main - call SYM(boot_card) - sub %sp, 0x60, %sp ! make room on stack (necessary?) - - call SYM(halt) - nop - -halted: nop - b SYM(halted) - -.section BOOTSTRAP - .align CPU_ALIGNMENT - param_space: - .space 8 diff --git a/bsps/sparc64/shared/start/trap_table.S b/bsps/sparc64/shared/start/trap_table.S deleted file mode 100644 index 6dc42b4448..0000000000 --- a/bsps/sparc64/shared/start/trap_table.S +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * trap_table.S - * - * trap code for Sparc64 RTEMS. - * - * COPYRIGHT (c) 2010 Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * This code defines the space for the trap table used by sun4u. - */ - -#include -#include -#include - -.register %g2, #scratch - -.macro JUMP_TO_TRAP offset - sethi %hi(real_trap_table), %g1; - sethi %hi(\offset), %g2; - or %g1, %lo(real_trap_table), %g1; - or %g2, %lo(\offset), %g2; ! g2 = offset - ldx [%g1], %g1; ! g1 = real_trap_table - add %g1, %g2, %g1; ! g1 = real_trap_table[offset] - jmpl %g1, %g0; - nop; -.endm - -! space to save a pointer to the real trap table -.section .data - .align 8 - .global real_trap_table - SYM(real_trap_table): - .space 8 - -.section .text - .align (TABLE_SIZE) -PUBLIC(trap_table) - SYM(trap_table): - - .irp idx, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, \ - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, \ - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, \ - 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, \ - 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, \ - 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, \ - 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, \ - 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, \ - 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, \ - 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, \ - 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, \ - 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, \ - 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, \ - 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ - 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, \ - 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, \ - 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, \ - 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, \ - 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, \ - 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, \ - 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, \ - 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, \ - 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, \ - 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, \ - 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, \ - 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, \ - 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, \ - 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, \ - 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, \ - 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, \ - 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, \ - 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, \ - 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, \ - 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, \ - 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, \ - 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, \ - 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, \ - 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, \ - 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, \ - 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, \ - 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, \ - 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, \ - 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, \ - 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, \ - 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, \ - 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, \ - 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, \ - 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, \ - 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, \ - 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, \ - 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511 - - .org trap_table + ((\idx)*32) - JUMP_TO_TRAP( ((\idx)*32) ); - .endr - - .irp idx, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, \ - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, \ - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, \ - 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, \ - 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, \ - 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, \ - 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, \ - 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, \ - 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, \ - 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, \ - 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, \ - 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, \ - 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, \ - 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ - 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, \ - 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, \ - 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, \ - 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, \ - 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, \ - 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, \ - 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, \ - 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, \ - 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, \ - 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, \ - 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, \ - 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, \ - 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, \ - 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, \ - 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, \ - 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, \ - 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, \ - 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, \ - 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, \ - 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, \ - 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, \ - 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, \ - 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, \ - 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, \ - 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, \ - 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, \ - 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, \ - 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, \ - 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, \ - 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, \ - 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, \ - 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, \ - 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, \ - 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, \ - 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, \ - 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, \ - 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511 - - .org trap_table + 512*32 + ((\idx)*32) - JUMP_TO_TRAP( 512*32 + ((\idx)*32) ); - .endr - diff --git a/bsps/sparc64/usiii/README.md b/bsps/sparc64/usiii/README.md deleted file mode 100644 index 68593825db..0000000000 --- a/bsps/sparc64/usiii/README.md +++ /dev/null @@ -1,63 +0,0 @@ -usiii -===== -``` -BSP NAME: usiii -BOARD: -BUS: n/a -CPU FAMILY: SPARC V9 (a.k.a. sun4u) -CPU: UltraSPARC III -COPROCESSORS: -MODE: n/a - -DEBUG MONITOR: -``` - -PERIPHERALS ------------ -``` -TIMERS: TICK register (ASR 4) - RESOLUTION: CPU clock resolution -SERIAL PORTS: -REAL-TIME CLOCK: -DMA: none -VIDEO: none -SCSI: none -NETWORKING: none -``` - -DRIVER INFORMATION ------------------- -``` -CLOCK DRIVER: -IOSUPP DRIVER: -SHMSUPP: -TIMER DRIVER: -TTY DRIVER: -``` - -STDIO ------ -``` -PORT: -ELECTRICAL: -BAUD: -BITS PER CHARACTER: -PARITY: -STOP BITS: -``` - -Board description ------------------ -clock rate: -bus width: -ROM: -RAM: - -This BSP is designed to operate on the UltraSPARC III SPARC64 -and similar processors. - -This BSP has been run on the Simics simulator with the serengeti target. - -Simics: -A commercially available simulator licensed by Virtutech. -https://www.simics.net/ diff --git a/bsps/sparc64/usiii/config/usiii.cfg b/bsps/sparc64/usiii/config/usiii.cfg deleted file mode 100644 index ee1c5089b0..0000000000 --- a/bsps/sparc64/usiii/config/usiii.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# -# Config file for the UltraSparc III, IV SPARC64 processors. -# TODO: currently configured and tested only for ultrasparc3 -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=sparc64 - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = -mcpu=ultrasparc3 - -# optimize flag: typically -g -O2 -CFLAGS_OPTIMIZE_V = -g -O2 -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/sparc64/usiii/include/bsp.h b/bsps/sparc64/usiii/include/bsp.h deleted file mode 100644 index 6286af26c6..0000000000 --- a/bsps/sparc64/usiii/include/bsp.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @ingroup RTEMSBSPsSPARC64USIII - * - * @brief Global BSP definitions. - */ - -/* bsp.h - * - * This include file contains all SPARC64 simulator definitions. - * - * COPYRIGHT (c) 1989-1998. On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef LIBBSP_SPARC64_USIII_BSP_H -#define LIBBSP_SPARC64_USIII_BSP_H - -/** - * @defgroup RTEMSBSPsSPARC64USIII USIII - * - * @ingroup RTEMSBSPsSPARC64 - * - * @brief USIII Board Support Package. - * - * @{ - */ - -#include -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* support for simulated clock tick */ -/* -void *clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body -*/ - -/* this should be defined somewhere */ -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif diff --git a/bsps/sparc64/usiii/include/bsp/irq.h b/bsps/sparc64/usiii/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/sparc64/usiii/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sparc64/usiii/include/tm27.h b/bsps/sparc64/usiii/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/bsps/sparc64/usiii/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sparc64/usiii/start/bspinit.S b/bsps/sparc64/usiii/start/bspinit.S deleted file mode 100644 index 78ad830e6c..0000000000 --- a/bsps/sparc64/usiii/start/bspinit.S +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * BSP specific initialization for Sparc64 RTEMS -- sun4u BSP - * - * This code defines start code specific to the sun4u BSP - */ - -/* - * COPYRIGHT (c) 2010 Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -#include - -#define LSU_CR_IM_MASK (0x0004) /* bit 2 */ -#define LSU_CR_DM_MASK (0x0008) /* bit 3 */ - -#define STACK_WINDOW_SAVE_AREA_SIZE (16*8) - -.register %g2, #scratch -.register %g3, #scratch - -.section .text - -PUBLIC(_BSP_init) -.global _BSP_init - SYM(_BSP_init): - save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp - - ! copy the tba - sethi %hi(real_trap_table), %o0 - rdpr %tba, %o2 - stx %o2, [%o0 + %lo(real_trap_table)] - -! /* copy firmware trap table so that RTEMS can install ISR handlers */ -! setx SYM(trap_table), %l0, %o0 -! rdpr %tba, %o1 -! set TABLE_SIZE, %o2 -! call memcpy -! nop - - mov %g0, %o0 - call _take_mmu - nop - - ret - restore - diff --git a/cpukit/score/cpu/sparc64/README.md b/cpukit/score/cpu/sparc64/README.md deleted file mode 100644 index 14091f6789..0000000000 --- a/cpukit/score/cpu/sparc64/README.md +++ /dev/null @@ -1,14 +0,0 @@ -SPARC64 -======= - -A lot of explanation needed, will do when known. - -The score/cpu/sparc64 contains only code that can execute without accessing -privileged registers or using privileged instructions. This was done because -the privileged registers differ between the sun4u and sun4v models. - -The model specific and privileged code that would normally be found in -score/cpu/sparc64 resides in libcpu/sparc64/@RTEMS_CPU_MODEL@/score or in -libcpu/sparc64/shared/score directory. This is primarily the interrupt -handling code. - diff --git a/cpukit/score/cpu/sparc64/context.S b/cpukit/score/cpu/sparc64/context.S deleted file mode 100644 index 8e9178218f..0000000000 --- a/cpukit/score/cpu/sparc64/context.S +++ /dev/null @@ -1,327 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* context.S - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language. - * - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - -/* - * The assembler needs to be told that we know what to do with - * the global registers. - */ -.register %g2, #scratch -.register %g3, #scratch -.register %g6, #scratch -.register %g7, #scratch - -#if (SPARC_HAS_FPU == 1) - -/* - * void _CPU_Context_save_fp( - * void **fp_context_ptr - * ) - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - */ - - .align 4 -PUBLIC(_CPU_Context_save_fp) - SYM(_CPU_Context_save_fp): - save %sp, -SPARC64_MINIMUM_STACK_FRAME_SIZE, %sp - - /* - * The following enables the floating point unit. - */ - - sparc64_enable_FPU(%l0) - - /* - * Although sun4v supports alternate register names for double- - * and quad-word floating point, SPARC v9 only uses f[#] - * - * Because quad-word fp is not supported by the hardware in - * many situations, we stick with double-word fp operations - */ - ldx [%i0], %l0 - std %f0, [%l0] - std %f2, [%l0 + F2_OFFSET] - std %f4, [%l0 + F4_OFFSET] - std %f6, [%l0 + F6_OFFSET] - std %f8, [%l0 + F8_OFFSET] - std %f10, [%l0 + F1O_OFFSET] - std %f12, [%l0 + F12_OFFSET] - std %f14, [%l0 + F14_OFFSET] - std %f16, [%l0 + F16_OFFSET] - std %f18, [%l0 + F18_OFFSET] - std %f20, [%l0 + F2O_OFFSET] - std %f22, [%l0 + F22_OFFSET] - std %f24, [%l0 + F24_OFFSET] - std %f26, [%l0 + F26_OFFSET] - std %f28, [%l0 + F28_OFFSET] - std %f30, [%l0 + F3O_OFFSET] - std %f32, [%l0 + F32_OFFSET] - std %f34, [%l0 + F34_OFFSET] - std %f36, [%l0 + F36_OFFSET] - std %f38, [%l0 + F38_OFFSET] - std %f40, [%l0 + F4O_OFFSET] - std %f42, [%l0 + F42_OFFSET] - std %f44, [%l0 + F44_OFFSET] - std %f46, [%l0 + F46_OFFSET] - std %f48, [%l0 + F48_OFFSET] - std %f50, [%l0 + F5O_OFFSET] - std %f52, [%l0 + F52_OFFSET] - std %f54, [%l0 + F54_OFFSET] - std %f56, [%l0 + F56_OFFSET] - std %f58, [%l0 + F58_OFFSET] - std %f60, [%l0 + F6O_OFFSET] - std %f62, [%l0 + F62_OFFSET] - stx %fsr, [%l0 + FSR_OFFSET] - ret - restore - - /* - * void _CPU_Context_restore_fp( - * void **fp_context_ptr - * ) - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - */ - - .align 4 -PUBLIC(_CPU_Context_restore_fp) - SYM(_CPU_Context_restore_fp): - save %sp, -SPARC64_MINIMUM_STACK_FRAME_SIZE , %sp - - /* - * The following enables the floating point unit. - */ - - sparc64_enable_FPU(%l0) - - ldx [%i0], %l0 - ldd [%l0 + FO_OFFSET], %f0 - ldd [%l0 + F2_OFFSET], %f2 - ldd [%l0 + F4_OFFSET], %f4 - ldd [%l0 + F6_OFFSET], %f6 - ldd [%l0 + F8_OFFSET], %f8 - ldd [%l0 + F1O_OFFSET], %f10 - ldd [%l0 + F12_OFFSET], %f12 - ldd [%l0 + F14_OFFSET], %f14 - ldd [%l0 + F16_OFFSET], %f16 - ldd [%l0 + F18_OFFSET], %f18 - ldd [%l0 + F2O_OFFSET], %f20 - ldd [%l0 + F22_OFFSET], %f22 - ldd [%l0 + F24_OFFSET], %f24 - ldd [%l0 + F26_OFFSET], %f26 - ldd [%l0 + F28_OFFSET], %f28 - ldd [%l0 + F3O_OFFSET], %f30 - ldd [%l0 + F32_OFFSET], %f32 - ldd [%l0 + F34_OFFSET], %f34 - ldd [%l0 + F36_OFFSET], %f36 - ldd [%l0 + F38_OFFSET], %f38 - ldd [%l0 + F4O_OFFSET], %f40 - ldd [%l0 + F42_OFFSET], %f42 - ldd [%l0 + F44_OFFSET], %f44 - ldd [%l0 + F46_OFFSET], %f46 - ldd [%l0 + F48_OFFSET], %f48 - ldd [%l0 + F5O_OFFSET], %f50 - ldd [%l0 + F52_OFFSET], %f52 - ldd [%l0 + F54_OFFSET], %f54 - ldd [%l0 + F56_OFFSET], %f56 - ldd [%l0 + F58_OFFSET], %f58 - ldd [%l0 + F6O_OFFSET], %f60 - ldd [%l0 + F62_OFFSET], %f62 - ldx [%l0 + FSR_OFFSET], %fsr - ret - restore - -#endif /* SPARC_HAS_FPU */ - - /* - * void _CPU_Context_switch( - * Context_Control *run, - * Context_Control *heir - * ) - * - * This routine performs a normal non-FP context switch. - */ - - .align 4 -PUBLIC(_CPU_Context_switch) - SYM(_CPU_Context_switch): - ! skip g0 - stx %g1, [%o0 + G1_OFFSET] ! save the global registers - stx %g2, [%o0 + G2_OFFSET] - stx %g3, [%o0 + G3_OFFSET] - stx %g4, [%o0 + G4_OFFSET] - stx %g5, [%o0 + G5_OFFSET] - stx %g6, [%o0 + G6_OFFSET] - stx %g7, [%o0 + G7_OFFSET] - - ! load the address of the ISR stack nesting prevention flag - setx SYM(_CPU_ISR_Dispatch_disable), %g1, %g2 - lduw [%g2], %g2 - - ! save it a bit later so we do not waste a couple of cycles - - stx %l0, [%o0 + L0_OFFSET] ! save the local registers - stx %l1, [%o0 + L1_OFFSET] - stx %l2, [%o0 + L2_OFFSET] - stx %l3, [%o0 + L3_OFFSET] - stx %l4, [%o0 + L4_OFFSET] - stx %l5, [%o0 + L5_OFFSET] - stx %l6, [%o0 + L6_OFFSET] - stx %l7, [%o0 + L7_OFFSET] - - ! Now actually save ISR stack nesting prevention flag - stuw %g2, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET] - - stx %i0, [%o0 + I0_OFFSET] ! save the input registers - stx %i1, [%o0 + I1_OFFSET] - stx %i2, [%o0 + I2_OFFSET] - stx %i3, [%o0 + I3_OFFSET] - stx %i4, [%o0 + I4_OFFSET] - stx %i5, [%o0 + I5_OFFSET] - stx %i6, [%o0 + I6_FP_OFFSET] - stx %i7, [%o0 + I7_OFFSET] - - stx %o0, [%o0 + O0_OFFSET] ! save the output registers - stx %o1, [%o0 + O1_OFFSET] - stx %o2, [%o0 + O2_OFFSET] - stx %o3, [%o0 + O3_OFFSET] - stx %o4, [%o0 + O4_OFFSET] - stx %o5, [%o0 + O5_OFFSET] - stx %o6, [%o0 + O6_SP_OFFSET] - stx %o7, [%o0 + O7_OFFSET] ! o7 is the PC - -! rdpr %pil, %o2 -! stuw %o2, [%o0 + PIL_OFFSET] ! save pil - -! rdpr %pstate, %o2 -! stx %o2, [%o0 + PSTATE_OFFSET] ! save status register - - /* - * This is entered from _CPU_Context_restore with: - * o1 = context to restore -! * o2 = pstate - * - * NOTE: Flushing the register windows is necessary, but it adds - * an unpredictable (but bounded) overhead to context switching. - */ - -PUBLIC(_CPU_Context_restore_heir) - SYM(_CPU_Context_restore_heir): - - flushw - - - - ! skip g0 - ldx [%o1 + G1_OFFSET], %g1 ! restore the global registers - ldx [%o1 + G2_OFFSET], %g2 - ldx [%o1 + G3_OFFSET], %g3 - ldx [%o1 + G4_OFFSET], %g4 - ldx [%o1 + G5_OFFSET], %g5 - ldx [%o1 + G6_OFFSET], %g6 - ldx [%o1 + G7_OFFSET], %g7 - - ! Load thread specific ISR dispatch prevention flag - ldx [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2 - setx SYM(_CPU_ISR_Dispatch_disable), %o5, %o3 - ! Store it to memory later to use the cycles - - ldx [%o1 + L0_OFFSET], %l0 ! restore the local registers - ldx [%o1 + L1_OFFSET], %l1 - ldx [%o1 + L2_OFFSET], %l2 - ldx [%o1 + L3_OFFSET], %l3 - ldx [%o1 + L4_OFFSET], %l4 - ldx [%o1 + L5_OFFSET], %l5 - ldx [%o1 + L6_OFFSET], %l6 - ldx [%o1 + L7_OFFSET], %l7 - - ! Now restore thread specific ISR dispatch prevention flag - stuw %o2, [%o3] - - ldx [%o1 + I0_OFFSET], %i0 ! restore the input registers - ldx [%o1 + I1_OFFSET], %i1 - ldx [%o1 + I2_OFFSET], %i2 - ldx [%o1 + I3_OFFSET], %i3 - ldx [%o1 + I4_OFFSET], %i4 - ldx [%o1 + I5_OFFSET], %i5 - ldx [%o1 + I6_FP_OFFSET], %i6 - ldx [%o1 + I7_OFFSET], %i7 - - ldx [%o1 + O0_OFFSET], %o0 - ldx [%o1 + O2_OFFSET], %o2 ! restore the output registers - ldx [%o1 + O3_OFFSET], %o3 - ldx [%o1 + O4_OFFSET], %o4 - ldx [%o1 + O5_OFFSET], %o5 - ldx [%o1 + O6_SP_OFFSET], %o6 - ldx [%o1 + O7_OFFSET], %o7 ! PC - - ! on a hunch... we should be able to use some of the %o regs -! lduw [%o1 + PIL_OFFSET], %o2 -! wrpr %g0, %o2, %pil - -! ldx [%o1 + PSTATE_OFFSET], %o2 - - ! do o1 last to avoid destroying heir context pointer - ldx [%o1 + O1_OFFSET], %o1 ! overwrite heir pointer -! wrpr %g0, %o2, %pstate - - retl - nop - - /* - * void _CPU_Context_restore( - * Context_Control *new_context - * ) - * - * This routine is generally used only to perform restart self. - * - * NOTE: It is unnecessary to reload some registers. - */ - /* if _CPU_Context_restore_heir does not flushw, then do it here */ - .align 4 -PUBLIC(_CPU_Context_restore) - SYM(_CPU_Context_restore): - save %sp, -SPARC64_MINIMUM_STACK_FRAME_SIZE, %sp -! rdpr %pstate, %o2 - ba SYM(_CPU_Context_restore_heir) - mov %i0, %o1 ! in the delay slot - -/* end of file */ diff --git a/cpukit/score/cpu/sparc64/cpu.c b/cpukit/score/cpu/sparc64/cpu.c deleted file mode 100644 index 41abc58de4..0000000000 --- a/cpukit/score/cpu/sparc64/cpu.c +++ /dev/null @@ -1,359 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @brief SPARC64 CPU Dependent Source - */ - -/* - * COPYRIGHT (c) 1989-2007. On-Line Applications Research Corporation (OAR). - * - * This file is based on the SPARC cpu.c file. Modifications are made to - * provide support for the SPARC-v9. - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - -#if (SPARC_HAS_FPU == 1) -Context_Control_fp _CPU_Null_fp_context; -#endif - -volatile uint32_t _CPU_ISR_Dispatch_disable; - -/* - * _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: NONE - * - * Output Parameters: NONE - * - * NOTE: There is no need to save the pointer to the thread dispatch routine. - * The SPARC's assembly code can reference it directly with no problems. - */ - -void _CPU_Initialize(void) -{ -#if (SPARC_HAS_FPU == 1) - Context_Control_fp *pointer; - - /* - * This seems to be the most appropriate way to obtain an initial - * FP context on the SPARC. The NULL fp context is copied in to - * the task's FP context during Context_Initialize_fp. - */ - - pointer = &_CPU_Null_fp_context; - _CPU_Context_save_fp( &pointer ); - -#endif - - /* - * Since no tasks have been created yet and no interrupts have occurred, - * there is no way that the currently executing thread can have an - * interrupt stack frame on its stack. - */ - _CPU_ISR_Dispatch_disable = 0; -} - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -) -{ - uint64_t stack_high; /* highest "stack aligned" address */ - - /* - * On CPUs with stacks which grow down (i.e. SPARC), we build the stack - * based on the stack_high address. - */ - - stack_high = ((uint64_t)(stack_base) + size); - stack_high &= ~(CPU_STACK_ALIGNMENT - 1); - - /* - * See the README in this directory for a diagram of the stack. - */ - - the_context->o7 = ((uint64_t) entry_point) - 8; - the_context->o6_sp = stack_high - SPARC64_MINIMUM_STACK_FRAME_SIZE - STACK_BIAS; - the_context->i6_fp = 0; - - /* ABI uses g4 as segment register, make sure it is zeroed */ - the_context->g4 = 0; - - /* PSTATE used to be built here, but is no longer included in context */ - - /* - * Since THIS thread is being created, there is no way that THIS - * thread can have an interrupt stack frame on its stack. - */ - the_context->isr_dispatch_disable = 0; - - if ( tls_area != NULL ) { - void *tcb = _TLS_Initialize_area( tls_area ); - - the_context->g7 = (uintptr_t) tcb; - } -} - -/* - * This initializes the set of opcodes placed in each trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ - -/* 64-bit registers complicate this. Also, in sparc v9, - * each trap level gets its own set of global registers, but - * does not get its own dedicated register window. so we avoid - * using the local registers in the trap handler. - */ -const CPU_Trap_table_entry _CPU_Trap_slot_template = { - 0x89508000, /* rdpr %tstate, %g4 */ - 0x05000000, /* sethi %hh(_handler), %g2 */ - 0x8410a000, /* or %g2, %hm(_handler), %g2 */ - 0x8528b020, /* sllx %g2, 32, %g2 */ - 0x07000000, /* sethi %hi(_handler), %g3 */ - 0x8610c002, /* or %g3, %g2, %g3 */ - 0x81c0e000, /* jmp %g3 + %lo(_handler) */ - 0x84102000 /* mov _vector, %g2 */ -}; - - -/* - * _CPU_ISR_Get_level - * - * Input Parameters: NONE - * - * Output Parameters: - * returns the current interrupt level (PIL field of the PSR) - */ -uint32_t _CPU_ISR_Get_level( void ) -{ - uint32_t level; - - sparc64_get_interrupt_level( level ); - - return level; -} - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs the specified handler as a "raw" non-executive - * supported trap handler (a.k.a. interrupt service routine). - * - * Input Parameters: - * vector - trap table entry number plus synchronous - * vs. asynchronous information - * new_handler - address of the handler to be installed - * old_handler - pointer to an address of the handler previously installed - * - * Output Parameters: NONE - * *new_handler - address of the handler previously installed - * - * NOTE: - * - * On the SPARC v9, there are really only 512 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 511 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 512 through 1023 are assumed - * by the executive to be synchronous and to require that the return be to the - * trapping instruction. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * a synchronous trap. This will avoid the executive changing the return - * address. - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - CPU_ISR_raw_handler new_handler, - CPU_ISR_raw_handler *old_handler -) -{ - uint32_t real_vector; - CPU_Trap_table_entry *tba; - CPU_Trap_table_entry *slot; - uint64_t u64_tba; - uint64_t u64_handler; - - /* - * Get the "real" trap number for this vector ignoring the synchronous - * versus asynchronous indicator included with our vector numbers. - */ - - real_vector = SPARC_REAL_TRAP_NUMBER( vector ); - - /* - * Get the current base address of the trap table and calculate a pointer - * to the slot we are interested in. - */ - - sparc64_get_tba( u64_tba ); - -/* u32_tbr &= 0xfffff000; */ - u64_tba &= 0xffffffffffff8000; /* keep only trap base address */ - - tba = (CPU_Trap_table_entry *) u64_tba; - - /* use array indexing to fill in lower bits -- require - * CPU_Trap_table_entry to be full-sized. */ - slot = &tba[ real_vector ]; - - /* - * Get the address of the old_handler from the trap table. - * - * NOTE: The old_handler returned will be bogus if it does not follow - * the RTEMS model. - */ - - /* shift amount to shift of hi bits (31:10) */ -#define HI_BITS_SHIFT 10 - - /* shift amount of hm bits (41:32) */ -#define HM_BITS_SHIFT 32 - - /* shift amount of hh bits (63:42) */ -#define HH_BITS_SHIFT 42 - - /* We're only interested in bits 0-9 of the immediate field*/ -#define IMM_MASK 0x000003FF - - if ( slot->rdpr_tstate_g4 == _CPU_Trap_slot_template.rdpr_tstate_g4 ) { - u64_handler = - (((uint64_t)((slot->sethi_of_hh_handler_to_g2 << HI_BITS_SHIFT) | - (slot->or_g2_hm_handler_to_g2 & IMM_MASK))) << HM_BITS_SHIFT) | - ((slot->sethi_of_handler_to_g3 << HI_BITS_SHIFT) | - (slot->jmp_to_low_of_handler_plus_g3 & IMM_MASK)); - *old_handler = (CPU_ISR_raw_handler) u64_handler; - } else - *old_handler = 0; - - /* - * Copy the template to the slot and then fix it. - */ - - *slot = _CPU_Trap_slot_template; - - u64_handler = (uint64_t) new_handler; - - /* mask for extracting %hh */ -#define HH_BITS_MASK 0xFFFFFC0000000000 - - /* mask for extracting %hm */ -#define HM_BITS_MASK 0x000003FF00000000 - - /* mask for extracting %hi */ -#define HI_BITS_MASK 0x00000000FFFFFC00 - - /* mask for extracting %lo */ -#define LO_BITS_MASK 0x00000000000003FF - - - slot->mov_vector_g2 |= vector; - slot->sethi_of_hh_handler_to_g2 |= - (u64_handler & HH_BITS_MASK) >> HH_BITS_SHIFT; - slot->or_g2_hm_handler_to_g2 |= - (u64_handler & HM_BITS_MASK) >> HM_BITS_SHIFT; - slot->sethi_of_handler_to_g3 |= - (u64_handler & HI_BITS_MASK) >> HI_BITS_SHIFT; - slot->jmp_to_low_of_handler_plus_g3 |= (u64_handler & LO_BITS_MASK); - - /* need to flush icache after this !!! */ - - /* need to flush icache in case old trap handler is in cache */ - rtems_cache_invalidate_entire_instruction(); - -} - -/* - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * new_handler - replacement ISR for this vector number - * old_handler - pointer to former ISR for this vector number - * - * Output parameters: - * *old_handler - former ISR for this vector number - */ -void _CPU_ISR_install_vector( - uint32_t vector, - CPU_ISR_handler new_handler, - CPU_ISR_handler *old_handler -) -{ - uint64_t real_vector; - CPU_ISR_raw_handler ignored; - - /* - * Get the "real" trap number for this vector ignoring the synchronous - * versus asynchronous indicator included with our vector numbers. - */ - real_vector = SPARC_REAL_TRAP_NUMBER( vector ); - /* - * Return the previous ISR handler. - */ - - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * Install the wrapper so this ISR can be invoked properly. - */ - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ real_vector ] = new_handler; -} diff --git a/cpukit/score/cpu/sparc64/include/rtems/asm.h b/cpukit/score/cpu/sparc64/include/rtems/asm.h deleted file mode 100644 index 6983e3311d..0000000000 --- a/cpukit/score/cpu/sparc64/include/rtems/asm.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#ifndef __ASM__ -#define __ASM__ -#endif - -#include -#include - -/** - * @defgroup RTEMSScoreCPUSPARC64ASM SPARC64 Assembler Support - * - * @ingroup RTEMSScoreCPUSPARC64 - * - * @brief SPARC64 Assembler Support - * - * @{ - */ - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ -/* XXX The following ifdef magic fixes the problem but results in a warning */ -/* XXX when compiling assembly code. */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif - -/** @} */ diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h deleted file mode 100644 index a0f11a9d7a..0000000000 --- a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h +++ /dev/null @@ -1,946 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @brief SPARC64 CPU Department Source - * - * This include file contains information pertaining to the port of - * the executive to the SPARC64 processor. - */ - -/* - * - * - * COPYRIGHT (c) 1989-2006. On-Line Applications Research Corporation (OAR). - * - * This file is based on the SPARC cpu.h file. Modifications are made - * to support the SPARC64 processor. - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * SPARC Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the FLOATING_POINT task attribute is supported. - * If FALSE, then the FLOATING_POINT task attribute is ignored. - */ - -#if ( SPARC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks FLOATING_POINT tasks implicitly? - * - * If TRUE, then the FLOATING_POINT task attribute is assumed. - * If FALSE, then the FLOATING_POINT task attribute is followed. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * The stack grows to lower addresses on the SPARC. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 - -/* - * The following is the variable attribute used to force alignment - * of critical data structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The SPARC does not appear to have particularly strict alignment - * requirements. This value (16) was chosen to take advantages of caches. - * - * SPARC 64 requirements on floating point alignment is at least 8, - * and is 16 if quad-word fp instructions are available (e.g. LDQF). - */ - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( 16 ) - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The SPARC v9 has 16 interrupt levels in the PIL field of the PSR. - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000F - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * This structure represents the organization of the minimum stack frame - * for the SPARC. More framing information is required in certain situaions - * such as when there are a large number of out parameters or when the callee - * must save floating point registers. - */ - -#ifndef ASM - -typedef struct { - uint64_t l0; - uint64_t l1; - uint64_t l2; - uint64_t l3; - uint64_t l4; - uint64_t l5; - uint64_t l6; - uint64_t l7; - uint64_t i0; - uint64_t i1; - uint64_t i2; - uint64_t i3; - uint64_t i4; - uint64_t i5; - uint64_t i6_fp; - uint64_t i7; - void *structure_return_address; - /* - * The following are for the callee to save the register arguments in - * should this be necessary. - */ - uint64_t saved_arg0; - uint64_t saved_arg1; - uint64_t saved_arg2; - uint64_t saved_arg3; - uint64_t saved_arg4; - uint64_t saved_arg5; - uint64_t pad0; -} SPARC64_Minimum_stack_frame; - -#endif /* !ASM */ - -#define CPU_STACK_FRAME_L0_OFFSET 0x00 -#define CPU_STACK_FRAME_L1_OFFSET 0x08 -#define CPU_STACK_FRAME_L2_OFFSET 0x10 -#define CPU_STACK_FRAME_L3_OFFSET 0x18 -#define CPU_STACK_FRAME_L4_OFFSET 0x20 -#define CPU_STACK_FRAME_L5_OFFSET 0x28 -#define CPU_STACK_FRAME_L6_OFFSET 0x30 -#define CPU_STACK_FRAME_L7_OFFSET 0x38 -#define CPU_STACK_FRAME_I0_OFFSET 0x40 -#define CPU_STACK_FRAME_I1_OFFSET 0x48 -#define CPU_STACK_FRAME_I2_OFFSET 0x50 -#define CPU_STACK_FRAME_I3_OFFSET 0x58 -#define CPU_STACK_FRAME_I4_OFFSET 0x60 -#define CPU_STACK_FRAME_I5_OFFSET 0x68 -#define CPU_STACK_FRAME_I6_FP_OFFSET 0x70 -#define CPU_STACK_FRAME_I7_OFFSET 0x78 -#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x80 -#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x88 -#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x90 -#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x98 -#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0xA0 -#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0xA8 -#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0 -#define CPU_STACK_FRAME_PAD0_OFFSET 0xB8 - -#define SPARC64_MINIMUM_STACK_FRAME_SIZE 0xC0 - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On the SPARC, we are relatively conservative in that we save most - * of the CPU state in the context area. The ET (enable trap) bit and - * the CWP (current window pointer) fields of the PSR are considered - * system wide resources and are not maintained on a per-thread basis. - */ - -#ifndef ASM - -typedef struct { - uint64_t g1; - uint64_t g2; - uint64_t g3; - uint64_t g4; - uint64_t g5; - uint64_t g6; - uint64_t g7; - - uint64_t l0; - uint64_t l1; - uint64_t l2; - uint64_t l3; - uint64_t l4; - uint64_t l5; - uint64_t l6; - uint64_t l7; - - uint64_t i0; - uint64_t i1; - uint64_t i2; - uint64_t i3; - uint64_t i4; - uint64_t i5; - uint64_t i6_fp; - uint64_t i7; - - uint64_t o0; - uint64_t o1; - uint64_t o2; - uint64_t o3; - uint64_t o4; - uint64_t o5; - uint64_t o6_sp; - uint64_t o7; - - uint32_t isr_dispatch_disable; - uint32_t pad; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->o6_sp - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control for assembly routines. - */ - -#define G1_OFFSET 0x00 -#define G2_OFFSET 0x08 -#define G3_OFFSET 0x10 -#define G4_OFFSET 0x18 -#define G5_OFFSET 0x20 -#define G6_OFFSET 0x28 -#define G7_OFFSET 0x30 - -#define L0_OFFSET 0x38 -#define L1_OFFSET 0x40 -#define L2_OFFSET 0x48 -#define L3_OFFSET 0x50 -#define L4_OFFSET 0x58 -#define L5_OFFSET 0x60 -#define L6_OFFSET 0x68 -#define L7_OFFSET 0x70 - -#define I0_OFFSET 0x78 -#define I1_OFFSET 0x80 -#define I2_OFFSET 0x88 -#define I3_OFFSET 0x90 -#define I4_OFFSET 0x98 -#define I5_OFFSET 0xA0 -#define I6_FP_OFFSET 0xA8 -#define I7_OFFSET 0xB0 - -#define O0_OFFSET 0xB8 -#define O1_OFFSET 0xC0 -#define O2_OFFSET 0xC8 -#define O3_OFFSET 0xD0 -#define O4_OFFSET 0xD8 -#define O5_OFFSET 0xE0 -#define O6_SP_OFFSET 0xE8 -#define O7_OFFSET 0xF0 - -#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8 -#define ISR_PAD_OFFSET 0xFC - -/* - * The floating point context area. - */ - -#ifndef ASM - -typedef struct { - double f0; /* f0-f1 */ - double f2; /* f2-f3 */ - double f4; /* f4-f5 */ - double f6; /* f6-f7 */ - double f8; /* f8-f9 */ - double f10; /* f10-f11 */ - double f12; /* f12-f13 */ - double f14; /* f14-f15 */ - double f16; /* f16-f17 */ - double f18; /* f18-f19 */ - double f20; /* f20-f21 */ - double f22; /* f22-f23 */ - double f24; /* f24-f25 */ - double f26; /* f26-f27 */ - double f28; /* f28-f29 */ - double f30; /* f30-f31 */ - double f32; - double f34; - double f36; - double f38; - double f40; - double f42; - double f44; - double f46; - double f48; - double f50; - double f52; - double f54; - double f56; - double f58; - double f60; - double f62; - uint64_t fsr; -} Context_Control_fp; - -#endif /* !ASM */ - -/* - * Offsets of fields with Context_Control_fp for assembly routines. - */ - -#define FO_OFFSET 0x00 -#define F2_OFFSET 0x08 -#define F4_OFFSET 0x10 -#define F6_OFFSET 0x18 -#define F8_OFFSET 0x20 -#define F1O_OFFSET 0x28 -#define F12_OFFSET 0x30 -#define F14_OFFSET 0x38 -#define F16_OFFSET 0x40 -#define F18_OFFSET 0x48 -#define F2O_OFFSET 0x50 -#define F22_OFFSET 0x58 -#define F24_OFFSET 0x60 -#define F26_OFFSET 0x68 -#define F28_OFFSET 0x70 -#define F3O_OFFSET 0x78 -#define F32_OFFSET 0x80 -#define F34_OFFSET 0x88 -#define F36_OFFSET 0x90 -#define F38_OFFSET 0x98 -#define F4O_OFFSET 0xA0 -#define F42_OFFSET 0xA8 -#define F44_OFFSET 0xB0 -#define F46_OFFSET 0xB8 -#define F48_OFFSET 0xC0 -#define F5O_OFFSET 0xC8 -#define F52_OFFSET 0xD0 -#define F54_OFFSET 0xD8 -#define F56_OFFSET 0xE0 -#define F58_OFFSET 0xE8 -#define F6O_OFFSET 0xF0 -#define F62_OFFSET 0xF8 -#define FSR_OFFSET 0x100 - -#define CONTEXT_CONTROL_FP_SIZE 0x108 - -#ifndef ASM - -/* - * Context saved on stack for an interrupt. - * - * NOTE: The tstate, tpc, and tnpc are saved in this structure - * to allow resetting the TL while still being able to return - * from a trap later. The PIL is saved because - * if this is an external interrupt, we will mask lower - * priority interrupts until finishing. Even though the y register - * is deprecated, gcc still uses it. - */ - -typedef struct { - SPARC64_Minimum_stack_frame Stack_frame; - uint64_t tstate; - uint64_t tpc; - uint64_t tnpc; - uint64_t pil; - uint64_t y; - uint64_t g1; - uint64_t g2; - uint64_t g3; - uint64_t g4; - uint64_t g5; - uint64_t g6; - uint64_t g7; - uint64_t o0; - uint64_t o1; - uint64_t o2; - uint64_t o3; - uint64_t o4; - uint64_t o5; - uint64_t o6_sp; - uint64_t o7; - uint64_t tvec; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Offsets of fields with CPU_Interrupt_frame for assembly routines. - */ - -#define ISF_TSTATE_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x00 -#define ISF_TPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x08 -#define ISF_TNPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x10 -#define ISF_PIL_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x18 -#define ISF_Y_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x20 -#define ISF_G1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x28 -#define ISF_G2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x30 -#define ISF_G3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x38 -#define ISF_G4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x40 -#define ISF_G5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x48 -#define ISF_G6_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x50 -#define ISF_G7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x58 -#define ISF_O0_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x60 -#define ISF_O1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x68 -#define ISF_O2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x70 -#define ISF_O3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x78 -#define ISF_O4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x80 -#define ISF_O5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x88 -#define ISF_O6_SP_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x90 -#define ISF_O7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x98 -#define ISF_TVEC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA0 - -#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA8 -#ifndef ASM -/* - * This variable is contains the initialize context for the FP unit. - * It is filled in by _CPU_Initialize and copied into the task's FP - * context area during _CPU_Context_Initialize. - */ - -extern Context_Control_fp _CPU_Null_fp_context; - -/* - * This flag is context switched with each thread. It indicates - * that THIS thread has an interrupt stack frame on its stack. - * By using this flag, we can avoid nesting more interrupt dispatching - * attempts on a previously interrupted thread's stack. - */ - -extern volatile uint32_t _CPU_ISR_Dispatch_disable; - -/* - * The following type defines an entry in the SPARC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ -/* For SPARC V9, we must use 6 of these instructions to perform a long - * jump, because the _handler value is now 64-bits. We also need to store - * temporary values in the global register set at this trap level. Because - * the handler runs at TL > 0 with GL > 0, it should be OK to use g2 and g3 - * to pass parameters to ISR_Handler. - * - * The instruction sequence is now more like: - * rdpr %tstate, %g4 - * setx _handler, %g2, %g3 - * jmp %g3+0 - * mov _vector, %g2 - */ -typedef struct { - uint32_t rdpr_tstate_g4; /* rdpr %tstate, %g4 */ - uint32_t sethi_of_hh_handler_to_g2; /* sethi %hh(_handler), %g2 */ - uint32_t or_g2_hm_handler_to_g2; /* or %l3, %hm(_handler), %g2 */ - uint32_t sllx_g2_by_32_to_g2; /* sllx %g2, 32, %g2 */ - uint32_t sethi_of_handler_to_g3; /* sethi %hi(_handler), %g3 */ - uint32_t or_g3_g2_to_g3; /* or %g3, %g2, %g3 */ - uint32_t jmp_to_low_of_handler_plus_g3; /* jmp %g3 + %lo(_handler) */ - uint32_t mov_vector_g2; /* mov _vector, %g2 */ -} CPU_Trap_table_entry; - -/* - * This is the set of opcodes for the instructions loaded into a trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ - -extern const CPU_Trap_table_entry _CPU_Trap_slot_template; - -/* - * The size of the floating point context area. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by the executive. - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ -/* On SPARC v9, there are 512 vectors. The same philosophy applies to - * vector installation and use, we just provide a larger table. - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 512 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023 - -#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x200 -#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) -#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 512 ) - -#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 512) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * This appears to be a fairly generous number for the SPARC since - * represents a call depth of about 20 routines based on the minimum - * stack frame. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 8 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * On the SPARC, this is required for double word loads and stores. - * - * Note: quad-word loads/stores need alignment of 16, but currently supported - * architectures do not provide HW implemented quad-word operations. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * The alignment restrictions for the SPARC are not that strict but this - * should unsure that the stack is always sufficiently alignment that the - * window overflow, underflow, and flush routines can use double word loads - * and stores. - */ - -#define CPU_STACK_ALIGNMENT 16 - -#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES - -#ifndef ASM - -/* - * ISR handler macros - */ - -/* - * Disable all interrupts for a critical section. The previous - * level is returned in _level. - */ - - #define _CPU_ISR_Disable( _level ) \ - (_level) = sparc_disable_interrupts() - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of a critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - sparc_enable_interrupts( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - sparc_flash_interrupts( _level ) - -static inline bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & SPARC_PSTATE_IE_MASK ) != 0; -} - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. - */ - -#define _CPU_ISR_Set_level( _newlevel ) \ - sparc_enable_interrupts( _newlevel) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* - * This macro is invoked from _Thread_Handler to do whatever CPU - * specific magic is required that must be done in the context of - * the thread when it starts. - * - * On the SPARC, this is setting the frame pointer so GDB is happy. - * Make GDB stop unwinding at _Thread_Handler, previous register window - * Frame pointer is 0 and calling address must be a function with starting - * with a SAVE instruction. If return address is leaf-function (no SAVE) - * GDB will not look at prev reg window fp. - * - * _Thread_Handler is known to start with SAVE. - */ - -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ - } while (0) - -/* - * This routine is responsible for somehow restarting the currently - * executing task. - * - * On the SPARC, this is is relatively painless but requires a small - * amount of wrapper code before using the regular restore code in - * of the context switch. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * This routine initializes the FP context area passed to it to. - * - * The SPARC allows us to use the simple initialization model - * in which an "initial" FP context was saved into _CPU_Null_fp_context - * at CPU initialization and it is simply copied into the destination - * context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) - -/* end of Context handler macros */ - -#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE - -/* Bitfield handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 0 ) -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#else -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Bitfield handler macros */ - -/* Priority handler handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 1 ) -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -typedef void ( *CPU_ISR_raw_handler )( void ); - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - CPU_ISR_raw_handler new_handler, - CPU_ISR_raw_handler *old_handler -); - -typedef void ( *CPU_ISR_handler )( uint32_t ); - -void _CPU_ISR_install_vector( - uint32_t vector, - CPU_ISR_handler new_handler, - CPU_ISR_handler *old_handler -); - -RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. - */ - -RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* - * CPU_swap_u32 - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit - * entity as shown below is not any more efficient on the SPARC. - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * It is not obvious how the SPARC can do significantly better than the - * generic code. gcc 2.7.0 only generates about 12 instructions for the - * following code at optimization level four (i.e. -O4). - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -uint32_t _CPU_Counter_frequency( void ); - -CPU_Counter_ticks _CPU_Counter_read( void ); - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h deleted file mode 100644 index 36f4ff040f..0000000000 --- a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH & Co. KG - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -/** - * @defgroup RTEMSScoreCPUSPARC64 SPARC64 - * - * @ingroup RTEMSScoreCPU - * - * @brief SPARC64 Architecture Support - * - * @{ - */ - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - (void) pattern; - - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - (void) pattern; - - while (1) { - /* TODO */ - } -} - -static inline void _CPU_Instruction_illegal( void ) -{ - __asm__ volatile ( "unimp" ); -} - -static inline void _CPU_Instruction_no_operation( void ) -{ - __asm__ volatile ( "nop" ); -} - -static inline void _CPU_Use_thread_local_storage( - const Context_Control *context -) -{ - (void) context; -} - -static inline void *_CPU_Get_TLS_thread_pointer( - const Context_Control *context -) -{ - (void) context; - return NULL; -} - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/sparc64.h b/cpukit/score/cpu/sparc64/include/rtems/score/sparc64.h deleted file mode 100644 index 14020e75d0..0000000000 --- a/cpukit/score/cpu/sparc64/include/rtems/score/sparc64.h +++ /dev/null @@ -1,361 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @brief Information Required to Build RTEMS for a Particular Member - * of the SPARC Family - * - * This include file contains information pertaining to the SPARC - * processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. On-Line Applications Research Corporation (OAR). - * - * This file is based on the SPARC sparc.h file. Modifications are made - * to support the SPARC64 processor. - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_SPARC_H -#define _RTEMS_SCORE_SPARC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "sparc" family. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * Currently recognized feature flags: - * - * + SPARC_HAS_FPU - * 0 - no HW FPU - * 1 - has HW FPU (assumed to be compatible w/90C602) - * - * + SPARC_HAS_BITSCAN - * 0 - does not have scan instructions - * 1 - has scan instruction (not currently implemented) - * - * + SPARC_NUMBER_OF_REGISTER_WINDOWS - * 8 is the most common number supported by SPARC implementations. - * SPARC_PSR_CWP_MASK is derived from this value. - */ - -/* - * Some higher end SPARCs have a bitscan instructions. It would - * be nice to take advantage of them. Right now, there is no - * port to a CPU model with this feature and no (untested) code - * that is based on this feature flag. - */ - -#define SPARC_HAS_BITSCAN 0 - -/* - * This should be OK until a port to a higher end SPARC processor - * is made that has more than 8 register windows. If this cannot - * be determined based on multilib settings (v7/v8/v9), then the - * cpu_asm.S code that depends on this will have to move to libcpu. - * - * SPARC v9 supports from 3 to 32 register windows. - * N_REG_WINDOWS = 8 on UltraSPARC T1 (impl. dep. #2-V8). - */ - -#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 - -/* - * This should be determined based on some soft float derived - * cpp predefine but gcc does not currently give us that information. - */ - - -#if defined(_SOFT_FLOAT) -#define SPARC_HAS_FPU 0 -#else -#define SPARC_HAS_FPU 1 -#endif - -#if SPARC_HAS_FPU -#define CPU_MODEL_NAME "w/FPU" -#else -#define CPU_MODEL_NAME "w/soft-float" -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "SPARC" - -/* - * Miscellaneous constants - */ - -/* - * The PSR is deprecated and deleted. - * - * The following registers represent fields of the PSR: - * PIL - Processor Interrupt Level register - * CWP - Current Window Pointer register - * VER - Version register - * CCR - Condition Codes Register - * PSTATE - Processor State register - */ - -/* - * PSTATE masks and starting bit positions - * - * NOTE: Reserved bits are ignored. - */ - -#define SPARC_PSTATE_AG_MASK 0x00000001 /* bit 0 */ -#define SPARC_PSTATE_IE_MASK 0x00000002 /* bit 1 */ -#define SPARC_PSTATE_PRIV_MASK 0x00000004 /* bit 2 */ -#define SPARC_PSTATE_AM_MASK 0x00000008 /* bit 3 */ -#define SPARC_PSTATE_PEF_MASK 0x00000010 /* bit 4 */ -#define SPARC_PSTATE_MM_MASK 0x00000040 /* bit 6 */ -#define SPARC_PSTATE_TLE_MASK 0x00000100 /* bit 8 */ -#define SPARC_PSTATE_CLE_MASK 0x00000200 /* bit 9 */ - -#define SPARC_PSTATE_AG_BIT_POSITION 0 /* bit 0 */ -#define SPARC_PSTATE_IE_BIT_POSITION 1 /* bit 1 */ -#define SPARC_PSTATE_PRIV_BIT_POSITION 2 /* bit 2 */ -#define SPARC_PSTATE_AM_BIT_POSITION 3 /* bit 3 */ -#define SPARC_PSTATE_PEF_BIT_POSITION 4 /* bit 4 */ -#define SPARC_PSTATE_MM_BIT_POSITION 6 /* bit 6 */ -#define SPARC_PSTATE_TLE_BIT_POSITION 8 /* bit 8 */ -#define SPARC_PSTATE_CLE_BIT_POSITION 9 /* bit 9 */ - -#define SPARC_FPRS_FEF_MASK 0x0100 /* bit 2 */ -#define SPARC_FPRS_FEF_BIT_POSITION 2 /* bit 2 */ - -#define SPARC_TSTATE_IE_MASK 0x00000200 /* bit 9 */ - -#define SPARC_SOFTINT_TM_MASK 0x00000001 /* bit 0 */ -#define SPARC_SOFTINT_SM_MASK 0x00010000 /* bit 16 */ -#define SPARC_SOFTINT_TM_BIT_POSITION 1 /* bit 0 */ -#define SPARC_SOFTINT_SM_BIT_POSITION 17 /* bit 16 */ - -#define STACK_BIAS (2047) - -#ifdef ASM - -/* - * To enable the FPU we need to set both PSTATE.pef and FPRS.fef - */ - -#define sparc64_enable_FPU(rtmp1) \ - rdpr %pstate, rtmp1; \ - or rtmp1, SPARC_PSTATE_PEF_MASK, rtmp1; \ - wrpr %g0, rtmp1, %pstate; \ - rd %fprs, rtmp1; \ - or rtmp1, SPARC_FPRS_FEF_MASK, rtmp1; \ - wr %g0, rtmp1, %fprs - - -#endif - -#ifndef ASM - -/* - * Standard nop - */ - -#define nop() \ - do { \ - __asm__ volatile ( "nop" ); \ - } while ( 0 ) - -/* - * Get and set the pstate - */ - -#define sparc64_get_pstate( _pstate ) \ - do { \ - (_pstate) = 0; \ - __asm__ volatile( "rdpr %%pstate, %0" : "=r" (_pstate) : "0" (_pstate) ); \ - } while ( 0 ) - -#define sparc64_set_pstate( _pstate ) \ - do { \ - __asm__ volatile ( \ - "wrpr %%g0, %0, %%pstate " : "=r" ((_pstate)) : "0" ((_pstate)) ); \ - } while ( 0 ) - -/* - * Get and set the PIL - */ - -#define sparc64_get_pil( _pil ) \ - do { \ - (_pil) = 0; \ - __asm__ volatile( "rdpr %%pil, %0" : "=r" (_pil) : "0" (_pil) ); \ - } while ( 0 ) - -#define sparc64_set_pil( _pil ) \ - do { \ - __asm__ volatile ( "wrpr %%g0, %0, %%pil " : "=r" ((_pil)) : "0" ((_pil)) ); \ - } while ( 0 ) - - -/* - * Get and set the TBA - */ - -#define sparc64_get_tba( _tba ) \ - do { \ - (_tba) = 0; /* to avoid unitialized warnings */ \ - __asm__ volatile( "rdpr %%tba, %0" : "=r" (_tba) : "0" (_tba) ); \ - } while ( 0 ) - -#define sparc64_set_tba( _tba ) \ - do { \ - __asm__ volatile( "wrpr %%g0, %0, %%tba" : "=r" (_tba) : "0" (_tba) ); \ - } while ( 0 ) - -/* - * Get and set the TL (trap level) - */ - -#define sparc64_get_tl( _tl ) \ - do { \ - (_tl) = 0; /* to avoid unitialized warnings */ \ - __asm__ volatile( "rdpr %%tl, %0" : "=r" (_tl) : "0" (_tl) ); \ - } while ( 0 ) - -#define sparc64_set_tl( _tl ) \ - do { \ - __asm__ volatile( "wrpr %%g0, %0, %%tl" : "=r" (_tl) : "0" (_tl) ); \ - } while ( 0 ) - - -/* - * read the stick register - * - * Note: - * stick asr=24, mnemonic=stick - * Note: stick does not appear to be a valid ASR for US3, although it is - * implemented in US3i. - */ -#define sparc64_read_stick( _stick ) \ - do { \ - (_stick) = 0; \ - __asm__ volatile( "rd %%stick, %0" : "=r" (_stick) : "0" (_stick) ); \ - } while ( 0 ) - -/* - * write the stick_cmpr register - * - * Note: - * stick_cmpr asr=25, mnemonic=stick_cmpr - * Note: stick_cmpr does not appear to be a valid ASR for US3, although it is - * implemented in US3i. - */ -#define sparc64_write_stick_cmpr( _stick_cmpr ) \ - do { \ - __asm__ volatile( "wr %%g0, %0, %%stick_cmpr" : "=r" (_stick_cmpr) \ - : "0" (_stick_cmpr) ); \ - } while ( 0 ) - -/* - * read the Tick register - */ -#define sparc64_read_tick( _tick ) \ - do { \ - (_tick) = 0; \ - __asm__ volatile( "rd %%tick, %0" : "=r" (_tick) : "0" (_tick) ); \ - } while ( 0 ) - -/* - * write the tick_cmpr register - */ -#define sparc64_write_tick_cmpr( _tick_cmpr ) \ - do { \ - __asm__ volatile( "wr %%g0, %0, %%tick_cmpr" : "=r" (_tick_cmpr) \ - : "0" (_tick_cmpr) ); \ - } while ( 0 ) - -/* - * Clear the softint register. - * - * sun4u and sun4v: softint_clr asr = 21, with mnemonic clear_softint - */ -#define sparc64_clear_interrupt_bits( _bit_mask ) \ - do { \ - __asm__ volatile( "wr %%g0, %0, %%clear_softint" : "=r" (_bit_mask) \ - : "0" (_bit_mask)); \ - } while ( 0 ) - -/************* DEPRECATED ****************/ -/* Note: Although the y register is deprecated, gcc still uses it */ -/* - * Get and set the Y - */ - -#define sparc_get_y( _y ) \ - do { \ - __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -#define sparc_set_y( _y ) \ - do { \ - __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -/************* /DEPRECATED ****************/ - -/* - * Manipulate the interrupt level in the pstate - */ - -uint32_t sparc_disable_interrupts(void); -void sparc_enable_interrupts(uint32_t); - -#define sparc_flash_interrupts( _level ) \ - do { \ - uint32_t _ignored; \ - \ - sparc_enable_interrupts( (_level) ); \ - _ignored = sparc_disable_interrupts(); \ - (void) _ignored; \ - } while ( 0 ) - -#define sparc64_get_interrupt_level( _level ) \ - do { \ - _level = 0; \ - sparc64_get_pil( _level ); \ - } while ( 0 ) - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_SPARC_H */ diff --git a/cpukit/score/cpu/sparc64/interrupt.S b/cpukit/score/cpu/sparc64/interrupt.S deleted file mode 100644 index 70ae679fd2..0000000000 --- a/cpukit/score/cpu/sparc64/interrupt.S +++ /dev/null @@ -1,561 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* cpu_asm.s - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language. - * - * COPYRIGHT (c) 1989-2007. On-Line Applications Research Corporation (OAR). - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - - -/* - * The assembler needs to be told that we know what to do with - * the global registers. - */ -.register %g2, #scratch -.register %g3, #scratch -.register %g6, #scratch -.register %g7, #scratch - - - /* - * void _ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * We enter this handler from the 8 instructions in the trap table with - * the following registers assumed to be set as shown: - * - * g4 = tstate (old l0) - * g2 = trap type (vector) (old l3) - * - * NOTE: By an executive defined convention: - * if trap type is between 0 and 511 it is an asynchronous trap - * if trap type is between 512 and 1023 it is an asynchonous trap - */ - - .align 4 -PUBLIC(_ISR_Handler) - SYM(_ISR_Handler): - - /* - * The ISR is called at TL = 1. - * On sun4u we use the alternate globals set. - * - * On entry: - * g4 = tstate (from trap table) - * g2 = trap vector # - * - * In either case, note that trap handlers share a register window with - * the interrupted context, unless we explicitly enter a new window. This - * differs from Sparc v8, in which a dedicated register window is saved - * for trap handling. This means we have to avoid overwriting any registers - * that we don't save. - * - */ - - - /* - * save some or all context on stack - */ - - /* - * Save the state of the interrupted task -- especially the global - * registers -- in the Interrupt Stack Frame. Note that the ISF - * includes a regular minimum stack frame which will be used if - * needed by register window overflow and underflow handlers. - * - * This is slightly wasteful, since the stack already has the window - * overflow space reserved, but there is no obvious way to ensure - * we can store the interrupted state and still handle window - * spill/fill correctly, since there is no room for the ISF. - * - */ - - /* this is for debugging purposes, make sure that TL = 1, otherwise - * things might get dicey */ - rdpr %tl, %g1 - cmp %g1, 1 - be 1f - nop - - 0: ba 0b - nop - - 1: - /* first store the sp of the interrupted task temporarily in g1 */ - mov %sp, %g1 - - sub %sp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp - ! make space for Stack_Frame||ISF - - /* save tstate, tpc, tnpc, pil */ - stx %g4, [%sp + STACK_BIAS + ISF_TSTATE_OFFSET] - rdpr %pil, %g3 - rdpr %tpc, %g4 - rdpr %tnpc, %g5 - stx %g3, [%sp + STACK_BIAS + ISF_PIL_OFFSET] - stx %g4, [%sp + STACK_BIAS + ISF_TPC_OFFSET] - stx %g5, [%sp + STACK_BIAS + ISF_TNPC_OFFSET] - stx %g2, [%sp + STACK_BIAS + ISF_TVEC_OFFSET] - - rd %y, %g4 ! save y - stx %g4, [%sp + STACK_BIAS + ISF_Y_OFFSET] - - ! save interrupted frame's output regs - stx %o0, [%sp + STACK_BIAS + ISF_O0_OFFSET] ! save o0 - stx %o1, [%sp + STACK_BIAS + ISF_O1_OFFSET] ! save o1 - stx %o2, [%sp + STACK_BIAS + ISF_O2_OFFSET] ! save o2 - stx %o3, [%sp + STACK_BIAS + ISF_O3_OFFSET] ! save o3 - stx %o4, [%sp + STACK_BIAS + ISF_O4_OFFSET] ! save o4 - stx %o5, [%sp + STACK_BIAS + ISF_O5_OFFSET] ! save o5 - stx %g1, [%sp + STACK_BIAS + ISF_O6_SP_OFFSET] ! save o6/sp - stx %o7, [%sp + STACK_BIAS + ISF_O7_OFFSET] ! save o7 - - mov %g1, %o5 ! hold the old sp here for now - mov %g2, %o1 ! we'll need trap # later - - /* switch to TL[0] */ - wrpr %g0, 0, %tl - - /* switch to normal globals */ -#if defined (SUN4U) - /* the assignment to pstate below will mask out the AG bit */ -#elif defined (SUN4V) - wrpr %g0, 0, %gl -#endif - /* get pstate to known state */ - wrpr %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK, %pstate - - ! save globals - stx %g1, [%sp + STACK_BIAS + ISF_G1_OFFSET] ! save g1 - stx %g2, [%sp + STACK_BIAS + ISF_G2_OFFSET] ! save g2 - stx %g3, [%sp + STACK_BIAS + ISF_G3_OFFSET] ! save g3 - stx %g4, [%sp + STACK_BIAS + ISF_G4_OFFSET] ! save g4 - stx %g5, [%sp + STACK_BIAS + ISF_G5_OFFSET] ! save g5 - stx %g6, [%sp + STACK_BIAS + ISF_G6_OFFSET] ! save g6 - stx %g7, [%sp + STACK_BIAS + ISF_G7_OFFSET] ! save g7 - - - mov %o1, %g2 ! get the trap # - mov %o5, %g7 ! store the interrupted %sp (preserve) - mov %sp, %o1 ! 2nd arg to ISR Handler = address of ISF - add %o1, STACK_BIAS, %o1 ! need to adjust for stack bias, 2nd arg = ISF - - /* - * Increment ISR nest level and Thread dispatch disable level. - * - * Register usage for this section: (note, these are used later) - * - * g3 = _Thread_Dispatch_disable_level pointer - * g5 = _Thread_Dispatch_disable_level value (uint32_t) - * g6 = _ISR_Nest_level pointer - * g4 = _ISR_Nest_level value (uint32_t) - * o5 = temp - * - * NOTE: It is assumed that g6 - g7 will be preserved until the ISR - * nest and thread dispatch disable levels are unnested. - */ - - setx THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3 - lduw [%g3], %g5 - setx ISR_NEST_LEVEL, %o5, %g6 - lduw [%g6], %g4 - - add %g5, 1, %g5 - stuw %g5, [%g3] - - add %g4, 1, %g4 - stuw %g4, [%g6] - - /* - * If ISR nest level was zero (now 1), then switch stack. - */ - - subcc %g4, 1, %g4 ! outermost interrupt handler? - bnz dont_switch_stacks ! No, then do not switch stacks - - setx SYM(INTERRUPT_STACK_HIGH), %o5, %g1 - ldx [%g1], %sp - - /* - * Adjust the stack for the stack bias - */ - sub %sp, STACK_BIAS, %sp - - /* - * Make sure we have a place on the stack for the window overflow - * trap handler to write into. At this point it is safe to - * enable traps again. - */ - - sub %sp, SPARC64_MINIMUM_STACK_FRAME_SIZE, %sp - - dont_switch_stacks: - /* - * Check if we have an external interrupt (trap 0x41 - 0x4f). If so, - * set the PIL to mask off interrupts with lower priority. - * - * The original PIL is not modified since it will be restored - * when the interrupt handler returns. - */ - - and %g2, 0x0ff, %g1 ! is bottom byte of vector number [0x41,0x4f]? - - subcc %g1, 0x41, %g0 - bl dont_fix_pil - subcc %g1, 0x4f, %g0 - bg dont_fix_pil - nop - wrpr %g0, %g1, %pil - - dont_fix_pil: - /* We need to be careful about enabling traps here. - * - * We already stored off the tstate, tpc, and tnpc, and switched to - * TL = 0, so it should be safe. - */ - - /* zero out g4 so that ofw calls work */ - mov %g0, %g4 - - ! **** ENABLE TRAPS **** - wrpr %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK | \ - SPARC_PSTATE_IE_MASK, %pstate - - /* - * Vector to user's handler. - * - * NOTE: TBR may no longer have vector number in it since - * we just enabled traps. It is definitely in g2. - */ - setx SYM(_ISR_Vector_table), %o5, %g1 - and %g2, 0x1FF, %o5 ! remove synchronous trap indicator - sll %o5, 3, %o5 ! o5 = offset into table - ldx [%g1 + %o5], %g1 ! g1 = _ISR_Vector_table[ vector ] - - - ! o1 = 2nd arg = address of the ISF - ! WAS LOADED WHEN ISF WAS SAVED!!! - mov %g2, %o0 ! o0 = 1st arg = vector number - call %g1, 0 - nop ! delay slot - - /* - * Redisable traps so we can finish up the interrupt processing. - * This is a conservative place to do this. - */ - ! **** DISABLE TRAPS **** - wrpr %g0, SPARC_PSTATE_PRIV_MASK, %pstate - - /* - * We may safely use any of the %o and %g registers, because - * we saved them earlier (and any other interrupt that uses - * them will also save them). Right now, the state of those - * registers are as follows: - * %o registers: unknown (user's handler may have destroyed) - * %g1,g4,g5: scratch - * %g2: unknown: was trap vector - * %g3: uknown: was _Thread_Dispatch_Disable_level pointer - * %g6: _ISR_Nest_level - * %g7: interrupted task's sp - */ - - /* - * Increment ISR nest level and Thread dispatch disable level. - * - * Register usage for this section: (note: as used above) - * - * g3 = _Thread_Dispatch_disable_level pointer - * g5 = _Thread_Dispatch_disable_level value - * g6 = _ISR_Nest_level pointer - * g4 = _ISR_Nest_level value - * o5 = temp - */ - - /* We have to re-load the values from memory, because there are - * not enough registers that we know will be preserved across the - * user's handler. If this is a problem, we can create a register - * window for _ISR_Handler. - */ - - setx THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3 - lduw [%g3],%g5 - lduw [%g6],%g4 - sub %g5, 1, %g5 - stuw %g5, [%g3] - sub %g4, 1, %g4 - stuw %g4, [%g6] - - orcc %g4, %g0, %g0 ! ISRs still nested? - bnz dont_restore_stack ! Yes then don't restore stack yet - nop - - /* - * This is the outermost interrupt handler. Need to get off the - * CPU Interrupt Stack and back to the tasks stack. - * - * The following subtract should get us back on the interrupted - * tasks stack and add enough room to invoke the dispatcher. - * When we enable traps, we are mostly back in the context - * of the task and subsequent interrupts can operate normally. - * - * Now %sp points to the bottom of the ISF. - * - */ - - sub %g7, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp - - dont_restore_stack: - - /* - * If dispatching is disabled (includes nested interrupt case), - * then do a "simple" exit. - */ - - orcc %g5, %g0, %g0 ! Is dispatching disabled? - bnz simple_return ! Yes, then do a "simple" exit - ! NOTE: Use the delay slot - mov %g0, %g4 ! clear g4 for ofw - - ! Are we dispatching from a previous ISR in the interrupted thread? - setx SYM(_CPU_ISR_Dispatch_disable), %o5, %g5 - lduw [%g5], %o5 - orcc %o5, %g0, %g0 ! Is this thread already doing an ISR? - bnz simple_return ! Yes, then do a "simple" exit - nop - - setx DISPATCH_NEEDED, %o5, %g7 - - - /* - * If a context switch is necessary, then do fudge stack to - * return to the interrupt dispatcher. - */ - - ldub [%g7], %o5 - - orcc %o5, %g0, %g0 ! Is thread switch necessary? - bz simple_return ! no, then do a simple return. otherwise fallthru - nop - - /* - * Invoke interrupt dispatcher. - */ - - ! Set ISR dispatch nesting prevention flag - mov 1, %o1 - setx SYM(_CPU_ISR_Dispatch_disable), %o5, %o2 - stuw %o1, [%o2] - - - ! **** ENABLE TRAPS **** - wrpr %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK | \ - SPARC_PSTATE_IE_MASK, %pstate - isr_dispatch: - call SYM(_Thread_Dispatch), 0 - nop - - /* - * We invoked _Thread_Dispatch in a state similar to the interrupted - * task. In order to safely be able to tinker with the register - * windows and get the task back to its pre-interrupt state, - * we need to disable interrupts. - */ - mov 2, %g4 ! syscall (disable interrupts) - ta 0 ! syscall (disable interrupts) - mov 0, %g4 - - /* - * While we had ISR dispatching disabled in this thread, - * did we miss anything. If so, then we need to do another - * _Thread_Dispatch before leaving this ISR Dispatch context. - */ - - setx DISPATCH_NEEDED, %o5, %o1 - ldub [%o1], %o2 - - orcc %o2, %g0, %g0 ! Is thread switch necessary? - bz allow_nest_again ! No, then clear out and return - nop - - ! Yes, then invoke the dispatcher -dispatchAgain: - mov 3, %g4 ! syscall (enable interrupts) - ta 0 ! syscall (enable interrupts) - ba isr_dispatch - mov 0, %g4 - - allow_nest_again: - - ! Zero out ISR stack nesting prevention flag - setx SYM(_CPU_ISR_Dispatch_disable), %o5, %o1 - stuw %g0,[%o1] - - /* - * The CWP in place at this point may be different from - * that which was in effect at the beginning of the ISR if we - * have been context switched between the beginning of this invocation - * of _ISR_Handler and this point. Thus the CWP and WIM should - * not be changed back to their values at ISR entry time. Any - * changes to the PSR must preserve the CWP. - */ - - simple_return: - flushw ! get register windows to a 'clean' state - - ! **** DISABLE TRAPS **** - wrpr %g0, SPARC_PSTATE_PRIV_MASK, %pstate - - ldx [%sp + STACK_BIAS + ISF_Y_OFFSET], %o1 ! restore y - wr %o1, 0, %y - - ldx [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1 - -! see if cwp is proper (tstate.cwp == cwp) - and %g1, 0x1F, %g6 - rdpr %cwp, %g7 - cmp %g6, %g7 - bz good_window - nop - - /* - * Fix the CWP. Need the cwp to be the proper cwp that - * gets restored when returning from the trap via retry/done. Do - * this before reloading the task's output regs. Basically fake a - * window spill/fill. - * - * Is this necessary on sun4v? Why not just re-write - * tstate.cwp to be equal to the current cwp? - */ - mov %sp, %g1 - stx %l0, [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET] - stx %l1, [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET] - stx %l2, [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET] - stx %l3, [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET] - stx %l4, [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET] - stx %l5, [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET] - stx %l6, [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET] - stx %l7, [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET] - stx %i0, [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET] - stx %i1, [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET] - stx %i2, [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET] - stx %i3, [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET] - stx %i4, [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET] - stx %i5, [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET] - stx %i6, [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET] - stx %i7, [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET] - wrpr %g0, %g6, %cwp - mov %g1, %sp - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET], %l0 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET], %l1 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET], %l2 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET], %l3 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET], %l4 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET], %l5 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET], %l6 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET], %l7 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET], %i0 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET], %i1 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET], %i2 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET], %i3 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET], %i4 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET], %i5 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET], %i6 - ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET], %i7 - - - good_window: - - - /* - * Restore tasks global and out registers - */ - - ldx [%sp + STACK_BIAS + ISF_G1_OFFSET], %g1 ! restore g1 - ldx [%sp + STACK_BIAS + ISF_G2_OFFSET], %g2 ! restore g2 - ldx [%sp + STACK_BIAS + ISF_G3_OFFSET], %g3 ! restore g3 - ldx [%sp + STACK_BIAS + ISF_G4_OFFSET], %g4 ! restore g4 - ldx [%sp + STACK_BIAS + ISF_G5_OFFSET], %g5 ! restore g5 - ldx [%sp + STACK_BIAS + ISF_G6_OFFSET], %g6 ! restore g6 - ldx [%sp + STACK_BIAS + ISF_G7_OFFSET], %g7 ! restore g7 - - ! Assume the interrupted context is in TL 0 with GL 0 / normal globals. - ! When tstate is restored at done/retry, the interrupted context is restored. - ! return to TL[1], GL[1], and restore TSTATE, TPC, and TNPC - wrpr %g0, 1, %tl - - ! return to GL=1 or AG -#if defined(SUN4U) - rdpr %pstate, %o1 - or %o1, SPARC_PSTATE_AG_MASK, %o1 - wrpr %o1, %g0, %pstate ! go to AG. -#elif defined(SUN4V) - wrpr %g0, 1, %gl -#endif - -! now we can use global registers (at gl=1 or AG) - ldx [%sp + STACK_BIAS + ISF_PIL_OFFSET], %g3 - ldx [%sp + STACK_BIAS + ISF_TPC_OFFSET], %g4 - ldx [%sp + STACK_BIAS + ISF_TNPC_OFFSET], %g5 - ldx [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1 - ldx [%sp + STACK_BIAS + ISF_TVEC_OFFSET], %g2 - wrpr %g0, %g3, %pil - wrpr %g0, %g4, %tpc - wrpr %g0, %g5, %tnpc - - wrpr %g0, %g1, %tstate - - ldx [%sp + STACK_BIAS + ISF_O0_OFFSET], %o0 ! restore o0 - ldx [%sp + STACK_BIAS + ISF_O1_OFFSET], %o1 ! restore o1 - ldx [%sp + STACK_BIAS + ISF_O2_OFFSET], %o2 ! restore o2 - ldx [%sp + STACK_BIAS + ISF_O3_OFFSET], %o3 ! restore o3 - ldx [%sp + STACK_BIAS + ISF_O4_OFFSET], %o4 ! restore o4 - ldx [%sp + STACK_BIAS + ISF_O5_OFFSET], %o5 ! restore o5 - ! sp is restored later - ldx [%sp + STACK_BIAS + ISF_O7_OFFSET], %o7 ! restore o7 - - ldx [%sp + STACK_BIAS + ISF_O6_SP_OFFSET], %o6 ! restore o6/sp - - /* - * Determine whether to re-execute the trapping instruction - * (asynchronous trap) or to skip the trapping instruction - * (synchronous trap). - */ - - andcc %g2, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0 - ! Is this a synchronous trap? - be not_synch ! No, then skip trapping instruction - mov 0, %g4 - retry ! re-execute trapping instruction - not_synch: - done ! skip trapping instruction - -/* end of file */ diff --git a/cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c b/cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c deleted file mode 100644 index ba629fd073..0000000000 --- a/cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Copyright (c) 2012 embedded brains GmbH & Co. KG - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) -{ - /* TODO */ -} diff --git a/cpukit/score/cpu/sparc64/sparc64-syscall.S b/cpukit/score/cpu/sparc64/sparc64-syscall.S deleted file mode 100644 index 9a467e8922..0000000000 --- a/cpukit/score/cpu/sparc64/sparc64-syscall.S +++ /dev/null @@ -1,145 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * systrap.S - * - * This file contains emulated system calls using software trap 0. - * The following calls are supported: - * - * + SYS_exit (halt) - * + SYS_irqdis (disable interrupts) - * + SYS_irqset (set interrupt level) - * - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "sparc64-syscall.h" - - -.seg "text" -/* - * system call - * - * On entry: - * g4[AG | GL=1] = tstate (from trap table) - * g2[AG | GL=1] = trap vector # (256) - * g3[AG | GL=1] = address of SYM(syscall) - * g4[AG | GL-1] = system call id - * if arch = sun4v: - * We need to back to GL-1 to read the system call id. - * on sun4u: - * We need to go back to the normal globals to read the system call id. - * - * First thing is to return to the previous set of globals, so - * that the system call id can be read. The syscall code needs - * to re-read tstate. - * - * syscall should only ever be entered by ta 0 being called explicitly - * by a function that knows what is happening. This means the syscall - * code can safely use any scratch registers and the %o registers. - */ - - -PUBLIC(syscall) - - - SYM(syscall): - mov %g0, %g4 ! clear %g4 at this GL -#if defined (SUN4U) - rdpr %pstate, %g1 - andn %g1, SPARC_PSTATE_AG_MASK, %g1 - wrpr %g1, %g0, %pstate ! go to regular globals -#elif defined (SUN4V) - rdpr %gl, %g1 - dec %g1 - wrpr %g0, %g1, %gl ! go back to GL = GL - 1 -#endif - - subcc %g4, 2, %g0 - bne 3f - rdpr %tstate, %g5 ! re-read tstate, use delay slot - - ! syscall 2, disable interrupts - rdpr %pil, %g1 - and %g5, SPARC_TSTATE_IE_MASK, %o0 - or %o0, %g1, %o0 ! return TSTATE_IE | PIL - wrpr %g0, 0xf, %pil ! set PIL to 15 - andn %g5, SPARC_TSTATE_IE_MASK, %g1 - wrpr %g0, %g1, %tstate ! disable interrupts in trap state - ba,a 9f - - 3: ! syscall 3, enable interrupts - subcc %g4, 3, %g0 - bne 1f - and %o0, 0xf, %g1 - wrpr %g0, %g1, %pil ! restore PIL -! and %o0, SPARC_TSTATE_IE_MASK, %g1 -! or %g5, %g1, %g1 ! restore saved IE - or %g5, SPARC_TSTATE_IE_MASK, %g1 ! restore IE (safe?) - wrpr %g0, %g1, %tstate - ba,a 9f - - 1: - ba,a 1b ! spin. taking a trap here -> htrap - - 9: ! leave - mov 0, %g4 ! clear %g4 - DONE - -PUBLIC(sparc_disable_interrupts) - - SYM(sparc_disable_interrupts): - mov SYS_irqdis, %g4 - ta 0 -#if 0 - rdpr %pstate, %g5 - rdpr %pil, %g1 - and %g5, SPARC_PSTATE_IE_MASK, %o0 - or %o0, %g1, %o0 ! return PSTATE_IE | PIL - wrpr %g0, 0xf, %pil ! set PIL to 15 - andn %g5, SPARC_PSTATE_IE_MASK, %g1 - wrpr %g0, %g1, %pstate ! disable interrupts -#endif - retl - nop - -PUBLIC(sparc_enable_interrupts) - - SYM(sparc_enable_interrupts): - mov SYS_irqen, %g4 - ta 0 -#if 0 - rdpr %pstate, %g5 - and %o0, 0xf, %g1 - wrpr %g0, %g1, %pil ! restore PIL - and %o0, SPARC_PSTATE_IE_MASK, %g1 - or %g5, %g1, %g1 ! restore saved IE -! or %g5, SPARC_PSTATE_IE_MASK, %g1 ! set IE regardless of old (safe?) - wrpr %g0, %g1, %pstate -#endif - retl - nop - - /* end of file */ diff --git a/cpukit/score/cpu/sparc64/sparc64-syscall.h b/cpukit/score/cpu/sparc64/sparc64-syscall.h deleted file mode 100644 index 85a74fa0f8..0000000000 --- a/cpukit/score/cpu/sparc64/sparc64-syscall.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 1999 Jiri Gaisler - * - * Permission to use, copy, modify, and/or distribute this software - * for any purpose with or without fee is hereby granted. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL - * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES - * OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, - * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, - * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#define SYS_exit 1 -#define SYS_irqdis 2 -#define SYS_irqen 3 diff --git a/spec/build/bsps/sparc64/grp.yml b/spec/build/bsps/sparc64/grp.yml deleted file mode 100644 index b1a505ab6d..0000000000 --- a/spec/build/bsps/sparc64/grp.yml +++ /dev/null @@ -1,61 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -build-type: group -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -cxxflags: [] -enabled-by: true -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/sparc64/include/asm.h - - bsps/sparc64/include/traptable.h -- destination: ${BSP_INCLUDEDIR}/arch - source: - - bsps/sparc64/include/arch/arch.h - - bsps/sparc64/include/arch/boot.h - - bsps/sparc64/include/arch/regdef.h - - bsps/sparc64/include/arch/stack.h -- destination: ${BSP_INCLUDEDIR}/arch/mm - source: - - bsps/sparc64/include/arch/mm/cache_spec.h - - bsps/sparc64/include/arch/mm/doxygen.h - - bsps/sparc64/include/arch/mm/frame.h - - bsps/sparc64/include/arch/mm/mmu.h - - bsps/sparc64/include/arch/mm/page.h - - bsps/sparc64/include/arch/mm/tlb.h - - bsps/sparc64/include/arch/mm/tte.h -- destination: ${BSP_INCLUDEDIR}/arch/mm/sun4u - source: - - bsps/sparc64/include/arch/mm/sun4u/frame.h - - bsps/sparc64/include/arch/mm/sun4u/mmu.h - - bsps/sparc64/include/arch/mm/sun4u/page.h - - bsps/sparc64/include/arch/mm/sun4u/tlb.h - - bsps/sparc64/include/arch/mm/sun4u/tte.h -- destination: ${BSP_INCLUDEDIR}/arch/sun4u - source: - - bsps/sparc64/include/arch/sun4u/arch.h -- destination: ${BSP_INCLUDEDIR}/boot - source: - - bsps/sparc64/include/boot/align.h - - bsps/sparc64/include/boot/balloc.h - - bsps/sparc64/include/boot/gentypes.h - - bsps/sparc64/include/boot/main.h - - bsps/sparc64/include/boot/ofw.h - - bsps/sparc64/include/boot/ofw_tree.h - - bsps/sparc64/include/boot/ofwarch.h - - bsps/sparc64/include/boot/register.h - - bsps/sparc64/include/boot/types.h -- destination: ${BSP_INCLUDEDIR}/genarch/ofw - source: - - bsps/sparc64/include/genarch/ofw/ofw_tree.h -- destination: ${BSP_INCLUDEDIR}/kernel - source: - - bsps/sparc64/include/kernel/align.h -ldflags: [] -links: [] -type: build -use-after: [] -use-before: [] diff --git a/spec/build/bsps/sparc64/niagara/abi.yml b/spec/build/bsps/sparc64/niagara/abi.yml deleted file mode 100644 index 6cc0e02274..0000000000 --- a/spec/build/bsps/sparc64/niagara/abi.yml +++ /dev/null @@ -1,19 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: - - -DSUN4V - - -mcpu=niagara -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/sparc64/niagara/bspniagara.yml b/spec/build/bsps/sparc64/niagara/bspniagara.yml deleted file mode 100644 index 94ee344f14..0000000000 --- a/spec/build/bsps/sparc64/niagara/bspniagara.yml +++ /dev/null @@ -1,63 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: sparc64 -bsp: niagara -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: niagara -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/sparc64/niagara/include/bsp.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/sparc64/niagara/include/bsp/irq.h -- destination: ${BSP_LIBDIR} - source: - - bsps/sparc64/shared/start/linkcmds - - bsps/sparc64/shared/start/linkcmds -links: -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: ../grp -- role: build-dependency - uid: abi -- role: build-dependency - uid: ../start -- role: build-dependency - uid: ../../bspopts -source: -- bsps/shared/cache/nocache.c -- bsps/shared/dev/btimer/btimer-cpucounter.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/serial/legacy-console-control.c -- bsps/shared/dev/serial/legacy-console-select.c -- bsps/shared/dev/serial/legacy-console.c -- bsps/shared/start/bspstart-empty.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -- bsps/sparc64/niagara/start/bspclean.c -- bsps/sparc64/niagara/start/bspinit.S -- bsps/sparc64/niagara/start/m5op_sparc.S -- bsps/sparc64/shared/clock/ckinit.c -- bsps/sparc64/shared/console/conscfg.c -- bsps/sparc64/shared/helenos/boot/genarch/balloc.c -- bsps/sparc64/shared/helenos/boot/genarch/ofw.c -- bsps/sparc64/shared/helenos/boot/genarch/ofw_tree.c -- bsps/sparc64/shared/helenos/boot/sparc64/loader/main.c -- bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwarch.c -- bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwasm.S -- bsps/sparc64/shared/start/halt.S -- bsps/sparc64/shared/start/setvec.c -type: build diff --git a/spec/build/bsps/sparc64/start.yml b/spec/build/bsps/sparc64/start.yml deleted file mode 100644 index 3e8e65d826..0000000000 --- a/spec/build/bsps/sparc64/start.yml +++ /dev/null @@ -1,14 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -asflags: [] -build-type: start-file -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -includes: [] -install-path: ${BSP_LIBDIR} -links: [] -source: -- bsps/sparc64/shared/start/start.S -target: start.o -type: build diff --git a/spec/build/bsps/sparc64/usiii/abi.yml b/spec/build/bsps/sparc64/usiii/abi.yml deleted file mode 100644 index 8673c41b60..0000000000 --- a/spec/build/bsps/sparc64/usiii/abi.yml +++ /dev/null @@ -1,20 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: - - -DSUN4U - - -DUS3 - - -mcpu=ultrasparc3 -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/sparc64/usiii/bspusiii.yml b/spec/build/bsps/sparc64/usiii/bspusiii.yml deleted file mode 100644 index c6f37d5816..0000000000 --- a/spec/build/bsps/sparc64/usiii/bspusiii.yml +++ /dev/null @@ -1,67 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: sparc64 -bsp: usiii -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: usiii -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/sparc64/usiii/include/bsp.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/sparc64/usiii/include/bsp/irq.h -- destination: ${BSP_LIBDIR} - source: - - bsps/sparc64/shared/start/linkcmds - - bsps/sparc64/shared/start/linkcmds -links: -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: ../grp -- role: build-dependency - uid: ../start -- role: build-dependency - uid: abi -- role: build-dependency - uid: optclkfastidle -- role: build-dependency - uid: ../../bspopts -source: -- bsps/shared/cache/nocache.c -- bsps/shared/dev/btimer/btimer-cpucounter.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/serial/legacy-console-control.c -- bsps/shared/dev/serial/legacy-console-select.c -- bsps/shared/dev/serial/legacy-console.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/bspstart-empty.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -- bsps/sparc64/shared/clock/ckinit.c -- bsps/sparc64/shared/console/conscfg.c -- bsps/sparc64/shared/helenos/boot/genarch/balloc.c -- bsps/sparc64/shared/helenos/boot/genarch/ofw.c -- bsps/sparc64/shared/helenos/boot/genarch/ofw_tree.c -- bsps/sparc64/shared/helenos/boot/sparc64/loader/main.c -- bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwarch.c -- bsps/sparc64/shared/helenos/boot/sparc64/loader/ofwasm.S -- bsps/sparc64/shared/helenos/kernel/sparc64/src/cache.S -- bsps/sparc64/shared/helenos/kernel/sparc64/src/sun4u/takemmu.S -- bsps/sparc64/shared/start/halt.S -- bsps/sparc64/shared/start/setvec.c -- bsps/sparc64/shared/start/trap_table.S -- bsps/sparc64/usiii/start/bspinit.S -type: build diff --git a/spec/build/bsps/sparc64/usiii/optclkfastidle.yml b/spec/build/bsps/sparc64/usiii/optclkfastidle.yml deleted file mode 100644 index 72e7ab8d9a..0000000000 --- a/spec/build/bsps/sparc64/usiii/optclkfastidle.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - If defined, speed up the clock ticks while the idle task is running so time spent in the idle task is minimized. This significantly reduces the wall time required to execute the RTEMS test suites. -enabled-by: true -links: [] -name: SIMSPARC_FAST_IDLE -type: build diff --git a/spec/build/cpukit/cpusparc64.yml b/spec/build/cpukit/cpusparc64.yml deleted file mode 100644 index dd35439e4f..0000000000 --- a/spec/build/cpukit/cpusparc64.yml +++ /dev/null @@ -1,30 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -build-type: objects -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -cxxflags: [] -enabled-by: -- sparc64 -includes: [] -install: -- destination: ${BSP_INCLUDEDIR}/rtems - source: - - cpukit/score/cpu/sparc64/include/rtems/asm.h -- destination: ${BSP_INCLUDEDIR}/rtems/score - source: - - cpukit/score/cpu/sparc64/include/rtems/score/cpu.h - - cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h - - cpukit/score/cpu/sparc64/include/rtems/score/sparc64.h -links: [] -source: -- cpukit/score/cpu/no_cpu/cpucounterfrequency.c -- cpukit/score/cpu/no_cpu/cpucounterread.c -- cpukit/score/cpu/no_cpu/cpuidle.c -- cpukit/score/cpu/sparc64/context.S -- cpukit/score/cpu/sparc64/cpu.c -- cpukit/score/cpu/sparc64/interrupt.S -- cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c -- cpukit/score/cpu/sparc64/sparc64-syscall.S -type: build diff --git a/spec/build/cpukit/librtemscpu.yml b/spec/build/cpukit/librtemscpu.yml index 4187456840..cfd03bc751 100644 --- a/spec/build/cpukit/librtemscpu.yml +++ b/spec/build/cpukit/librtemscpu.yml @@ -504,8 +504,6 @@ links: uid: cpuriscv - role: build-dependency uid: cpusparc -- role: build-dependency - uid: cpusparc64 - role: build-dependency uid: cpuv850 - role: build-dependency