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2001-01-24 Ralf Corsepius <corsepiu@faw.uni-ulm.de>

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* Makefile.am, README, console/console-io.c, start/start.S,
	startup/linkcmds: Update to make shsim closer to functional.
This commit is contained in:
Joel Sherrill
2001-01-24 19:10:38 +00:00
parent b00b6a7808
commit e8a7a466a2
6 changed files with 125 additions and 63 deletions
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5
c/src/lib/libbsp/sh/shsim/ChangeLog
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@@ -1,3 +1,8 @@
2001-01-24 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am, README, console/console-io.c, start/start.S,
startup/linkcmds: Update to make shsim closer to functional.
2001-01-03 Joel Sherrill <joel@OARcorp.com> 2001-01-03 Joel Sherrill <joel@OARcorp.com>
* console/console-io.c: Added console_initialize_hardware(). * console/console-io.c: Added console_initialize_hardware().

3
c/src/lib/libbsp/sh/shsim/Makefile.am
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@@ -7,12 +7,11 @@ ACLOCAL_AMFLAGS = -I ../../../../../../aclocal
# wrapup is the one that actually builds and installs the library # wrapup is the one that actually builds and installs the library
# from the individual .rel files built in other directories # from the individual .rel files built in other directories
#SUBDIRS = include start startup clock console timer wrapup
SUBDIRS = include start startup clock console wrapup SUBDIRS = include start startup clock console wrapup
include $(top_srcdir)/../../bsp.am include $(top_srcdir)/../../bsp.am
EXTRA_DIST = bsp_specs times EXTRA_DIST = bsp_specs
include $(top_srcdir)/../../../../../../automake/subdirs.am include $(top_srcdir)/../../../../../../automake/subdirs.am
include $(top_srcdir)/../../../../../../automake/local.am include $(top_srcdir)/../../../../../../automake/local.am

28
c/src/lib/libbsp/sh/shsim/README
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@@ -6,9 +6,31 @@ Simple BSP for the SH simulator built into gdb.
Simulator Invocation Simulator Invocation
==================== ====================
target sim sh-rtems[elf|]-gdb <executable>
(gdb) target sim
(gdb) set archi [sh|sh2]
(gdb) load <executable>
(gdb) run
Status Status
====== ======
Does not link yet. libcpu/sh code needs to be addressed so we can
get context switch code. * The simulator invocation procedure outlined above produces error messages
with gdb-5.0, nevertheless seems to work. With gdb versions > 5.0 these
error messages are gone. I.e. if you plan to seriously work with the gdb
simulator better use gdb versions > 5.0.
* gdb's simulator is not able to correctly emulate memory areas esp. shadowing
and non-consecutive memory. I.e. access to memory areas besides area 0 will
(bogusly) generate SIGBUS exceptions. This includes access to area 5
(On-chip peripherials) and prevents simulation of configuration of
accesses to on-chip peripherials.
* Due to limitations of the simulator you will only be able to run
applications which do not try to access any SH control registers.
Currently, this excludes all applications, which apply timers and serial
devices, i.e. almost any real world application.
* The simulator currently uses gdb's trap34 interface for console I/O. This
could be replaced with polled sci1 I/O for SHes > SH1.

7
c/src/lib/libbsp/sh/shsim/console/console-io.c
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@@ -24,6 +24,10 @@
#define SYS_read 3 #define SYS_read 3
#define SYS_write 4 #define SYS_write 4
int errno ;
extern int __trap34(int, int, void*, int );
/* /*
* console_initialize_hardware * console_initialize_hardware
* *
@@ -47,7 +51,8 @@ void console_outbyte_polled(
char ch char ch
) )
{ {
return __trap34 (SYS_write, 1, &ch, 1); __trap34 (SYS_write, 1, &ch, 1);
return;
} }
/* /*

93
c/src/lib/libbsp/sh/shsim/start/start.S
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@@ -1,29 +1,64 @@
.section .text /*
.global start * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
start: * Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include "asm.h"
BEGIN_CODE
PUBLIC(start)
SYM (start):
! install the stack pointer
mov.l stack_k,r15 mov.l stack_k,r15
! zero out bss ! zero out bss
mov.l edata_k,r0 mov.l edata_k,r0
mov.l end_k,r1 mov.l end_k,r1
mov #0,r2 mov #0,r2
start_l: 0:
mov.l r2,@r0 mov.l r2,@r0
add #4,r0 add #4,r0
cmp/ge r0,r1 cmp/ge r0,r1
bt start_l bt 0b
#if defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY) ! copy the vector table from rom to ram
mov.l set_fpscr_k, r1 mov.l vects_k,r0 ! vectab
jsr @r1 mov #0,r1 ! address of boot vector table
mov #0,r4 mov #0,r2 ! number of bytes copied
lds r3,fpscr mov.w vects_size,r3 ! size of entries in vectab
#endif /* defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) */ 1:
mov.l @r1+,r4
mov.l r4,@r0
add #4,r0
add #1,r2
cmp/hi r3,r2
bf 1b
mov.l vects_k,r0 ! update vbr to point to vectab
ldc r0,vbr
! call the mainline ! call the mainline
mov.l boot_card_k,r0 mov #0,r4 ! argc
jsr @r0 mov.l main_k,r0
or r0,r0 jsr @r0
mov #0,r5 ! argv
! call exit ! call exit
mov r0,r4 mov r0,r4
@@ -31,25 +66,31 @@ start_l:
jsr @r0 jsr @r0
or r0,r0 or r0,r0
END_CODE
.align 2 .align 2
#if defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
set_fpscr_k:
.long ___set_fpscr
#endif /* defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(SH4_SINGLE_ONLY) */
stack_k: stack_k:
.long _stack .long SYM(stack)
edata_k: edata_k:
.long _edata .long SYM(edata)
end_k: end_k:
.long _end .long SYM(end)
boot_card_k: main_k:
.long _boot_card .long SYM(boot_card)
exit_k: exit_k:
.long _exit .long SYM(exit)
vects_k:
.long SYM(vectab)
vects_size:
.word 255
#ifdef __ELF__ #ifdef __ELF__
.section .stack,"aw" .section .stack,"aw"
#else #else
.section .stack .section .stack
#endif #endif
_stack: .long 0xdeaddead SYM(stack):
.long 0xdeaddead
monvects_k:
.long SYM(monvects)

52
c/src/lib/libbsp/sh/shsim/startup/linkcmds
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@@ -1,35 +1,24 @@
/* /*
* This is an adapted linker script from egcs-1.0.1 * Memory layout for an SH 7032 with main memory in area 0
* *
* Memory layout for an SH 7032 with main memory in area 2 * NOTES:
* This memory layout it very similar to that used for Hitachi's * + All RAM/ROM areas are mapped onto area 0, because gdb's simulator
* EVB with CMON in rom * is not able to simulate memory areas but area 0. Area 5 (on-chip
* peripherials) can not be mapped onto area 0 and will cause SIGILL
* exceptions.
* + Assumed to be compatible with other SH-cpu family members (eg. SH7045)
* *
* NOTE: The ram start address may vary, all other start addresses are fixed * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
* Not suiteable for gdb's simulator
* *
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and * COPYRIGHT (c) 2001, Ralf Corsepius, Ulm, Germany
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* *
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$ * $Id$
*/ */
OUTPUT_FORMAT("coff-sh")
OUTPUT_ARCH(sh) OUTPUT_ARCH(sh)
ENTRY(_start) ENTRY(_start)
@@ -37,33 +26,34 @@ MEMORY
{ {
rom : o = 0x00000000, l = 128k rom : o = 0x00000000, l = 128k
onchip_peri : o = 0x05000000, l = 512 onchip_peri : o = 0x05000000, l = 512
ram : o = 0x0A040000, l = 256k ram : o = 0x00040000, l = 256k
onchip_ram : o = 0x0f000000, l = 8k onchip_ram : o = 0x00080000, l = 8k
} }
SECTIONS SECTIONS
{ {
/* boot vector table */ /* boot vector table */
.monvects 0x00000000 (NOLOAD): { .monvects 0x00000000 (NOLOAD) :
{
_monvects = . ; _monvects = . ;
} > rom } > rom
/* monitor play area */ /* monitor play area */
.monram 0x0A040000 (NOLOAD) : .monram 0x00040000 (NOLOAD) :
{ {
_ramstart = .; _ramstart = .;
} > ram } > ram
/* monitor vector table */ /* monitor vector table */
.vects 0x0A042000 (NOLOAD) : { .vects 0x00042000 (NOLOAD) : {
_vectab = . ; _vectab = . ;
*(.vects); *(.vects);
} }
/* Read-only sections, merged into text segment: */ /* Read-only sections, merged into text segment: */
. = 0x0a044000 ; . = 0x00044000 ;
.interp : { *(.interp) } .interp : { *(.interp) }
.hash : { *(.hash) } .hash : { *(.hash) }
.dynsym : { *(.dynsym) } .dynsym : { *(.dynsym) }
@@ -153,15 +143,15 @@ SECTIONS
_end = . ; _end = . ;
PROVIDE (end = .); PROVIDE (end = .);
_HeapBase = . ; _HeapStart = . ;
. = . + 1024 * 20 ; . = . + 1024 * 20 ;
PROVIDE( _HeapEnd = . ); PROVIDE( _HeapEnd = . );
_WorkSpaceBase = . ; _WorkSpaceStart = . ;
. = 0x0a080000 ; . = 0x00080000 ;
PROVIDE(_WorkSpaceEnd = .); PROVIDE(_WorkSpaceEnd = .);
_CPU_Interrupt_stack_low = 0x0f000000 ; _CPU_Interrupt_stack_low = 0x00080000 ;
_CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ; _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
/* Stabs debugging sections. */ /* Stabs debugging sections. */
@@ -198,6 +188,6 @@ SECTIONS
.debug_typenames 0 : { *(.debug_typenames) } .debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) } .debug_varnames 0 : { *(.debug_varnames) }
.stack 0x0f001ff0 : { _stack = .; *(.stack) } > onchip_ram .stack 0x00081ff0 : { _stack = .; *(.stack) } > onchip_ram
/* These must appear regardless of . */ /* These must appear regardless of . */
} }