forked from Imagelibrary/rtems
rtems: Use size_t for cache line size
A cache line cannot have a negative size.
This commit is contained in:
@@ -629,7 +629,7 @@ static void initializeHardware(struct bfin_ethernetSoftc *sc) {
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including other status structures, so we can safely manage both the
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including other status structures, so we can safely manage both the
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processor and DMA writing to them. So this rounds up the structure
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processor and DMA writing to them. So this rounds up the structure
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sizes to a multiple of the cache line size. */
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sizes to a multiple of the cache line size. */
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cacheAlignment = rtems_cache_get_data_line_size();
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cacheAlignment = (int) rtems_cache_get_data_line_size();
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if (cacheAlignment == 0)
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if (cacheAlignment == 0)
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cacheAlignment = 1;
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cacheAlignment = 1;
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rxStatusSize = cacheAlignment * ((sizeof(rxStatusT) + cacheAlignment - 1) /
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rxStatusSize = cacheAlignment * ((sizeof(rxStatusT) + cacheAlignment - 1) /
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@@ -21,7 +21,7 @@ int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum)
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/* Do we have a dcbz instruction? */
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/* Do we have a dcbz instruction? */
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if ((opcode & 0xffe007ff) == 0x7c0007ec) {
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if ((opcode & 0xffe007ff) == 0x7c0007ec) {
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unsigned clsz = (unsigned) rtems_cache_get_data_line_size();
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unsigned clsz = rtems_cache_get_data_line_size();
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unsigned a = (opcode >> 16) & 0x1f;
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unsigned a = (opcode >> 16) & 0x1f;
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unsigned b = (opcode >> 11) & 0x1f;
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unsigned b = (opcode >> 11) & 0x1f;
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unsigned *regs = &frame->GPR0;
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unsigned *regs = &frame->GPR0;
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@@ -149,7 +149,7 @@ rtems_cache_invalidate_entire_data( void )
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/*
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/*
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* This function returns the data cache granularity.
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* This function returns the data cache granularity.
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*/
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*/
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int
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size_t
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rtems_cache_get_data_line_size( void )
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rtems_cache_get_data_line_size( void )
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{
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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@@ -264,7 +264,7 @@ rtems_cache_invalidate_entire_instruction( void )
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/*
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/*
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* This function returns the instruction cache granularity.
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* This function returns the instruction cache granularity.
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*/
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*/
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int
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size_t
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rtems_cache_get_instruction_line_size( void )
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rtems_cache_get_instruction_line_size( void )
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{
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{
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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@@ -47,7 +47,7 @@ extern "C" {
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* @retval 0 No data cache is present.
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* @retval 0 No data cache is present.
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* @retval positive The data cache line size in bytes.
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* @retval positive The data cache line size in bytes.
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*/
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*/
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int rtems_cache_get_data_line_size( void );
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size_t rtems_cache_get_data_line_size( void );
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/**
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/**
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* @brief Returns the instruction cache line size in bytes.
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* @brief Returns the instruction cache line size in bytes.
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@@ -58,7 +58,7 @@ int rtems_cache_get_data_line_size( void );
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* @retval 0 No instruction cache is present.
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* @retval 0 No instruction cache is present.
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* @retval positive The instruction cache line size in bytes.
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* @retval positive The instruction cache line size in bytes.
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*/
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*/
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int rtems_cache_get_instruction_line_size( void );
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size_t rtems_cache_get_instruction_line_size( void );
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/**
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/**
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* @brief Flushes multiple data cache lines.
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* @brief Flushes multiple data cache lines.
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@@ -165,7 +165,7 @@ static void test_timing(void)
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uint64_t d[3];
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uint64_t d[3];
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printf(
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printf(
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"data cache line size %i bytes\n",
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"data cache line size %zi bytes\n",
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rtems_cache_get_data_line_size()
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rtems_cache_get_data_line_size()
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);
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);
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@@ -290,7 +290,7 @@ static void test_timing(void)
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);
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);
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printf(
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printf(
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"instruction cache line size %i bytes\n",
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"instruction cache line size %zi bytes\n",
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rtems_cache_get_instruction_line_size()
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rtems_cache_get_instruction_line_size()
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);
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);
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