RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

bsps/arm: Initialize priorities of PPIs

Browse Source 
At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs).  We have to initialize the
priority of the PPIs on secondary processors.
This commit is contained in:
Sebastian Huber
2020-02-21 14:21:33 +01:00
parent 486829b276
commit e58ecb8433
1 changed files with 6 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
bsps/arm/shared/irq/irq-gic.c
View File

@@ -152,6 +152,7 @@ BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
{ {
volatile gic_cpuif *cpuif = GIC_CPUIF; volatile gic_cpuif *cpuif = GIC_CPUIF;
volatile gic_dist *dist = ARM_GIC_DIST; volatile gic_dist *dist = ARM_GIC_DIST;
uint32_t id;
while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) { while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) {
/* Wait */ /* Wait */
@@ -161,6 +162,11 @@ BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
dist->icdigr[0] = 0xffffffff; dist->icdigr[0] = 0xffffffff;
#endif #endif
/* Initialize Peripheral Private Interrupts (PPIs) */
for (id = 0; id < 32; ++id) {
gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
}
cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
cpuif->iccicr = CPUIF_ICCICR; cpuif->iccicr = CPUIF_ICCICR;