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bsps/grlib: Fix FTMCTRL - MCFG1 bit fields

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There was an off by one error in all bit fields.  Add the R flag.

Update #4842.
This commit is contained in:
Sebastian Huber
2023-02-16 09:11:22 +01:00
parent 2d71cba033
commit e56cecf501
1 changed files with 60 additions and 47 deletions
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107
bsps/include/grlib/ftmctrl-regs.h
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@@ -82,59 +82,61 @@ extern "C" {
* @{
*/
#define FTMCTRL_MCFG1_PBRDY 0x80000000U
#define FTMCTRL_MCFG1_PBRDY 0x40000000U
#define FTMCTRL_MCFG1_ABRDY 0x40000000U
#define FTMCTRL_MCFG1_ABRDY 0x20000000U
#define FTMCTRL_MCFG1_IOBUSW 0x20000000U
#define FTMCTRL_MCFG1_IOBUSW_SHIFT 27
#define FTMCTRL_MCFG1_IOBUSW_MASK 0x18000000U
#define FTMCTRL_MCFG1_IOBUSW_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_IOBUSW_MASK ) >> \
FTMCTRL_MCFG1_IOBUSW_SHIFT )
#define FTMCTRL_MCFG1_IOBUSW_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IOBUSW_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \
FTMCTRL_MCFG1_IOBUSW_MASK ) )
#define FTMCTRL_MCFG1_IOBUSW( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \
FTMCTRL_MCFG1_IOBUSW_MASK )
#define FTMCTRL_MCFG1_IBRDY_SHIFT 27
#define FTMCTRL_MCFG1_IBRDY_MASK 0x18000000U
#define FTMCTRL_MCFG1_IBRDY_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_IBRDY_MASK ) >> \
FTMCTRL_MCFG1_IBRDY_SHIFT )
#define FTMCTRL_MCFG1_IBRDY_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IBRDY_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_IBRDY_SHIFT ) & \
FTMCTRL_MCFG1_IBRDY_MASK ) )
#define FTMCTRL_MCFG1_IBRDY( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_IBRDY_SHIFT ) & \
FTMCTRL_MCFG1_IBRDY_MASK )
#define FTMCTRL_MCFG1_IBRDY 0x4000000U
#define FTMCTRL_MCFG1_BEXCN 0x4000000U
#define FTMCTRL_MCFG1_BEXCN 0x2000000U
#define FTMCTRL_MCFG1_IO_WAITSTATES 0x1000000U
#define FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT 20
#define FTMCTRL_MCFG1_IO_WAITSTATES_MASK 0xf00000U
#define FTMCTRL_MCFG1_IO_WAITSTATES_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) >> \
FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT )
#define FTMCTRL_MCFG1_IO_WAITSTATES_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \
FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) )
#define FTMCTRL_MCFG1_IO_WAITSTATES( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \
FTMCTRL_MCFG1_IO_WAITSTATES_MASK )
#define FTMCTRL_MCFG1_IOEN_SHIFT 20
#define FTMCTRL_MCFG1_IOEN_MASK 0xf00000U
#define FTMCTRL_MCFG1_IOEN_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_IOEN_MASK ) >> \
FTMCTRL_MCFG1_IOEN_SHIFT )
#define FTMCTRL_MCFG1_IOEN_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IOEN_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_IOEN_SHIFT ) & \
FTMCTRL_MCFG1_IOEN_MASK ) )
#define FTMCTRL_MCFG1_IOEN( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_IOEN_SHIFT ) & \
FTMCTRL_MCFG1_IOEN_MASK )
#define FTMCTRL_MCFG1_IOEN 0x80000U
#define FTMCTRL_MCFG1_ROMBANKSZ 0x80000U
#define FTMCTRL_MCFG1_R 0x40000U
#define FTMCTRL_MCFG1_PWEN_SHIFT 14
#define FTMCTRL_MCFG1_PWEN_MASK 0x3c000U
#define FTMCTRL_MCFG1_PWEN_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PWEN_MASK ) >> \
FTMCTRL_MCFG1_PWEN_SHIFT )
#define FTMCTRL_MCFG1_PWEN_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PWEN_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_PWEN_SHIFT ) & \
FTMCTRL_MCFG1_PWEN_MASK ) )
#define FTMCTRL_MCFG1_PWEN( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_PWEN_SHIFT ) & \
FTMCTRL_MCFG1_PWEN_MASK )
#define FTMCTRL_MCFG1_ROMBANKSZ_SHIFT 14
#define FTMCTRL_MCFG1_ROMBANKSZ_MASK 0x3c000U
#define FTMCTRL_MCFG1_ROMBANKSZ_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_ROMBANKSZ_MASK ) >> \
FTMCTRL_MCFG1_ROMBANKSZ_SHIFT )
#define FTMCTRL_MCFG1_ROMBANKSZ_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_ROMBANKSZ_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \
FTMCTRL_MCFG1_ROMBANKSZ_MASK ) )
#define FTMCTRL_MCFG1_ROMBANKSZ( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \
FTMCTRL_MCFG1_ROMBANKSZ_MASK )
#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 12
#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x3000U
#define FTMCTRL_MCFG1_PWEN 0x800U
#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 8
#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x300U
#define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WIDTH_MASK ) >> \
FTMCTRL_MCFG1_PROM_WIDTH_SHIFT )
@@ -146,10 +148,21 @@ extern "C" {
( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
FTMCTRL_MCFG1_PROM_WIDTH_MASK )
#define FTMCTRL_MCFG1_PROM_WRITE_WS 0x800U
#define FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT 4
#define FTMCTRL_MCFG1_PROM_WRITE_WS_MASK 0xf0U
#define FTMCTRL_MCFG1_PROM_WRITE_WS_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) >> \
FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT )
#define FTMCTRL_MCFG1_PROM_WRITE_WS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \
FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) )
#define FTMCTRL_MCFG1_PROM_WRITE_WS( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \
FTMCTRL_MCFG1_PROM_WRITE_WS_MASK )
#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 8
#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0x300U
#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 0
#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0xfU
#define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PROM_READ_WS_MASK ) >> \
FTMCTRL_MCFG1_PROM_READ_WS_SHIFT )