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Remove (unsupported, no toolchain).

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This commit is contained in:
Ralf Corsepius
2010-06-09 04:38:13 +00:00
parent 75ab0720b7
commit e4266e1a60
12 changed files with 0 additions and 2446 deletions
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2
cpukit/score/cpu/nios2/.cvsignore
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Makefile
Makefile.in

100
cpukit/score/cpu/nios2/ChangeLog
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2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com>
* cpu.c, cpu_asm.S, irq.c: Add include of config.h
2009-03-02 Joel Sherrill <joel.sherrill@oarcorp.com>
* cpu_asm.S: Eliminate extern of unused variables.
2009-03-02 Joel Sherrill <joel.sherrill@oarcorp.com>
* cpu.c: Remove stray semi-colon.
2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com>
* cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to
consistently return void * and take a uintptr_t argument.
2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com>
* cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and
passing address of _Thread_Dispatch to _CPU_Initialize. Clean up
comments.
2008-09-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* rtems/score/types.h: Do not define boolean, single_precision,
double_precision unless RTEMS_DEPRECATED_TYPES is given.
2008-09-08 Joel Sherrill <joel.sherrill@oarcorp.com>
* rtems/score/cpu.h: Remove extraneous spaces.
2008-08-21 Ralf Corsépius <ralf.corsepius@rtems.org>
* rtems/score/types.h: Include stdbool.h.
Use bool as base-type for boolean.
2008-07-31 Joel Sherrill <joel.sherrill@OARcorp.com>
* cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com>
* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
parameter to indicate that the port uses the Simple Vectored
Interrupt model or the Programmable Interrupt Controller Model. The
PIC model is implemented primarily in the BSP and it is responsible
for all memory allocation.
2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com>
* rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
2007-12-17 Joel Sherrill <joel.sherrill@OARcorp.com>
* irq.c: Sweep to make sure grep for COPYRIGHT passes.
2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com>
* cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
Table to Configuration Table. Eliminate CPU Table from all ports.
Delete references to CPU Table in all forms.
2007-12-03 Joel Sherrill <joel.sherrill@OARcorp.com>
* rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
the Configuration Table. This included pretasking_hook,
predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
extra_mpci_receive_server_stack, stack_allocate_hook, and
stack_free_hook. As a side-effect of this effort some multiprocessing
code was made conditional and some style clean up occurred.
2007-04-17 Ralf Corsépius <ralf.corsepius@rtems.org>
* rtems/score/cpu.h:
Use Context_Control_fp* instead of void* for fp_contexts.
Eliminate evil casts.
2006-11-17 Ralf Corsépius <ralf.corsepius@rtems.org>
* rtems/score/types.h: Remove unsigned64, signed64.
2006-08-10 Joel Sherrill <joel@OARcorp.com>
* .cvsignore: New file.
2006-08-09 Kolja Waschk <waschk@telos.de>
* rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/nios2.h,
rtems/score/types.h: New files.
2006-08-09 Kolja Waschk <waschk@telos.de>
* ChangeLog, Makefile.am, cpu.c, cpu_asm.S, irq.c, preinstall.am,
rtems/asm.h: New files.
2005-12-09 Kolja Waschk <rtemsdev@ixo.de>
Derived from no_cpu

25
cpukit/score/cpu/nios2/Makefile.am
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##
## $Id$
##
include $(top_srcdir)/automake/compile.am
CLEANFILES =
DISTCLEANFILES =
include_rtemsdir = $(includedir)/rtems
include_rtems_HEADERS = rtems/asm.h
include_rtems_scoredir = $(includedir)/rtems/score
include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/nios2.h \
rtems/score/cpu_asm.h rtems/score/types.h
noinst_LIBRARIES = libscorecpu.a
libscorecpu_a_SOURCES = cpu.c irq.c cpu_asm.S
libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
all-local: $(PREINSTALL_FILES)
include $(srcdir)/preinstall.am
include $(top_srcdir)/automake/local.am

180
cpukit/score/cpu/nios2/cpu.c
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/*
* NIOS2 CPU Dependent Source
*
* COPYRIGHT (c) 1989-2006
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/system.h>
#include <rtems/score/isr.h>
#include <rtems/score/wkspace.h>
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
*
* INPUT PARAMETERS: NONE
*
* NO_CPU Specific Information:
*
* XXX document implementation including references if appropriate
*/
void _CPU_Initialize(void)
{
/*
* If there is not an easy way to initialize the FP context
* during Context_Initialize, then it is usually easier to
* save an "uninitialized" FP context here and copy it to
* the task's during Context_Initialize.
*/
/* FP context initialization support goes here */
}
/*PAGE
*
* _CPU_ISR_Get_level
*
* NO_CPU Specific Information:
*
* XXX document implementation including references if appropriate
*/
uint32_t _CPU_ISR_Get_level( void )
{
/*
* This routine returns the current interrupt level.
*/
return 0;
}
/*PAGE
*
* _CPU_ISR_install_raw_handler
*
* NO_CPU Specific Information:
*
* XXX document implementation including references if appropriate
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
/*
* This is where we install the interrupt handler into the "raw" interrupt
* table used by the CPU to dispatch interrupt handlers.
*/
}
/*PAGE
*
* _CPU_ISR_install_vector
*
* This kernel routine installs the RTEMS handler for the
* specified vector.
*
* Input parameters:
* vector - interrupt vector number
* old_handler - former ISR for this vector number
* new_handler - replacement ISR for this vector number
*
* Output parameters: NONE
*
*
* NO_CPU Specific Information:
*
* XXX document implementation including references if appropriate
*/
void _CPU_ISR_install_vector(
uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
*old_handler = _ISR_Vector_table[ vector ];
/*
* If the interrupt vector table is a table of pointer to isr entry
* points, then we need to install the appropriate RTEMS interrupt
* handler for this vector number.
*/
_CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
/*
* We put the actual user ISR address in '_ISR_vector_table'. This will
* be used by the _ISR_Handler so the user gets control.
*/
_ISR_Vector_table[ vector ] = new_handler;
}
/*PAGE
*
* _CPU_Install_interrupt_stack
*
* NO_CPU Specific Information:
*
* XXX document implementation including references if appropriate
*/
void _CPU_Install_interrupt_stack( void )
{
}
/*PAGE
*
* _CPU_Thread_Idle_body
*
* NOTES:
*
* 1. This is the same as the regular CPU independent algorithm.
*
* 2. If you implement this using a "halt", "idle", or "shutdown"
* instruction, then don't forget to put it in an infinite loop.
*
* 3. Be warned. Some processors with onboard DMA have been known
* to stop the DMA if the CPU were put in IDLE mode. This might
* also be a problem with other on-chip peripherals. So use this
* hook with caution.
*
* NO_CPU Specific Information:
*
* XXX document implementation including references if appropriate
*/
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
#if 1
for(;;);
#else
for(;;)
{
uint32_t st = __builtin_rdctl(0); /* read status register */
/* Differentiate between IRQ off and on (for debugging) */
if(st & 1)
for(;;);
else
for(;;);
/* insert your "halt" instruction here */ ;
}
#endif
}

386
cpukit/score/cpu/nios2/cpu_asm.S
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/*
* $Id$
*
* This file contains all assembly code for the
* NIOS2 implementation of RTEMS.
*
* Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
*
* Derived from no_cpu/cpu_asm.S, copyright (c) 1989-1999,
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/asm.h>
#include <rtems/score/cpu_asm.h>
.set noat
/* ===================================================================== */
/*
* void _CPU_Context_switch( run_context, heir_context )
* void _CPU_Context_restore( run_context, heir_context )
*
* This routine performs a normal non-FP context switch.
*/
.globl _CPU_Context_switch
_CPU_Context_switch:
rdctl r6, status
stw r16, 0(r4)
stw r17, 4(r4)
stw r18, 8(r4)
stw r19, 12(r4)
stw r20, 16(r4)
stw r21, 20(r4)
stw r22, 24(r4)
stw r23, 28(r4)
stw gp, 32(r4)
stw fp, 36(r4)
stw sp, 40(r4)
stw ra, 44(r4)
/* r6 saved status */
stw r6, 48(r4)
_CPU_Context_switch_restore:
ldw r16, 0(r5)
ldw r17, 4(r5)
ldw r18, 8(r5)
ldw r19, 12(r5)
ldw r20, 16(r5)
ldw r21, 20(r5)
ldw r22, 24(r5)
ldw r23, 28(r5)
ldw gp, 32(r5)
ldw fp, 36(r5)
ldw sp, 40(r5)
/* Disable interrupts */
wrctl status, r0
ldw ea, 44(r5)
ldw at, 48(r5)
/* FIXME: Always have interrupts enabled when we return from Context_switch */
ori at, at, 1
wrctl estatus, at
eret
.globl _CPU_Context_restore
_CPU_Context_restore:
/* Copy first to second arg, then re-use 2nd half of Context_switch */
mov r5, r4
br _CPU_Context_switch_restore
/* ===================================================================== */
.globl _exception_vector
_exception_vector:
/*
* First, re-wind so we're pointed to the instruction where the exception
* occurred.
*/
addi ea, ea, -4
/*
* Now test to determine the cause of the exception.
*/
/* TODO: Look at [ea] if there was an unknown/trap instruction */
/* If interrupts are globally disabled, it certainly was no interrupt */
rdctl et, estatus
andi et, et, 1
beq et, zero, _Exception_Handler
/* If no interrupts are pending, it was a software exception */
rdctl et, ipending
beq et, zero, _Exception_Handler
/*
* Falling through to here means that this was a hardware interrupt.
*/
br _ISR_Handler
/* =====================================================================
* Exception handler:
* Responsible for unimplemented instructions and other software
* exceptions. Not responsible for hardware interrupts. Currently,
* software exceptions are regarded as error conditions, and the
* handling isn't perfect. */
_Exception_Handler:
/* stw et, 108(sp') => stw et, -20(sp) */
stw et, -20(sp)
mov et, sp
addi sp, sp, -128
stw r1, 0(sp)
stw r2, 4(sp)
stw r3, 8(sp)
rdctl r1, estatus
rdctl r2, ienable
rdctl r3, ipending
stw r4, 12(sp)
stw r5, 16(sp)
stw r6, 20(sp)
stw r7, 24(sp)
stw r8, 28(sp)
stw r9, 32(sp)
stw r10, 36(sp)
stw r11, 40(sp)
stw r12, 44(sp)
stw r13, 48(sp)
stw r14, 52(sp)
stw r15, 56(sp)
stw r16, 60(sp)
stw r17, 64(sp)
stw r18, 68(sp)
stw r19, 72(sp)
stw r20, 76(sp)
stw r21, 80(sp)
stw r22, 84(sp)
stw r23, 88(sp)
stw gp, 92(sp)
stw fp, 96(sp)
/* sp */
stw et, 100(sp)
stw ra, 104(sp)
/* stw et, 108(sp) */
stw ea, 112(sp)
/* status */
stw r1, 116(sp)
/* ienable */
stw r2, 120(sp)
/* ipending */
stw r3, 124(sp)
/*
* Restore the global pointer.
*/
movhi gp, %hiadj(_gp)
addi gp, gp, %lo(_gp)
/*
* Pass a pointer to the stack frame as the input argument of the
* exception handler (CPU_Exception_frame *).
*/
mov r4, sp
/*
* Call the exception handler.
*/
.extern __Exception_Handler
call __Exception_Handler
stuck_in_exception:
br stuck_in_exception
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
ldw r1, 0(sp)
ldw r2, 4(sp)
ldw r3, 8(sp)
ldw r4, 12(sp)
ldw r5, 16(sp)
ldw r6, 20(sp)
ldw r7, 24(sp)
ldw r8, 28(sp)
ldw r9, 32(sp)
ldw r10, 36(sp)
ldw r11, 40(sp)
ldw r12, 44(sp)
ldw r13, 48(sp)
ldw r14, 52(sp)
ldw r15, 56(sp)
ldw r16, 60(sp)
ldw r17, 64(sp)
ldw r18, 68(sp)
ldw r19, 72(sp)
ldw r20, 76(sp)
ldw r21, 80(sp)
ldw r22, 84(sp)
ldw r23, 88(sp)
ldw gp, 92(sp)
ldw fp, 96(sp)
ldw ra, 104(sp)
/* Disable interrupts */
wrctl status, r0
ldw ea, 112(sp)
ldw et, 116(sp)
/* FIXME: Enable interrupts after exception processing */
ori et, et, 1
wrctl estatus, et
ldw et, 108(sp)
/* Restore stack pointer */
ldw sp, 100(sp)
eret
/* ===================================================================== */
.section .text
_ISR_Handler:
/*
* Process an external hardware interrupt.
*
* First, preserve all callee saved registers on
* the stack. (See the Nios2 ABI documentation for details).
*
* Do we really need to save all?
*
* If this is interrupting a task (and not another interrupt),
* everything is saved into the task's stack, thus putting us
* in a situation similar to when the task calls a subroutine
* (and only the CPU_Context_Control subset needs to be changed)
*/
rdctl et, estatus
/* Keep this in the same order as CPU_Interrupt_frame: */
addi sp, sp, -76
stw r1, 0(sp)
stw r2, 4(sp)
stw r3, 8(sp)
stw r4, 12(sp)
stw r5, 16(sp)
stw r6, 20(sp)
stw r7, 24(sp)
stw r8, 28(sp)
stw r9, 32(sp)
stw r10, 36(sp)
stw r11, 40(sp)
stw r12, 44(sp)
stw r13, 48(sp)
stw r14, 52(sp)
stw r15, 56(sp)
stw ra, 60(sp)
stw gp, 64(sp)
/* et contains status */
stw et, 68(sp)
stw ea, 72(sp)
/*
* Obtain a bitlist of the pending interrupts.
*/
rdctl et, ipending
/*
* Restore the global pointer to the expected value.
*/
movhi gp, %hiadj(_gp)
addi gp, gp, %lo(_gp)
/*
* Search through the bit list stored in r24(et) to find the first enabled
* bit. The offset of this bit is the index of the interrupt that is
* to be handled.
*/
mov r4, zero
6:
andi r3, r24, 1
bne r3, zero, 7f
addi r4, r4, 1
srli r24, r24, 1
br 6b
7:
/*
* Having located the interrupt source, r4 contains the index of the
* interrupt to be handled. r5, the 2nd argument to the function,
* will point to the CPU_Interrupt_frame.
*/
mov r5, sp
.extern __ISR_Handler
call __ISR_Handler
/*
* Now that the interrupt processing is complete, prepare to return to
* the interrupted code.
*/
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
ldw r1, 0(sp)
ldw r2, 4(sp)
ldw r3, 8(sp)
ldw r4, 12(sp)
ldw r5, 16(sp)
ldw r6, 20(sp)
ldw r7, 24(sp)
ldw r8, 28(sp)
ldw r9, 32(sp)
ldw r10, 36(sp)
ldw r11, 40(sp)
ldw r12, 44(sp)
ldw r13, 48(sp)
ldw r14, 52(sp)
ldw r15, 56(sp)
ldw ra, 60(sp)
ldw gp, 64(sp)
/* Disable interrupts */
wrctl status, r0
/* Restore the exception registers */
/* load saved ea into ea */
ldw ea, 72(sp)
/* load saved estatus into et */
ldw et, 68(sp)
/* Always have interrupts enabled when we return from interrupt */
ori et, et, 1
wrctl estatus, et
/* Restore the stack pointer */
addi sp, sp, 76
/*
* Return to the interrupted instruction.
*/
eret

98
cpukit/score/cpu/nios2/irq.c
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/*
* NIOS2 exception and interrupt handler
*
* Derived from c4x/irq.c
*
* COPYRIGHT (c) 1989-2007.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/system.h>
#include <rtems/score/cpu.h>
#include <rtems/score/isr.h>
#include <rtems/score/thread.h>
/*
* This routine provides the RTEMS interrupt management.
*
* Upon entry, interrupts are disabled
*/
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
unsigned long *_old_stack_ptr;
#endif
register unsigned long *stack_ptr asm("sp");
void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
{
register uint32_t level;
/* Interrupts are disabled upon entry to this Handler */
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if ( _ISR_Nest_level == 0 ) {
/* Install irq stack */
_old_stack_ptr = stack_ptr;
stack_ptr = _CPU_Interrupt_stack_high - 4;
}
#endif
_ISR_Nest_level++;
_Thread_Dispatch_disable_level++;
if ( _ISR_Vector_table[ vector] )
{
(*_ISR_Vector_table[ vector ])(vector, ifr);
};
/* Make sure that interrupts are disabled again */
_CPU_ISR_Disable( level );
_Thread_Dispatch_disable_level--;
_ISR_Nest_level--;
if( _ISR_Nest_level == 0)
{
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
stack_ptr = _old_stack_ptr;
#endif
if( _Thread_Dispatch_disable_level == 0 )
{
if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing )
{
_ISR_Signals_to_thread_executing = FALSE;
_CPU_ISR_Enable( level );
_Thread_Dispatch();
/* may have switched to another task and not return here immed. */
_CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */
}
}
else
{
_ISR_Signals_to_thread_executing = FALSE;
};
};
_CPU_ISR_Enable( level );
}
void __Exception_Handler(CPU_Exception_frame *efr)
{
_CPU_Fatal_halt(0xECC0);
}

45
cpukit/score/cpu/nios2/preinstall.am
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@@ -1,45 +0,0 @@
## Automatically generated by ampolish3 - Do not edit
if AMPOLISH3
$(srcdir)/preinstall.am: Makefile.am
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
endif
PREINSTALL_DIRS =
DISTCLEANFILES += $(PREINSTALL_DIRS)
all-am: $(PREINSTALL_FILES)
PREINSTALL_FILES =
CLEANFILES += $(PREINSTALL_FILES)
$(PROJECT_INCLUDE)/rtems/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
$(PROJECT_INCLUDE)/rtems/score/nios2.h: rtems/score/nios2.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/nios2.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/nios2.h
$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h

97
cpukit/score/cpu/nios2/rtems/asm.h
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/**
* @file rtems/asm.h
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*/
/*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*
* COPYRIGHT (c) 1994-1997.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#ifndef _RTEMS_ASM_H
#define _RTEMS_ASM_H
/*
* Indicate we are in an assembly file and get the basic CPU definitions.
*/
#ifndef ASM
#define ASM
#endif
#include <rtems/score/cpuopts.h>
#include <rtems/score/nios2.h>
/*
* Recent versions of GNU cpp define variables which indicate the
* need for underscores and percents. If not using GNU cpp or
* the version does not support this, then you will obviously
* have to define these as appropriate.
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
#define __REGISTER_PREFIX__
#endif
#include <rtems/concat.h>
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
*
* EXAMPLE: #define d0 REG (d0)
*/
/*
* Define macros to handle section beginning and ends.
*/
#define BEGIN_CODE_DCL .text
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
#define BEGIN_CODE .text
#define END_CODE
#define BEGIN_DATA
#define END_DATA
#define BEGIN_BSS
#define END_BSS
#define END
/*
* Following must be tailor for a particular flavor of the C compiler.
* They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .globl SYM (sym)
#define EXTERN(sym) .globl SYM (sym)
#endif

1326
cpukit/score/cpu/nios2/rtems/score/cpu.h
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74
cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
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@@ -1,74 +0,0 @@
/**
* @file rtems/score/cpu_asm.h
*/
/*
* Very loose template for an include file for the cpu_asm.? file
* if it is implemented as a ".S" file (preprocessed by cpp) instead
* of a ".s" file (preprocessed by gm4 or gasp).
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*
*/
#ifndef _RTEMS_SCORE_CPU_ASM_H
#define _RTEMS_SCORE_CPU_ASM_H
/* pull in the generated offsets */
/*
#include <rtems/score/offsets.h>
*/
/*
* Hardware General Registers
*/
/* put something here */
/*
* Hardware Floating Point Registers
*/
/* put something here */
/*
* Hardware Control Registers
*/
/* put something here */
/*
* Calling Convention
*/
/* put something here */
/*
* Temporary registers
*/
/* put something here */
/*
* Floating Point Registers - SW Conventions
*/
/* put something here */
/*
* Temporary floating point registers
*/
/* put something here */
#endif
/* end of file */

62
cpukit/score/cpu/nios2/rtems/score/nios2.h
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/* nios2.h
*
* This file sets up basic CPU dependency settings based on
* compiler settings. For example, it can determine if
* floating point is available. This particular implementation
* is specific to the NIOS2 port.
*
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*
*/
#ifndef _RTEMS_SCORE_NIOS2_H
#define _RTEMS_SCORE_NIOS2_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the NIOS2 family.
* It does this by setting variables to indicate which
* implementation dependent features are present in a particular
* member of the family.
*
* This is a good place to list all the known CPU models
* that this port supports and which RTEMS CPU model they correspond
* to.
*/
/*
* Define the name of the CPU family and specific model.
*/
#define CPU_NAME "NIOS2"
#define CPU_MODEL_NAME "nios2"
/*
* See also nios2-rtems-gcc -print-multi-lib for all valid combinations of
*
* -mno-hw-mul
* -mhw-mulx
* -mstack-check
* -pg
* -EB
* -mcustom-fpu-cfg=60-1
* -mcustom-fpu-cfg=60-2
*/
#ifdef __cplusplus
}
#endif
#endif /* _RTEMS_SCORE_NIOS2_H */

51
cpukit/score/cpu/nios2/rtems/score/types.h
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/**
* @file rtems/score/types.h
*/
/*
* This include file contains type definitions pertaining to the
* Altera Nios II processor family.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef _RTEMS_SCORE_TYPES_H
#define _RTEMS_SCORE_TYPES_H
#ifndef ASM
#include <stdbool.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef uint16_t Priority_Bit_map_control;
typedef void nios2_isr;
typedef void ( *nios2_isr_entry )( void );
#ifdef RTEMS_DEPRECATED_TYPES
typedef bool boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
#endif
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif