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2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* configure.ac, startup/bspstart.c, include/coverhd.h: Use standard
	cache BSP options.
This commit is contained in:
Sebastian Huber
2011-06-07 13:32:31 +00:00
parent b6027474f6
commit e3cb4aae28
4 changed files with 16 additions and 21 deletions
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5
c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
View File

@@ -1,3 +1,8 @@
2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.ac, startup/bspstart.c, include/coverhd.h: Use standard
cache BSP options.
2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* console/console.c, irq/irq.c:

20
c/src/lib/libbsp/powerpc/mbx8xx/configure.ac
View File

@@ -18,22 +18,12 @@ RTEMS_PROG_CCAS
RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[mbx860_005b],[0])
RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[1])
RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
[If defined, then the PowerPC specific code in RTEMS will use
data cache instructions to optimize the context switch code.
This code can conflict with debuggers or emulators.])
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mbx860_005b],[])
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
RTEMS_BSPOPTS_SET([DATA_CACHE_ENABLE],[*],[1])
RTEMS_BSPOPTS_HELP([DATA_CACHE_ENABLE],
[If defined, the data cache will be enabled after address translation
is turned on.])
RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[1])
RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
[If defined, the instruction cache will be enabled after address translation
is turned on.])
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([NVRAM_CONFIGURE],[mbx860_005b],[0])
RTEMS_BSPOPTS_SET([NVRAM_CONFIGURE],[*],[1])

8
c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h
View File

@@ -32,7 +32,7 @@ extern "C" {
#endif
#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
#if defined( INSTRUCTION_CACHE_ENABLE )
#if BSP_INSTRUCTION_CACHE_ENABLED
/*
* 50 MHz processor, cache enabled.
*/
@@ -190,10 +190,10 @@ extern "C" {
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 5
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3
#endif /* defined( INSTRUCTION_CACHE_ENABLE ) */
#endif /* BSP_INSTRUCTION_CACHE_ENABLED */
#else
#if defined( INSTRUCTION_CACHE_ENABLE )
#if BSP_INSTRUCTION_CACHE_ENABLED
/*
* 40 MHz processor, cache enabled.
*/
@@ -351,7 +351,7 @@ extern "C" {
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3
#endif /* defined( INSTRUCTION_CACHE_ENABLE ) */
#endif /* BSP_INSTRUCTION_CACHE_ENABLED */
#endif

4
c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
View File

@@ -106,10 +106,10 @@ void bsp_start(void)
if ( nvram->cache_mode & 0x01 )
rtems_cache_enable_data();
#else
#ifdef INSTRUCTION_CACHE_ENABLE
#if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
#ifdef DATA_CACHE_ENABLE
#if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
#endif