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2008-09-03 Joel Sherrill <joel.sherrill@OARcorp.com>

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* Makefile.am, configure.ac, console/alloc360.c, console/console.c,
	console/console.h, console/m68360.h, console/mc68360_scc.c,
	console/ns16550cfg.c, console/rsPMCQ1.c, console/rsPMCQ1.h,
	include/bsp.h, irq/irq_init.c, vme/VMEConfig.h: Initiate update and
	testing. Add missing files. Does not run hello yet.
	* console/debugio.c, console/polled_io.c, irq/openpic_xxx_irq.c: New files.
This commit is contained in:
Joel Sherrill
2008-09-03 20:35:43 +00:00
parent 4598164a0b
commit e36390a662
17 changed files with 1939 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
c/src/lib/libbsp/powerpc/ep1a/ChangeLog
View File

@@ -1,3 +1,12 @@
2008-09-03 Joel Sherrill <joel.sherrill@OARcorp.com>
* Makefile.am, configure.ac, console/alloc360.c, console/console.c,
console/console.h, console/m68360.h, console/mc68360_scc.c,
console/ns16550cfg.c, console/rsPMCQ1.c, console/rsPMCQ1.h,
include/bsp.h, irq/irq_init.c, vme/VMEConfig.h: Initiate update and
testing. Add missing files. Does not run hello yet.
* console/debugio.c, console/polled_io.c, irq/openpic_xxx_irq.c: New files.
2008-08-20 Ralf Corsépius <ralf.corsepius@rtems.org>
* console/mc68360_scc.c, console/rsPMCQ1.c, console/rsPMCQ1.h,

2
c/src/lib/libbsp/powerpc/ep1a/Makefile.am
View File

@@ -54,7 +54,7 @@ include_bsp_HEADERS += ../../powerpc/shared/irq/irq.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
irq_SOURCES = irq/irq_init.c ../shared/irq/openpic_i8259_irq.c ../../powerpc/shared/irq/i8259.c
irq_SOURCES = irq/irq_init.c irq/openpic_xxx_irq.c ../../powerpc/shared/irq/i8259.c
include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
vme/VMEConfig.h \

14
c/src/lib/libbsp/powerpc/ep1a/configure.ac
View File

@@ -15,6 +15,20 @@ RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
[If defined, then the PowerPC specific code in RTEMS will use
data cache instructions to optimize the context switch code.
This code can conflict with debuggers or emulators. It is known
to break the Corelis PowerPC emulator with at least some combinations
of PowerPC 603e revisions and emulator versions.
The BSP actually contains the call that enables this.])
RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[0])
RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
[If defined, the instruction cache will be enabled after address translation
is turned on.])
RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
[whether using console interrupts])

9
c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c
View File

@@ -7,7 +7,7 @@
* Saskatoon, Saskatchewan, CANADA
* eric@skatter.usask.ca
*
* COPYRIGHT (c) 1989-1999.
* COPYRIGHT (c) 2008.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -24,11 +24,18 @@
#include "rsPMCQ1.h"
#include <rtems/bspIo.h>
#define DEBUG_PRINT 1
void M360SetupMemory( M68360_t ptr ){
volatile m360_t *m360;
m360 = ptr->m360;
#if DEBUG_PRINT
printk("m360->mcr:0x%08x Q1_360_SIM_MCR:0x%08x\n",
(unsigned int)&(m360->mcr), ((unsigned int)m360+Q1_360_SIM_MCR));
#endif
ptr->bdregions[0].base = (char *)&m360->dpram1[0];
ptr->bdregions[0].size = sizeof m360->dpram1;
ptr->bdregions[0].used = 0;

81
c/src/lib/libbsp/powerpc/ep1a/console/console.c
View File

@@ -1,9 +1,9 @@
/*
/*XXX
* This file contains the TTY driver for the ep1a
*
* This driver uses the termios pseudo driver.
*
* COPYRIGHT (c) 1989-1999.
* COPYRIGHT (c) 2008.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -241,6 +241,83 @@ rtems_device_driver console_initialize(
return RTEMS_SUCCESSFUL;
}
#if 0
/* PAGE
*
* DEBUG_puts
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* string - pointer to debug output string
*
* Output parameters: NONE
*
* Return values: NONE
*/
void DEBUG_puts(
char *string
)
{
char *s;
unsigned32 Irql;
rtems_interrupt_disable(Irql);
for ( s = string ; *s ; s++ )
{
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor, *s);
}
rtems_interrupt_enable(Irql);
}
/* PAGE
*
* DEBUG_puth
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* ulHexNum - value to display
*
* Output parameters: NONE
*
* Return values: NONE
*/
void
DEBUG_puth(
unsigned32 ulHexNum
)
{
unsigned long i,d;
unsigned32 Irql;
rtems_interrupt_disable(Irql);
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor, '0');
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor, 'x');
for(i=32;i;)
{
i-=4;
d=(ulHexNum>>i)&0xf;
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor,
(d<=9) ? d+'0' : d+'a'-0xa);
}
rtems_interrupt_enable(Irql);
}
#endif
/* const char arg to be compatible with BSP_output_char decl. */
void

4
c/src/lib/libbsp/powerpc/ep1a/console/console.h
View File

@@ -17,7 +17,7 @@
* no support for this code.
*
*
* COPYRIGHT (c) 1989-1999.
* COPYRIGHT (c) 1989-2008.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -25,7 +25,7 @@
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
*/
#include <rtems/ringbuf.h>
#include <libchip/serial.h>

113
c/src/lib/libbsp/powerpc/ep1a/console/debugio.c Normal file
View File

@@ -0,0 +1,113 @@
/*
* This file contains the debug IO support.
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* debugio.c,v 1.2.4.1 2003/09/04 18:45:11 joel Exp
*/
#include <bsp.h>
#include <rtems/libio.h>
#include <stdlib.h>
#include <assert.h>
#include <termios.h>
#include <libchip/serial.h>
/*
* Load configuration table
*/
extern console_data Console_Port_Data[];
extern rtems_device_minor_number Console_Port_Minor;
/* PAGE
*
* DEBUG_puts
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* string - pointer to debug output string
*
* Output parameters: NONE
*
* Return values: NONE
*/
void DEBUG_puts(
char *string
)
{
char *s;
unsigned32 Irql;
rtems_interrupt_disable(Irql);
for ( s = string ; *s ; s++ ) {
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor, *s);
}
rtems_interrupt_enable(Irql);
}
/* PAGE
*
* DEBUG_puth
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* ulHexNum - value to display
*
* Output parameters: NONE
*
* Return values: NONE
*/
void DEBUG_puth(
unsigned32 ulHexNum
)
{
unsigned long i,d;
unsigned32 Irql;
void (*poll)(int minor, char cChar);
poll = Console_Port_Tbl[Console_Port_Minor].pDeviceFns->deviceWritePolled;
rtems_interrupt_disable(Irql);
(*poll)(Console_Port_Minor, '0');
(*poll)(Console_Port_Minor, 'x');
for ( i=32 ; i ; ) {
i -= 4;
d = (ulHexNum>>i)&0xf;
(*poll)(Console_Port_Minor, (d<=9) ? d+'0' : d+'a'-0xa);
}
rtems_interrupt_enable(Irql);
}

15
c/src/lib/libbsp/powerpc/ep1a/console/m68360.h
View File

@@ -48,15 +48,22 @@ typedef struct m360MEMCRegisters_ {
#define M360_GSMR_RFW 0x00000020
#define M360_GSMR_RINV 0x02000000
#define M360_GSMR_TINV 0x01000000
#define M360_GSMR_TDCR_16X 0x00020000
#define M360_GSMR_RDCR_16X 0x00008000
#define M360_GSMR_MODE_UART 0x00000004
#define M360_GSMR_DIAG_LLOOP 0x00000040
#define M360_GSMR_ENR 0x00000020
#define M360_GSMR_ENT 0x00000010
#define M360_GSMR_MODE_UART 0x00000004
#define M360_PSMR_FLC 0x8000
#define M360_PSMR_SL 0x4000
#define M360_PSMR_SL_1 0x0000
#define M360_PSMR_SL_2 0x4000
#define M360_PSMR_CL5 0x0000
#define M360_PSMR_CL6 0x1000
#define M360_PSMR_CL7 0x2000
#define M360_PSMR_CL8 0x3000
#define M360_PSMR_UM_NORMAL 0x0000
#define M360_PSMR_FRZ 0x0200
@@ -970,4 +977,8 @@ void *M360AllocateBufferDescriptors (M68360_t ptr, int count);
void M360ExecuteRISC( volatile m360_t *m360, uint16_t command);
int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector );
#if 0
extern volatile m360_t *m360;
#endif
#endif /* __MC68360_h */

202
c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c
View File

@@ -1,6 +1,7 @@
/* This file contains the termios TTY driver for the Motorola MC68360 SCC ports.
/* This file contains the termios TTY driver for the
* Motorola MC68360 SCC ports.
*
* COPYRIGHT (c) 1989-1999.
* COPYRIGHT (c) 1989-2008.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -22,23 +23,33 @@
#include <libchip/sersupp.h>
#include <stdlib.h>
#include <rtems/bspIo.h>
#include <rtems/termiostypes.h>
#include <string.h>
#define MC68360_LENGHT_SIZE 100
int mc68360_length_array[ MC68360_LENGHT_SIZE ];
#if 0
#define DEBUG_360
#endif
#if 1 /* XXX */
int EP1A_READ_LENGTH_GREATER_THAN_1 = 0;
#define MC68360_LENGTH_SIZE 400
int mc68360_length_array[ MC68360_LENGTH_SIZE ];
int mc68360_length_count=0;
void mc68360_Show_length_array(void) {
int i;
for (i=0; i<MC68360_LENGHT_SIZE; i++)
for (i=0; i<MC68360_LENGTH_SIZE; i++)
printf(" %d", mc68360_length_array[i] );
printf("\n\n");
}
#endif
M68360_t M68360_chips = NULL;
#define SYNC eieio
#define mc68360_scc_Is_422( _minor ) (Console_Port_Tbl[minor].sDeviceName[7] == '4' )
void mc68360_scc_nullFunc(void) {}
@@ -171,6 +182,20 @@ static int
mc68360_sccBRGC(int baud, int m360_clock_rate)
{
int data;
#if 0
int divisor;
int div16;
div16 = 0;
divisor = ((m360_clock_rate / 16) + (baud / 2)) / baud;
if (divisor > 4096)
{
div16 = 1;
divisor = (divisor + 8) / 16;
}
return(M360_BRG_EN | M360_BRG_EXTC_BRGCLK |
((divisor - 1) << 1) | div16);
#endif
/*
* configure baud rate generator for 16x bit rate, where.....
@@ -214,7 +239,7 @@ mc68360_sccBRGC(int baud, int m360_clock_rate)
* none *
* *
**************************************************************************/
void mc68360_sccInterruptHandler( rtems_irq_hdl_param handle )
void mc68360_sccInterruptHandler( M68360_t chip )
{
volatile m360_t *m360;
int port;
@@ -223,13 +248,22 @@ void mc68360_sccInterruptHandler( rtems_irq_hdl_param handle )
int i;
char data;
int clear_isr;
M68360_t chip = (M68360_t)handle;
#ifdef DEBUG_360
printk("mc68360_sccInterruptHandler\n");
#endif
for (port=0; port<4; port++) {
clear_isr = FALSE;
m360 = chip->m360;
/*
* XXX - Can we add something here to check if this is our interrupt.
* XXX - We need a parameter here so that we know which 360 instead of
* looping through them all!
*/
/*
* Handle a RX interrupt.
*/
@@ -241,6 +275,9 @@ void mc68360_sccInterruptHandler( rtems_irq_hdl_param handle )
while ((status & M360_BD_EMPTY) == 0)
{
length= scc_read16("sccRxBd->length",&chip->port[port].sccRxBd->length);
if (length > 1)
EP1A_READ_LENGTH_GREATER_THAN_1 = length;
for (i=0;i<length;i++) {
data= chip->port[port].rxBuf[i];
rtems_termios_enqueue_raw_characters(
@@ -265,9 +302,13 @@ void mc68360_sccInterruptHandler( rtems_irq_hdl_param handle )
if ((status & M360_BD_EMPTY) == 0)
{
scc_write16("sccTxBd->status",&chip->port[port].sccTxBd->status,0);
#if 1
rtems_termios_dequeue_characters(
Console_Port_Data[chip->port[port].minor].termios_data,
chip->port[port].sccTxBd->length);
#else
mc68360_scc_write_support_int(chip->port[port].minor,"*****", 5);
#endif
}
}
@@ -293,10 +334,57 @@ int mc68360_scc_open(
void * arg
)
{
M68360_serial_ports_t ptr;
volatile m360_t *m360;
uint32_t data;
#ifdef DEBUG_360
printk("mc68360_scc_open %d\n", minor);
#endif
ptr = Console_Port_Tbl[minor].pDeviceParams;
m360 = ptr->chip->m360;
/*
* Enable the receiver and the transmitter.
*/
SYNC();
data = scc_read32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l);
scc_write32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l,
(data | M360_GSMR_ENR | M360_GSMR_ENT) );
data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK );
data &= (~PMCQ1_INT_MASK_QUICC);
PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK, data );
data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS );
data &= (~PMCQ1_INT_STATUS_QUICC);
PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS, data );
return RTEMS_SUCCESSFUL;
}
uint32_t mc68360_scc_calculate_pbdat( M68360_t chip )
{
uint32_t i;
uint32_t pbdat_data;
int minor;
uint32_t type422data[4] = {
0x00440, 0x00880, 0x10100, 0x20200
};
pbdat_data = 0x3;
for (i=0; i<4; i++) {
minor = chip->port[i].minor;
if mc68360_scc_Is_422( minor )
pbdat_data |= type422data[i];
}
return pbdat_data;
}
/*
* mc68360_scc_initialize_interrupts
*
@@ -320,6 +408,7 @@ void mc68360_scc_initialize_interrupts(int minor)
ptr = Console_Port_Tbl[minor].pDeviceParams;
m360 = ptr->chip->m360;
#ifdef DEBUG_360
printk("m360 0x%08x baseaddr 0x%08x\n",
m360, ptr->chip->board_data->baseaddr);
@@ -337,8 +426,8 @@ void mc68360_scc_initialize_interrupts(int minor)
*/
data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_DRIVER_ENABLE );
SYNC();
data |= (PMCQ1_DRIVER_ENABLE_3 | PMCQ1_DRIVER_ENABLE_2 |
PMCQ1_DRIVER_ENABLE_1 | PMCQ1_DRIVER_ENABLE_0);
data = data & ~(PMCQ1_DRIVER_ENABLE_3 | PMCQ1_DRIVER_ENABLE_2 |
PMCQ1_DRIVER_ENABLE_1 | PMCQ1_DRIVER_ENABLE_0);
PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_DRIVER_ENABLE, data);
data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_DRIVER_ENABLE );
SYNC();
@@ -383,10 +472,21 @@ void mc68360_scc_initialize_interrupts(int minor)
/*
* XXX
*/
#if 0
scc_write32( "pbpar", &m360->pbpar, 0x00000000 );
scc_write32( "pbdir", &m360->pbdir, 0x0003ffff );
scc_write32( "pbdat", &m360->pbdat, 0x0000003f );
SYNC();
#else
data = mc68360_scc_calculate_pbdat( ptr->chip );
scc_write32( "pbpar", &m360->pbpar, 0x00000000 );
scc_write32( "pbdat", &m360->pbdat, data );
SYNC();
scc_write32( "pbdir", &m360->pbdir, 0x0003fc3 );
SYNC();
#endif
/*
* XXX
@@ -529,6 +629,7 @@ void mc68360_scc_initialize_interrupts(int minor)
(M360_PSMR_CL8 | M360_PSMR_UM_NORMAL | M360_PSMR_TPM_ODD) );
SYNC();
#if 0 /* XXX - ??? */
/*
* Enable the receiver and the transmitter.
*/
@@ -536,7 +637,7 @@ void mc68360_scc_initialize_interrupts(int minor)
SYNC();
data = scc_read32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l);
scc_write32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l,
(data | M360_GSMR_ENR | M360_GSMR_ENT) );
(data | M360_GSMR_ENR | M360_GSMR_ENT) );
data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK );
data &= (~PMCQ1_INT_MASK_QUICC);
@@ -545,6 +646,7 @@ void mc68360_scc_initialize_interrupts(int minor)
data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS );
data &= (~PMCQ1_INT_STATUS_QUICC);
PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS, data );
#endif
}
/*
@@ -562,10 +664,12 @@ int mc68360_scc_write_support_int(
rtems_interrupt_level Irql;
M68360_serial_ports_t ptr;
#if 1
mc68360_length_array[ mc68360_length_count ] = len;
mc68360_length_count++;
if ( mc68360_length_count >= MC68360_LENGHT_SIZE )
if ( mc68360_length_count >= MC68360_LENGTH_SIZE )
mc68360_length_count=0;
#endif
ptr = Console_Port_Tbl[minor].pDeviceParams;
@@ -634,12 +738,41 @@ int mc68360_scc_set_attributes(
int baud;
volatile m360_t *m360;
M68360_serial_ports_t ptr;
uint16_t value;
#ifdef DEBUG_360
printk("mc68360_scc_set_attributes\n");
#endif
ptr = Console_Port_Tbl[minor].pDeviceParams;
m360 = ptr->chip->m360;
baud = termios_baud_to_number(t->c_cflag & CBAUD);
if (baud > 0) {
switch (t->c_cflag & CBAUD)
{
case B50: baud = 50; break;
case B75: baud = 75; break;
case B110: baud = 110; break;
case B134: baud = 134; break;
case B150: baud = 150; break;
case B200: baud = 200; break;
case B300: baud = 300; break;
case B600: baud = 600; break;
case B1200: baud = 1200; break;
case B1800: baud = 1800; break;
case B2400: baud = 2400; break;
case B4800: baud = 4800; break;
case B9600: baud = 9600; break;
case B19200: baud = 19200; break;
case B38400: baud = 38400; break;
case B57600: baud = 57600; break;
case B115200: baud = 115200; break;
case B230400: baud = 230400; break;
case B460800: baud = 460800; break;
default: baud = -1; break;
}
if (baud > 0)
{
scc_write32(
"pBRGC",
ptr->pBRGC,
@@ -647,6 +780,47 @@ int mc68360_scc_set_attributes(
);
}
/* Initial value of PSMR should be 0 */
value = M360_PSMR_UM_NORMAL;
/* set the number of data bits, 8 is most common */
if (t->c_cflag & CSIZE) /* was it specified? */
{
switch (t->c_cflag & CSIZE) {
case CS5: value |= M360_PSMR_CL5; break;
case CS6: value |= M360_PSMR_CL6; break;
case CS7: value |= M360_PSMR_CL7; break;
case CS8: value |= M360_PSMR_CL8; break;
}
} else {
value |= M360_PSMR_CL8; /* default to 8 data bits */
}
/* the number of stop bits */
if (t->c_cflag & CSTOPB)
value |= M360_PSMR_SL_2; /* Two stop bits */
else
value |= M360_PSMR_SL_1; /* One stop bit */
/* Set Parity M360_PSMR_PEN bit should be clear on no parity so
* do nothing in that case
*/
if (t->c_cflag & PARENB) /* enable parity detection? */
{
value |= M360_PSMR_PEN;
if (t->c_cflag & PARODD){
value |= M360_PSMR_RPM_ODD; /* select odd parity */
value |= M360_PSMR_TPM_ODD;
} else {
value |= M360_PSMR_RPM_EVEN; /* select even parity */
value |= M360_PSMR_TPM_EVEN;
}
}
SYNC();
scc_write16( "pSCCR->psmr", &ptr->pSCCR->psmr, value );
SYNC();
return 0;
}

9
c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.c
View File

@@ -26,7 +26,7 @@ uint8_t Read_ns16550_register(
uint8_t ucRegNum
)
{
struct uart_reg *p = (struct uart_reg *)ulCtrlPort;
volatile struct uart_reg *p = (volatile struct uart_reg *)ulCtrlPort;
uint8_t ucData;
ucData = p[ucRegNum].reg;
asm volatile("sync");
@@ -39,9 +39,12 @@ void Write_ns16550_register(
uint8_t ucData
)
{
struct uart_reg *p = (struct uart_reg *)ulCtrlPort;
volatile struct uart_reg *p = (volatile struct uart_reg *)ulCtrlPort;
volatile int i;
p[ucRegNum].reg = ucData;
asm volatile("sync");
for (i=0;i<0x08ff;i++);
asm volatile("isync");
asm volatile("eieio");
for (i=0;i<0x08ff;i++)
asm volatile("isync");
}

1130
c/src/lib/libbsp/powerpc/ep1a/console/polled_io.c Normal file
View File

File diff suppressed because it is too large Load Diff

61
c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c
View File

@@ -41,7 +41,7 @@ call rsPMCQ1Init() to perform ba sic initialisation of the PMCQ1's.
#include "m68360.h"
/* defines */
#if 0
#if 1
#define DEBUG_360
#endif
@@ -115,9 +115,10 @@ void rsPMCQ1_scc_nullFunc(void) {}
void rsPMCQ1Int( void *ptr )
{
unsigned long status;
unsigned long status1;
unsigned long mask;
unsigned long status;
unsigned long status1;
unsigned long mask;
uint32_t data;
PPMCQ1BoardData boardData = ptr;
status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
@@ -129,7 +130,7 @@ void rsPMCQ1Int( void *ptr )
if (boardData->quiccInt) {
boardData->quiccInt(boardData->quiccArg);
} else {
*(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
*(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
}
}
@@ -138,16 +139,25 @@ void rsPMCQ1Int( void *ptr )
/* If there is a handler call it otherwise mask the interrupt */
if (boardData->maInt) {
boardData->maInt(boardData->maArg);
data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
data &= (~PMCQ1_INT_STATUS_MA);
PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data );
} else {
*(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
*(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
}
}
RTEMS_COMPILER_MEMORY_BARRIER();
/* Clear Interrupt on QSPAN */
*(unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000;
*(volatile unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000;
/* read back the status register to ensure that the pci write has completed */
status1 = *(volatile unsigned long *)(boardData->bridgeaddr + 0x600);
RTEMS_COMPILER_MEMORY_BARRIER();
}
@@ -165,12 +175,13 @@ unsigned int rsPMCQ1MaIntConnect (
unsigned long busNo, /* Pci Bus number of PMCQ1 */
unsigned long slotNo, /* Pci Slot number of PMCQ1 */
unsigned long funcNo, /* Pci Function number of PMCQ1 */
rtems_irq_hdl routine,/* interrupt routine */
rtems_irq_hdl_param arg /* argument to pass to interrupt routine */
FUNCION_PTR routine,/* interrupt routine */
int arg /* argument to pass to interrupt routine */
)
{
PPMCQ1BoardData boardData;
unsigned int status = RTEMS_IO_ERROR;
uint32_t data;
unsigned int status = RTEMS_IO_ERROR;
for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)
{
@@ -179,6 +190,15 @@ unsigned int rsPMCQ1MaIntConnect (
{
boardData->maInt = routine;
boardData->maArg = arg;
data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );
data &= (~PMCQ1_INT_MASK_MA);
PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_MASK, data );
data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
data &= (~PMCQ1_INT_STATUS_MA);
PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data );
status = RTEMS_SUCCESSFUL;
break;
}
@@ -234,8 +254,8 @@ unsigned int rsPMCQ1QuiccIntConnect(
unsigned long busNo, /* Pci Bus number of PMCQ1 */
unsigned long slotNo, /* Pci Slot number of PMCQ1 */
unsigned long funcNo, /* Pci Function number of PMCQ1 */
rtems_irq_hdl routine,/* interrupt routine */
rtems_irq_hdl_param arg /* argument to pass to interrupt routine */
FUNCION_PTR routine,/* interrupt routine */
int arg /* argument to pass to interrupt routine */
)
{
PPMCQ1BoardData boardData;
@@ -303,20 +323,19 @@ unsigned int rsPMCQ1Init(void)
{
int busNo;
int slotNo;
uint32_t baseaddr = 0;
uint32_t bridgeaddr = 0;
unsigned int baseaddr = 0;
unsigned int bridgeaddr = 0;
unsigned long pbti0_ctl;
int i;
unsigned char int_vector;
int fun;
uint32_t temp;
int temp;
PPMCQ1BoardData boardData;
rtems_irq_connect_data IrqData = {0,
rsPMCQ1Int,
NULL,
(rtems_irq_enable)rsPMCQ1_scc_nullFunc,
(rtems_irq_disable)rsPMCQ1_scc_nullFunc,
(rtems_irq_is_enabled)rsPMCQ1_scc_nullFunc,
rsPMCQ1_scc_nullFunc,
rsPMCQ1_scc_nullFunc,
rsPMCQ1_scc_nullFunc,
NULL};
if (rsPMCQ1Initialized)
@@ -436,7 +455,7 @@ unsigned int rsPMCQ1Init(void)
#ifdef DEBUG_360
printk("PMCQ1 int_vector %d\n", int_vector);
#endif
IrqData.name = (rtems_irq_number)((unsigned int)BSP_PCI_IRQ0 + int_vector);
IrqData.name = ((unsigned int)BSP_PCI_IRQ0 + int_vector);
IrqData.handle = boardData;
if (!BSP_install_rtems_shared_irq_handler (&IrqData)) {
printk("Error installing interrupt handler!\n");
@@ -474,7 +493,7 @@ unsigned int rsPMCQ1Init(void)
unsigned int rsPMCQ1Commission( unsigned long busNo, unsigned long slotNo )
{
unsigned int status = RTEMS_IO_ERROR;
uint32_t bridgeaddr = 0;
uint32_t bridgeaddr = 0;
unsigned long val;
int i;
uint32_t venId1;

35
c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h
View File

@@ -21,6 +21,9 @@
*
*/
#include <libcpu/io.h>
#include <bsp/irq.h>
/*
modification history
--------------------
@@ -30,9 +33,6 @@
#ifndef __INCPMCQ1H
#define __INCPMCQ1H
#include <libcpu/io.h>
#include <bsp/irq.h>
/*
* PMCQ1 definitions
*/
@@ -96,8 +96,8 @@
#define PMCQ1_RAM 0x00200000
/*
#define PMCQ1_Read_EPLD( _base, _reg ) ( *((unsigned long *) ((uint32_t)_base + _reg)) )
#define PMCQ1_Write_EPLD( _base, _reg, _data ) *((unsigned long *) ((uint32_t)_base + _reg)) = _data
#define PMCQ1_Read_EPLD( _base, _reg ) ( *((unsigned long *) ((unsigned32)_base + _reg)) )
#define PMCQ1_Write_EPLD( _base, _reg, _data ) *((unsigned long *) ((unsigned32)_base + _reg)) = _data
*/
uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg );
void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data );
@@ -108,6 +108,7 @@ void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data );
#define QSPAN2_INT_STATUS 0x00000600
typedef void (*FUNCION_PTR) (int);
#define PCI_ID(v, d) ((d << 16) | v)
@@ -130,10 +131,10 @@ typedef struct _PMCQ1BoardData
unsigned long funcNo;
unsigned long baseaddr;
unsigned long bridgeaddr;
rtems_irq_hdl quiccInt;
rtems_irq_hdl_param quiccArg;
rtems_irq_hdl maInt;
rtems_irq_hdl_param maArg;
FUNCION_PTR quiccInt;
int quiccArg;
FUNCION_PTR maInt;
int maArg;
} PMCQ1BoardData, *PPMCQ1BoardData;
extern PPMCQ1BoardData pmcq1BoardData;
@@ -142,7 +143,19 @@ extern PPMCQ1BoardData pmcq1BoardData;
* Function declarations
*/
extern unsigned int rsPMCQ1QuiccIntConnect(
unsigned long busNo, unsigned long slotNo,unsigned long funcNo, rtems_irq_hdl routine,rtems_irq_hdl_param arg );
extern unsigned int rsPMCQ1Init(void);
unsigned long busNo,
unsigned long slotNo,
unsigned long funcNo,
FUNCION_PTR routine,
int arg
);
unsigned int rsPMCQ1Init();
unsigned int rsPMCQ1MaIntConnect (
unsigned long busNo, /* Pci Bus number of PMCQ1 */
unsigned long slotNo, /* Pci Slot number of PMCQ1 */
unsigned long funcNo, /* Pci Function number of PMCQ1 */
FUNCION_PTR routine,/* interrupt routine */
int arg /* argument to pass to interrupt routine */
);
#endif /* __INCPMCQ1H */

2
c/src/lib/libbsp/powerpc/ep1a/include/bsp.h
View File

@@ -37,11 +37,11 @@
#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET
#define PCI_MEM_BASE 0x80000000
#define PCI_MEM_BASE_ADJUSTMENT 0
/* address of our ram on the PCI bus */
#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET
/* offset of pci memory as seen from the CPU */
#undef PCI_MEM_BASE
#define PCI_MEM_BASE 0x00000000
/* Override the default values for the following DEFAULT */

2
c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c
View File

@@ -35,6 +35,7 @@
/*
#define SHOW_ISA_PCI_BRIDGE_SETTINGS
*/
#define TRACE_IRQ_INIT
/*
* default on/off function
@@ -184,6 +185,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
initial_config.irqBase = BSP_LOWEST_OFFSET;
initial_config.irqPrioTbl = irqPrioTable;
printk("Call BSP_rtems_irq_mngt_set\n");
if (!BSP_rtems_irq_mngt_set(&initial_config)) {
/*
* put something here that will show the failure...

293
c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c Normal file
View File

@@ -0,0 +1,293 @@
/*
*
* This file contains the i8259/openpic-specific implementation of the function described in irq.h
*
* Copyright (C) 1998, 1999 valette@crf.canon.fr
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <stdlib.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq_supp.h>
#include <bsp/VMEConfig.h>
#include <bsp/openpic.h>
#include <libcpu/raw_exception.h>
#include <libcpu/io.h>
#include <bsp/vectors.h>
#include <stdlib.h>
#include <rtems/bspIo.h> /* for printk */
#define RAVEN_INTR_ACK_REG 0xfeff0030
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
/*
* pointer to the mask representing the additionnal irq vectors
* that must be disabled when a particular entry is activated.
* They will be dynamically computed from the priority table given
* in BSP_rtems_irq_mngt_set();
* CAUTION : this table is accessed directly by interrupt routine
* prologue.
*/
rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER];
#endif
/*
* default handler connected on each irq after bsp initialization
*/
static rtems_irq_connect_data default_rtems_entry;
static rtems_irq_connect_data* rtems_hdl_tbl;
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
/*
* Check if IRQ is an ISA IRQ
*/
static inline int is_isa_irq(const rtems_irq_number irqLine)
{
return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
);
}
#endif
/*
* Check if IRQ is an OPENPIC IRQ
*/
static inline int is_pci_irq(const rtems_irq_number irqLine)
{
return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
);
}
/*
* ------------------------ RTEMS Irq helper functions ----------------
*/
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
/*
* Caution : this function assumes the variable "*config"
* is already set and that the tables it contains are still valid
* and accessible.
*/
static void compute_i8259_masks_from_prio (rtems_irq_global_settings* config)
{
int i;
int j;
/*
* Always mask at least current interrupt to prevent re-entrance
*/
for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
* ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
/*
* Mask interrupts at i8259 level that have a lower priority
*/
if (config->irqPrioTbl [i] > config->irqPrioTbl [j]) {
* ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
}
}
}
}
#endif
void
BSP_enable_irq_at_pic(const rtems_irq_number name)
{
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
if (is_isa_irq(name)) {
/*
* Enable interrupt at PIC level
*/
printk("ERROR BSP_irq_enable_at_i8259s Being Called for %d\n", (int)name);
BSP_irq_enable_at_i8259s ((int) name);
}
#endif
if (is_pci_irq(name)) {
/*
* Enable interrupt at OPENPIC level
*/
printk(" openpic_enable_irq %d\n", (int)name );
openpic_enable_irq ((int) name);
}
}
int
BSP_disable_irq_at_pic(const rtems_irq_number name)
{
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
if (is_isa_irq(name)) {
/*
* disable interrupt at PIC level
*/
return BSP_irq_disable_at_i8259s ((int) name);
}
#endif
if (is_pci_irq(name)) {
/*
* disable interrupt at OPENPIC level
*/
return openpic_disable_irq ((int) name );
}
return -1;
}
/*
* RTEMS Global Interrupt Handler Management Routines
*/
int BSP_setup_the_pic(rtems_irq_global_settings* config)
{
int i;
/*
* Store various code accelerators
*/
default_rtems_entry = config->defaultEntry;
rtems_hdl_tbl = config->irqHdlTbl;
/*
* set up internal tables used by rtems interrupt prologue
*/
#if 0
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
/*
* start with ISA IRQ
*/
compute_i8259_masks_from_prio (config);
for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
BSP_irq_enable_at_i8259s (i);
}
else {
BSP_irq_disable_at_i8259s (i);
}
}
if ( BSP_ISA_IRQ_NUMBER > 0 ) {
/*
* must enable slave pic anyway
*/
BSP_irq_enable_at_i8259s (2);
}
#endif
#endif
/*
* continue with PCI IRQ
*/
for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
/*
* Note that openpic_set_priority() sets the TASK priority of the PIC
*/
openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET,
config->irqPrioTbl[i]);
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
openpic_enable_irq ((int) i );
}
else {
openpic_disable_irq ((int) i );
}
}
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
if ( BSP_ISA_IRQ_NUMBER > 0 ) {
/*
* Must enable PCI/ISA bridge IRQ
*/
openpic_enable_irq (0);
}
#endif
return 1;
}
int _BSP_vme_bridge_irq = -1;
unsigned BSP_spuriousIntr = 0;
/*
* High level IRQ handler called from shared_raw_irq_code_entry
*/
int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
{
register unsigned int irq;
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
register unsigned isaIntr; /* boolean */
register unsigned oldMask = 0; /* old isa pic masks */
register unsigned newMask; /* new isa pic masks */
#endif
if (excNum == ASM_DEC_VECTOR) {
/* printk("ASM_DEC_VECTOR\n"); */
bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);
return 0;
}
irq = openpic_irq(0);
if (irq == OPENPIC_VEC_SPURIOUS) {
/* printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS ); */
++BSP_spuriousIntr;
return 0;
}
/* some BSPs might want to use a different numbering... */
irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;
/* printk("OpenPic Irq: %d\n", irq); */
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
if (isaIntr) {
/* printk("BSP_PCI_ISA_BRIDGE_IRQ\n"); */
/*
* Acknowledge and read 8259 vector
*/
irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
/*
* store current PIC mask
*/
oldMask = i8259s_cache;
newMask = oldMask | irq_mask_or_tbl [irq];
i8259s_cache = newMask;
outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
BSP_irq_ack_at_i8259s (irq);
openpic_eoi(0);
}
#endif
/* dispatch handlers */
/* printk("dispatch\n"); */
irq -=16;
bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
/* printk("Back from dispatch\n"); */
#ifdef BSP_PCI_ISA_BRIDGE_IRQ
if (isaIntr) {\
i8259s_cache = oldMask;
outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
}
else
#endif
{
#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
/* leave it to the VME bridge driver to do EOI, so
* it can re-enable the openpic while handling
* VME interrupts (-> VME priorities in software)
*/
if (_BSP_vme_bridge_irq != irq)
#endif
openpic_eoi(0);
}
return 0;
}

16
c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h
View File

@@ -63,9 +63,9 @@
*/
#undef BSP_VME_BAT_IDX
#define _VME_A32_WIN0_ON_PCI 0x10000000
#define _VME_A24_ON_PCI 0x1f000000
#define _VME_A16_ON_PCI 0x1fff0000
#define _VME_A32_WIN0_ON_PCI 0x90000000
#define _VME_A24_ON_PCI 0x9f000000
#define _VME_A16_ON_PCI 0x9fff0000
/* start of the A32 window on the VME bus
* TODO: this should perhaps be a configuration option
@@ -77,6 +77,16 @@
* at _VME_DRAM_OFFSET
*/
#undef _VME_DRAM_OFFSET
#define _VME_DRAM_OFFSET 0xc0000000
#define _VME_DRAM_32_OFFSET1 0x20000000
#define _VME_DRAM_32_OFFSET2 0x20b00000
#define _VME_DRAM_24_OFFSET1 0x00000000
#define _VME_DRAM_24_OFFSET2 0x00100000
#define _VME_DRAM_16_OFFSET1 0x00000000
#define _VME_DRAM_16_OFFSET2 0x00008000
#define _VME_A24_SIZE 0x00100000
#define _VME_A16_SIZE 0x00008000
#undef _VME_CSR_ON_PCI