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2001-05-22 Greg Menke <gregory.menke@gsfc.nasa.gov>

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* rtems/score/cpu.h: Add the interrupt stack structure and enhance
	the context initialization to account for floating point tasks.
	* rtems/score/mips.h: Added the routines mips_set_cause(),
	mips_get_fcr31(), and mips_set_fcr31().
	* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
This commit is contained in:
Joel Sherrill
2001-05-22 22:59:42 +00:00
parent baf22b93bd
commit e2040badd2
6 changed files with 172 additions and 42 deletions
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8
c/src/exec/score/cpu/mips/ChangeLog
View File

@@ -1,3 +1,11 @@
2001-05-22 Greg Menke <gregory.menke@gsfc.nasa.gov>
* rtems/score/cpu.h: Add the interrupt stack structure and enhance
the context initialization to account for floating point tasks.
* rtems/score/mips.h: Added the routines mips_set_cause(),
mips_get_fcr31(), and mips_set_fcr31().
* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
2001-05-07 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S: Merged patches from Gregory Menke

33
c/src/exec/score/cpu/mips/rtems/score/cpu.h
View File

@@ -148,9 +148,12 @@ extern "C" {
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER 1
/*
* Does the CPU have hardware floating point?
@@ -380,7 +383,7 @@ typedef struct {
__MIPS_REGISTER_TYPE fp;
__MIPS_REGISTER_TYPE ra;
__MIPS_REGISTER_TYPE c0_sr;
__MIPS_REGISTER_TYPE c0_epc;
/* __MIPS_REGISTER_TYPE c0_epc; */
} Context_Control;
/* WARNING: If this structure is modified, the constants in cpu.h
@@ -424,8 +427,25 @@ typedef struct {
#endif
} Context_Control_fp;
typedef struct {
unsigned32 special_interrupt_register;
/*
This struct reflects the stack frame employed in ISR_Handler. Note
that the ISR routine doesn't save all registers to this frame, so
cpu_asm.S should be consulted to see if the registers you're
interested in are actually there.
*/
typedef struct
{
#if __mips == 1
unsigned int regs[80];
#endif
#if __mips == 3
unsigned int regs[94];
#endif
} CPU_Interrupt_frame;
@@ -685,8 +705,9 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
(_the_context)->sp = _stack_tmp; \
(_the_context)->fp = _stack_tmp; \
(_the_context)->ra = (unsigned64)_entry_point; \
if (_isr) (_the_context)->c0_sr = 0xff00; \
else (_the_context)->c0_sr = 0xff01; \
(_the_context)->c0_sr = ((_the_context)->c0_sr & 0x0fff0000) | \
((_isr)?0xff00:0xff01) | \
((_is_fp)?0x20000000:0x10000000); \
}
/*

36
c/src/exec/score/cpu/mips/rtems/score/mips.h
View File

@@ -90,6 +90,42 @@ extern "C" {
asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
} while (0)
#define mips_get_cause( _x ) \
do { \
asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
} while (0)
#define mips_set_cause( _x ) \
do { \
register unsigned int __x = (_x); \
asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
} while (0)
#define mips_get_fcr31( _x ) \
do { \
asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
} while(0)
#define mips_set_fcr31( _x ) \
do { \
register unsigned int __x = (_x); \
asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
} while(0)
/*
* Manipulate interrupt mask
*

8
cpukit/score/cpu/mips/ChangeLog
View File

@@ -1,3 +1,11 @@
2001-05-22 Greg Menke <gregory.menke@gsfc.nasa.gov>
* rtems/score/cpu.h: Add the interrupt stack structure and enhance
the context initialization to account for floating point tasks.
* rtems/score/mips.h: Added the routines mips_set_cause(),
mips_get_fcr31(), and mips_set_fcr31().
* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
2001-05-07 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S: Merged patches from Gregory Menke

33
cpukit/score/cpu/mips/rtems/score/cpu.h
View File

@@ -148,9 +148,12 @@ extern "C" {
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER 1
/*
* Does the CPU have hardware floating point?
@@ -380,7 +383,7 @@ typedef struct {
__MIPS_REGISTER_TYPE fp;
__MIPS_REGISTER_TYPE ra;
__MIPS_REGISTER_TYPE c0_sr;
__MIPS_REGISTER_TYPE c0_epc;
/* __MIPS_REGISTER_TYPE c0_epc; */
} Context_Control;
/* WARNING: If this structure is modified, the constants in cpu.h
@@ -424,8 +427,25 @@ typedef struct {
#endif
} Context_Control_fp;
typedef struct {
unsigned32 special_interrupt_register;
/*
This struct reflects the stack frame employed in ISR_Handler. Note
that the ISR routine doesn't save all registers to this frame, so
cpu_asm.S should be consulted to see if the registers you're
interested in are actually there.
*/
typedef struct
{
#if __mips == 1
unsigned int regs[80];
#endif
#if __mips == 3
unsigned int regs[94];
#endif
} CPU_Interrupt_frame;
@@ -685,8 +705,9 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
(_the_context)->sp = _stack_tmp; \
(_the_context)->fp = _stack_tmp; \
(_the_context)->ra = (unsigned64)_entry_point; \
if (_isr) (_the_context)->c0_sr = 0xff00; \
else (_the_context)->c0_sr = 0xff01; \
(_the_context)->c0_sr = ((_the_context)->c0_sr & 0x0fff0000) | \
((_isr)?0xff00:0xff01) | \
((_is_fp)?0x20000000:0x10000000); \
}
/*

36
cpukit/score/cpu/mips/rtems/score/mips.h
View File

@@ -90,6 +90,42 @@ extern "C" {
asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
} while (0)
#define mips_get_cause( _x ) \
do { \
asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
} while (0)
#define mips_set_cause( _x ) \
do { \
register unsigned int __x = (_x); \
asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
} while (0)
#define mips_get_fcr31( _x ) \
do { \
asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
} while(0)
#define mips_set_fcr31( _x ) \
do { \
register unsigned int __x = (_x); \
asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
} while(0)
/*
* Manipulate interrupt mask
*