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Patches for Qemu 1.0.50

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This commit is contained in:
Sebastian Huber
2012-02-11 21:15:06 +01:00
parent 14ee5a1e22
commit e1ebfebf1b
9 changed files with 122 additions and 152 deletions
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28
c/src/lib/libbsp/arm/lm3s69xx/0001-Fixed-interrupt-handling-for-ARMv7M.patch
View File

@@ -1,28 +0,0 @@
From 917f2491c1dc2525b24c635afe4459e55700149c Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Sun, 5 Jun 2011 14:57:17 +0200
Subject: [PATCH 1/6] Fixed interrupt handling for ARMv7M.
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
cpu-exec.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 6ddd8dd..d1e9816 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -470,8 +470,8 @@ int cpu_exec(CPUState *env1)
We avoid this by disabling interrupts when
pc contains a magic address. */
if (interrupt_request & CPU_INTERRUPT_HARD
- && ((IS_M(env) && env->regs[15] < 0xfffffff0)
- || !(env->uncached_cpsr & CPSR_I))) {
+ && !(env->uncached_cpsr & CPSR_I)
+ && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
env->exception_index = EXCP_IRQ;
do_interrupt(env);
next_tb = 0;
--
1.7.1

26
c/src/lib/libbsp/arm/lm3s69xx/0002-Fixed-system-handler-priority-register-access.patch → c/src/lib/libbsp/arm/lm3s69xx/0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch
View File

@@ -1,22 +1,24 @@
From 403b4e0718a815b425a964cfbf7f4117a9278d88 Mon Sep 17 00:00:00 2001
From 0c8e700376cec0c7b5a70f999b5e286efc321423 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Sun, 19 Jun 2011 15:33:17 +0200
Subject: [PATCH 2/6] Fixed system handler priority register access.
Date: Fri, 16 Dec 2011 19:46:40 +0100
Subject: [PATCH 1/4] target-arm: Fixed ARMv7-M SHPR access
According to "ARMv7-M Architecture Reference Manual" issue D section
"B3.2.10 System Handler Prioriy Register 1, SHPR1", "B3.2.11 System
Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy
Register 3, SHPR3".
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
hw/arm_gic.c | 16 ++++++++++++++--
hw/armv7m_nvic.c | 19 -------------------
2 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 0e934ec..9f75fcc 100644
index 9b52119..5139d95 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -341,6 +341,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
@@ -356,6 +356,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
if (GIC_TEST_TRIGGER(irq + i))
res |= (2 << (i * 2));
}
@@ -28,17 +30,17 @@ index 0e934ec..9f75fcc 100644
#endif
} else if (offset < 0xfe0) {
goto bad_reg;
@@ -372,7 +377,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
@@ -387,7 +392,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
gic_state *s = (gic_state *)opaque;
uint32_t addr;
addr = offset;
- if (addr < 0x100 || addr > 0xd00)
+ if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
+ && addr != 0xd20)) {
+ && addr != 0xd20))
return nvic_readl(s, addr);
#endif
val = gic_dist_readw(opaque, offset);
@@ -507,6 +513,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
@@ -528,6 +534,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
GIC_CLEAR_TRIGGER(irq + i);
}
}
@@ -50,7 +52,7 @@ index 0e934ec..9f75fcc 100644
#endif
} else {
/* 0xf00 is only handled for 32-bit writes. */
@@ -532,7 +543,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
@@ -553,7 +564,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
#ifdef NVIC
uint32_t addr;
addr = offset;
@@ -61,10 +63,10 @@ index 0e934ec..9f75fcc 100644
return;
}
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index d06eec9..a2d1404 100644
index bf8c3c5..65b575e 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -194,14 +194,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
@@ -195,14 +195,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
case 0xd14: /* Configuration Control. */
/* TODO: Implement Configuration Control bits. */
return 0;
@@ -79,7 +81,7 @@ index d06eec9..a2d1404 100644
case 0xd24: /* System Handler Status. */
val = 0;
if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
@@ -334,17 +326,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
@@ -335,17 +327,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
case 0xd14: /* Configuration Control. */
/* TODO: Implement control registers. */
goto bad_reg;

13
c/src/lib/libbsp/arm/lm3s69xx/0003-Disable-priority_mask-unused-for-NVIC.patch → c/src/lib/libbsp/arm/lm3s69xx/0002-target-arm-Disable-priority_mask-feature.patch
View File

@@ -1,17 +1,20 @@
From 00cf49e35ff83ca3d90caf98339591452b1100e5 Mon Sep 17 00:00:00 2001
From 5f562d098d84e12d4688272dcf68a2d0318721a7 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Sun, 17 Jul 2011 15:13:42 +0200
Subject: [PATCH 3/6] Disable priority_mask (unused for NVIC).
Date: Fri, 16 Dec 2011 20:00:59 +0100
Subject: [PATCH 2/4] target-arm: Disable priority_mask feature
This is unused for the ARMv7-M NVIC.
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
hw/arm_gic.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 9f75fcc..a97a318 100644
index 5139d95..cafcc81 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -642,7 +642,11 @@ static void gic_reset(gic_state *s)
@@ -707,7 +707,11 @@ static void gic_reset(gic_state *s)
int i;
memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
for (i = 0 ; i < NUM_CPU(s); i++) {

63
c/src/lib/libbsp/arm/lm3s69xx/0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch Normal file
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@@ -0,0 +1,63 @@
From 78e85bb79c02b14170c3f39d9bb9cccd4d625890 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 16 Dec 2011 20:12:29 +0100
Subject: [PATCH 3/4] target-arm: Evil hack for BASEPRI and BASEPRI_MAX
This is only a quick and dirty fix to get the ARMv7-M BASEPRI and
BASEPRI_MAX feature working.
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
cpu-exec.c | 4 ++--
target-arm/helper.c | 12 +++++-------
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index a9fa608..6ca9aab 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -408,8 +408,8 @@ int cpu_exec(CPUState *env)
We avoid this by disabling interrupts when
pc contains a magic address. */
if (interrupt_request & CPU_INTERRUPT_HARD
- && ((IS_M(env) && env->regs[15] < 0xfffffff0)
- || !(env->uncached_cpsr & CPSR_I))) {
+ && !(env->uncached_cpsr & CPSR_I)
+ && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
env->exception_index = EXCP_IRQ;
do_interrupt(env);
next_tb = 0;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 65f4fbf..be2e6db 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2163,7 +2163,7 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
return (env->uncached_cpsr & CPSR_I) != 0;
case 17: /* BASEPRI */
case 18: /* BASEPRI_MAX */
- return env->v7m.basepri;
+ return (env->uncached_cpsr & CPSR_I) != 0;
case 19: /* FAULTMASK */
return (env->uncached_cpsr & CPSR_F) != 0;
case 20: /* CONTROL */
@@ -2218,13 +2218,11 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
env->uncached_cpsr &= ~CPSR_I;
break;
case 17: /* BASEPRI */
- env->v7m.basepri = val & 0xff;
- break;
case 18: /* BASEPRI_MAX */
- val &= 0xff;
- if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
- env->v7m.basepri = val;
- break;
+ if (val)
+ env->uncached_cpsr |= CPSR_I;
+ else
+ env->uncached_cpsr &= ~CPSR_I;
case 19: /* FAULTMASK */
if (val & 1)
env->uncached_cpsr |= CPSR_F;
--
1.7.1

25
c/src/lib/libbsp/arm/lm3s69xx/0004-Typo.patch
View File

@@ -1,25 +0,0 @@
From 9c977927e545943996981c86c7ec71f0b44921ba Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Sun, 17 Jul 2011 15:14:40 +0200
Subject: [PATCH 4/6] Typo.
---
hw/arm_gic.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index a97a318..237f13f 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -378,7 +378,7 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
uint32_t addr;
addr = offset;
if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
- && addr != 0xd20)) {
+ && addr != 0xd20))
return nvic_readl(s, addr);
#endif
val = gic_dist_readw(opaque, offset);
--
1.7.1

32
c/src/lib/libbsp/arm/lm3s69xx/0004-target-arm-Evil-hack-to-increase-the-RAM-size.patch Normal file
View File

@@ -0,0 +1,32 @@
From e06edd436a336e5db5188eb7ffac594138fc825a Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 16 Dec 2011 20:19:45 +0100
Subject: [PATCH 4/4] target-arm: Evil hack to increase the RAM size
This increases the RAM of the Stellaris LM3S6965 in a brute force way.
It would be nice to be able to override the default RAM size with
command line options. The default RAM size is to small to run complex
test suites.
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
hw/stellaris.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/hw/stellaris.c b/hw/stellaris.c
index ce62a98..dd7b7d7 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -1219,7 +1219,8 @@ static stellaris_board_info stellaris_boards[] = {
{ "LM3S6965EVB",
0x10010002,
0x1073402e,
- 0x00ff007f, /* dc0 */
+ /* FIXME */
+ 0xffffffff, /* dc0 */
0x001133ff,
0x030f5317,
0x0f0f87ff,
--
1.7.1

49
c/src/lib/libbsp/arm/lm3s69xx/0005-Evil-hack-for-BASEPRI-BASEPRI_MAX.patch
View File

@@ -1,49 +0,0 @@
From ee20f52f56b076e71f617e4e3cfe413bea73b824 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 16 Sep 2011 21:28:21 +0200
Subject: [PATCH 5/6] Evil hack for BASEPRI/BASEPRI_MAX.
---
target-arm/helper.c | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2fd45c4..d5fc9d3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1997,7 +1997,11 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
return (env->uncached_cpsr & CPSR_I) != 0;
case 17: /* BASEPRI */
case 18: /* BASEPRI_MAX */
+ /* FIXME */
+ return (env->uncached_cpsr & CPSR_I) != 0;
+#if 0
return env->v7m.basepri;
+#endif
case 19: /* FAULTMASK */
return (env->uncached_cpsr & CPSR_F) != 0;
case 20: /* CONTROL */
@@ -2052,6 +2056,12 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
env->uncached_cpsr &= ~CPSR_I;
break;
case 17: /* BASEPRI */
+ case 18: /* BASEPRI_MAX */
+ if (val)
+ env->uncached_cpsr |= CPSR_I;
+ else
+ env->uncached_cpsr &= ~CPSR_I;
+#if 0
env->v7m.basepri = val & 0xff;
break;
case 18: /* BASEPRI_MAX */
@@ -2059,6 +2069,7 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
env->v7m.basepri = val;
break;
+#endif
case 19: /* FAULTMASK */
if (val & 1)
env->uncached_cpsr |= CPSR_F;
--
1.7.1

26
c/src/lib/libbsp/arm/lm3s69xx/0006-Evil-hack-to-increase-the-RAM-size.patch
View File

@@ -1,26 +0,0 @@
From 187cd2844ffb0e197231dbf7a844e531c1146e09 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Sat, 24 Sep 2011 15:21:41 +0200
Subject: [PATCH 6/6] Evil hack to increase the RAM size.
---
hw/stellaris.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/hw/stellaris.c b/hw/stellaris.c
index ac9fcc1..c00b2fa 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -1177,7 +1177,8 @@ static stellaris_board_info stellaris_boards[] = {
{ "LM3S6965EVB",
0x10010002,
0x1073402e,
- 0x00ff007f, /* dc0 */
+ /* FIXME */
+ 0xffffffff, /* dc0 */
0x001133ff,
0x030f5317,
0x0f0f87ff,
--
1.7.1

12
c/src/lib/libbsp/arm/lm3s69xx/README
View File

@@ -1,14 +1,12 @@
Tested only on Qemu simulator with git (git://git.qemu.org/qemu.git) version
f9188227a455446b5c10a8f5114f266001c1c801 (Tue May 17 17:08:43 2011).
1.0.50.
You have to apply the patches:
0001-Fixed-interrupt-handling-for-ARMv7M.patch
0002-Fixed-system-handler-priority-register-access.patch
0003-Disable-priority_mask-unused-for-NVIC.patch
0004-Typo.patch
0005-Evil-hack-for-BASEPRI-BASEPRI_MAX.patch
0006-Evil-hack-to-increase-the-RAM-size.patch
0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch
0002-target-arm-Disable-priority_mask-feature.patch
0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch
0004-target-arm-Evil-hack-to-increase-the-RAM-size.patch
Command line: