forked from Imagelibrary/rtems
rtems: Add cache size functions
Add rtems_cache_get_data_cache_size() and rtems_cache_get_instruction_cache_size().
This commit is contained in:
@@ -160,6 +160,16 @@ rtems_cache_get_data_line_size( void )
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}
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size_t
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rtems_cache_get_data_cache_size( uint32_t level )
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{
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#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS)
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return _CPU_cache_get_data_cache_size( level );
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#else
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return 0;
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#endif
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}
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/*
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/*
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* This function freezes the data cache; cache lines
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* This function freezes the data cache; cache lines
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* are not replaced.
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* are not replaced.
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@@ -275,6 +285,17 @@ rtems_cache_get_instruction_line_size( void )
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}
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}
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size_t
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rtems_cache_get_instruction_cache_size( uint32_t level )
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{
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#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS)
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return _CPU_cache_get_instruction_cache_size( level );
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#else
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return 0;
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#endif
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}
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/*
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/*
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* This function freezes the instruction cache; cache lines
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* This function freezes the instruction cache; cache lines
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* are not replaced.
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* are not replaced.
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@@ -60,6 +60,26 @@ size_t rtems_cache_get_data_line_size( void );
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*/
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*/
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size_t rtems_cache_get_instruction_line_size( void );
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size_t rtems_cache_get_instruction_line_size( void );
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/**
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* @brief Returns the data cache size in bytes.
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*
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* @param[in] level The cache level of interest. The cache level zero
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* specifies the entire data cache.
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*
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* @returns The data cache size in bytes of the specified level.
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*/
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size_t rtems_cache_get_data_cache_size( uint32_t level );
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/**
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* @brief Returns the instruction cache size in bytes.
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*
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* @param[in] level The cache level of interest. The cache level zero
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* specifies the entire instruction cache.
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*
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* @returns The instruction cache size in bytes of the specified level.
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*/
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size_t rtems_cache_get_instruction_cache_size( uint32_t level );
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/**
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/**
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* @brief Flushes multiple data cache lines.
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* @brief Flushes multiple data cache lines.
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*
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*
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@@ -163,12 +163,28 @@ static void test_timing(void)
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rtems_interrupt_lock lock = RTEMS_INTERRUPT_LOCK_INITIALIZER;
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rtems_interrupt_lock lock = RTEMS_INTERRUPT_LOCK_INITIALIZER;
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size_t data_size = sizeof(data);
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size_t data_size = sizeof(data);
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uint64_t d[3];
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uint64_t d[3];
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uint32_t cache_level;
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size_t cache_size;
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printf(
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printf(
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"data cache line size %zi bytes\n",
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"data cache line size %zi bytes\n"
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rtems_cache_get_data_line_size()
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"data cache size %zi bytes\n",
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rtems_cache_get_data_line_size(),
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rtems_cache_get_data_cache_size(0)
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);
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);
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cache_level = 1;
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cache_size = rtems_cache_get_data_cache_size(cache_level);
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while (cache_size > 0) {
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printf(
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"data cache level %" PRIu32 " size %zi bytes\n",
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cache_level,
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cache_size
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);
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++cache_level;
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cache_size = rtems_cache_get_data_cache_size(cache_level);
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}
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rtems_interrupt_lock_acquire(&lock, level);
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rtems_interrupt_lock_acquire(&lock, level);
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d[0] = load();
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d[0] = load();
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@@ -290,10 +306,24 @@ static void test_timing(void)
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);
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);
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printf(
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printf(
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"instruction cache line size %zi bytes\n",
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"instruction cache line size %zi bytes\n"
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rtems_cache_get_instruction_line_size()
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"instruction cache size %zi bytes\n",
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rtems_cache_get_instruction_line_size(),
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rtems_cache_get_instruction_cache_size(0)
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);
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);
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cache_level = 1;
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cache_size = rtems_cache_get_instruction_cache_size(cache_level);
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while (cache_size > 0) {
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printf(
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"instruction cache level %" PRIu32 " size %zi bytes\n",
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cache_level,
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cache_size
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);
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++cache_level;
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cache_size = rtems_cache_get_instruction_cache_size(cache_level);
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}
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rtems_interrupt_lock_acquire(&lock, level);
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rtems_interrupt_lock_acquire(&lock, level);
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d[0] = do_some_work();
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d[0] = do_some_work();
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@@ -3,6 +3,9 @@ data cache flush and invalidate test
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data cache operations by line passed the test
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data cache operations by line passed the test
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data cache operations by line passed the test (copy-back cache detected)
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data cache operations by line passed the test (copy-back cache detected)
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data cache line size 32 bytes
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data cache line size 32 bytes
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data cache size 262144 bytes
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data cache level 1 size 32768 bytes
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data cache level 2 size 262144 bytes
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load 4096 bytes with flush entire data
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load 4096 bytes with flush entire data
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duration with normal cache 12660 ns
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duration with normal cache 12660 ns
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duration with warm cache 2580 ns
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duration with warm cache 2580 ns
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@@ -28,6 +31,9 @@ store 4096 bytes with invalidate multiple data
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duration with warm cache 2580 ns
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duration with warm cache 2580 ns
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duration with invalidated cache 2640 ns
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duration with invalidated cache 2640 ns
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instruction cache line size 32 bytes
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instruction cache line size 32 bytes
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instruction cache size 262144 bytes
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instruction cache level 1 size 32768 bytes
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instruction cache level 2 size 262144 bytes
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invalidate entire instruction
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invalidate entire instruction
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duration with normal cache 5780 ns
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duration with normal cache 5780 ns
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duration with warm cache 640 ns
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duration with warm cache 640 ns
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