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termios: Update due to API changes

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Termios notifies now the driver about an inactive transmit with the
length argument set to zero.
This commit is contained in:
Sebastian Huber
2013-06-24 17:29:11 +02:00
parent 1df348b960
commit e18db9f0cf
28 changed files with 254 additions and 270 deletions
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17
c/src/lib/libcpu/bfin/serial/uart.c
View File

@@ -323,12 +323,14 @@ static int setAttributes(int minor, const struct termios *termios) {
static ssize_t uart_interruptWrite(int minor, const char *buf, size_t len) {
uint32_t base = 0;
bfin_uart_channel_t* channel = NULL;
rtems_interrupt_level isrLevel;
/**
* Sanity Check
*/
if (NULL == buf || NULL == channel || NULL == uartsConfig || minor < 0) {
if (
NULL == buf || NULL == channel || NULL == uartsConfig
|| minor < 0 || 0 == len
) {
return 0;
}
@@ -338,8 +340,6 @@ static ssize_t uart_interruptWrite(int minor, const char *buf, size_t len) {
return 0;
}
rtems_interrupt_disable(isrLevel);
base = channel->uart_baseAddress;
channel->flags |= BFIN_UART_XMIT_BUSY;
@@ -347,8 +347,6 @@ static ssize_t uart_interruptWrite(int minor, const char *buf, size_t len) {
*(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf;
*(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI;
rtems_interrupt_enable(isrLevel);
return 0;
}
@@ -412,12 +410,11 @@ static ssize_t uart_DmaWrite(int minor, const char *buf, size_t len) {
uint32_t base = 0;
bfin_uart_channel_t* channel = NULL;
uint32_t tx_dma_base = 0;
rtems_interrupt_level isrLevel;
/**
* Sanity Check
*/
if ( NULL == buf || 0 > minor || NULL == uartsConfig ) {
if ( NULL == buf || 0 > minor || NULL == uartsConfig || 0 == len ) {
return 0;
}
@@ -430,8 +427,6 @@ static ssize_t uart_DmaWrite(int minor, const char *buf, size_t len) {
return 0;
}
rtems_interrupt_disable(isrLevel);
base = channel->uart_baseAddress;
tx_dma_base = channel->uart_txDmaBaseAddress;
@@ -445,8 +440,6 @@ static ssize_t uart_DmaWrite(int minor, const char *buf, size_t len) {
*(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) |= DMA_CONFIG_DMAEN;
*(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI;
rtems_interrupt_enable(isrLevel);
return 0;
}

23
c/src/lib/libcpu/m68k/mcf5206/console/mcfuart.c
View File

@@ -519,19 +519,20 @@ mcfuart_interrupt_handler(rtems_vector_number vec)
ssize_t
mcfuart_interrupt_write(mcfuart *uart, const char *buf, size_t len)
{
int level;
rtems_interrupt_disable(level);
uart->tx_buf = buf;
uart->tx_buf_len = len;
uart->tx_ptr = 0;
*MCF5206E_UIMR(MBAR, uart->chn) =
MCF5206E_UIMR_FFULL | MCF5206E_UIMR_TXRDY;
while (((*MCF5206E_USR(MBAR,uart->chn) & MCF5206E_USR_TXRDY) != 0) &&
(uart->tx_ptr < uart->tx_buf_len))
if (len > 0)
{
*MCF5206E_UTB(MBAR,uart->chn) = uart->tx_buf[uart->tx_ptr++];
uart->tx_buf = buf;
uart->tx_buf_len = len;
uart->tx_ptr = 0;
*MCF5206E_UIMR(MBAR, uart->chn) =
MCF5206E_UIMR_FFULL | MCF5206E_UIMR_TXRDY;
while (((*MCF5206E_USR(MBAR,uart->chn) & MCF5206E_USR_TXRDY) != 0) &&
(uart->tx_ptr < uart->tx_buf_len))
{
*MCF5206E_UTB(MBAR,uart->chn) = uart->tx_buf[uart->tx_ptr++];
}
}
rtems_interrupt_enable(level);
return 0;
}

4
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
View File

@@ -686,7 +686,6 @@ MG5UART_STATIC int mg5uart_write_support_int(
size_t len
)
{
uint32_t Irql;
uint32_t pMG5UART_port;
pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
@@ -703,8 +702,6 @@ MG5UART_STATIC int mg5uart_write_support_int(
* Put the character out and enable interrupts if necessary.
*/
rtems_interrupt_disable(Irql);
MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf);
if( Console_Port_Data[minor].bActive == FALSE )
@@ -713,7 +710,6 @@ MG5UART_STATIC int mg5uart_write_support_int(
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL);
}
rtems_interrupt_enable(Irql);
return 1;
}

11
c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c
View File

@@ -292,13 +292,12 @@ static int mpc55xx_esci_termios_poll_write( int minor, const char *out,
*/
static int mpc55xx_esci_termios_write( int minor, const char *out, size_t n)
{
mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [minor];
rtems_interrupt_level level;
if (n > 0) {
mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [minor];
rtems_interrupt_disable(level);
e->regs->DR.B.D = out [0];
e->transmit_in_progress = true;
rtems_interrupt_enable(level);
e->regs->DR.B.D = out [0];
e->transmit_in_progress = true;
}
return 0;
}

9
c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c
View File

@@ -144,10 +144,13 @@ ssize_t m5xx_uart_write(
size_t len
)
{
volatile m5xxSCIRegisters_t *regs = sci_descs[minor].regs;
if (len > 0) {
volatile m5xxSCIRegisters_t *regs = sci_descs[minor].regs;
regs->scdr = *buf; /* start transmission */
regs->sccr1 |= QSMCM_SCI_TIE; /* enable interrupt */
}
regs->scdr = *buf; /* start transmission */
regs->sccr1 |= QSMCM_SCI_TIE; /* enable interrupt */
return 0;
}

13
c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c
View File

@@ -1090,12 +1090,15 @@ m8xx_uart_write(
size_t len
)
{
while( (TxBd[minor]->status) & M8260_BD_READY );
if (len > 0) {
while( (TxBd[minor]->status) & M8260_BD_READY );
rtems_cache_flush_multiple_data_lines( buf, len );
TxBd[minor]->buffer = (char *) buf;
TxBd[minor]->length = len;
TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP | M8260_BD_INTERRUPT;
}
rtems_cache_flush_multiple_data_lines( buf, len );
TxBd[minor]->buffer = (char *) buf;
TxBd[minor]->length = len;
TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP | M8260_BD_INTERRUPT;
return 0;
}

7
c/src/lib/libcpu/powerpc/ppc403/console/console.c
View File

@@ -271,8 +271,11 @@ spiPollRead (int minor)
static int
spiInterruptWrite (int minor, const char *buf, int len)
{
port->SPTB = *buf; /* write char to send */
port->SPTC |= TCRIntEnabled; /* always enable tx interrupt */
if (len > 0) {
port->SPTB = *buf; /* write char to send */
port->SPTC |= TCRIntEnabled; /* always enable tx interrupt */
}
return 0;
}

7
c/src/lib/libcpu/powerpc/ppc403/console/console405.c
View File

@@ -296,8 +296,11 @@ spiStopRemoteTx (int minor)
static ssize_t InterruptWrite (int minor, const char *buf, size_t len)
{
port->IER |= IER_XMT; /* always enable tx interrupt */
port->THR = *buf; /* write char to send */
if (len > 0) {
port->IER |= IER_XMT; /* always enable tx interrupt */
port->THR = *buf; /* write char to send */
}
return 0;
}

27
c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
View File

@@ -761,24 +761,21 @@ sh4uart2_interrupt_transmit(rtems_vector_number vec)
rtems_status_code
sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len)
{
volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1;
volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2;
int level;
if (len > 0) {
volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1;
volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2;
while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0);
while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0);
rtems_interrupt_disable(level);
uart->tx_buf = buf;
uart->tx_buf_len = len;
uart->tx_ptr = 0;
uart->tx_buf = buf;
uart->tx_buf_len = len;
uart->tx_ptr = 0;
if (uart->chn == SH4_SCI)
*scr1 |= SH7750_SCSCR_TIE;
else
*scr2 |= SH7750_SCSCR_TIE;
rtems_interrupt_enable(level);
if (uart->chn == SH4_SCI)
*scr1 |= SH7750_SCSCR_TIE;
else
*scr2 |= SH7750_SCSCR_TIE;
}
return RTEMS_SUCCESSFUL;
}