forked from Imagelibrary/rtems
libdebugger/arm: Support ROM tables.
- Parse the ROM taables if present to find the component base for the debug hardware. This lets the RPi2 run dl09.exe.
This commit is contained in:
Chris Johns
@@ -26,6 +26,8 @@
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#define TARGET_DEBUG 0
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#define ARM_DUMP_ROM_TABLES 0
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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@@ -548,10 +550,278 @@ arm_debug_cp14_enable(rtems_debugger_target* target)
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static jmp_buf unlock_abort_jmpbuf;
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static size_t arm_debug_retries;
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static void
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arm_debug_dump_rom_table(uint32_t* rom, size_t depth)
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{
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uint32_t pidr[7];
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uint32_t cidr[4];
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uint32_t memtype;
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uint32_t pidr4_4KB_count;
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size_t r;
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static const char *table_class[16] = {
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"reserved",
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"ROM table",
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"reserved", "reserved",
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"reserved",
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"reserved",
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"reserved",
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"reserved",
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"reserved",
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"CoreSight component",
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"reserved",
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"Peripheral Test Block",
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"reserved",
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"OptimoDE DESS",
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"Generic IP component",
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"PrimeCell or System component"
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};
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#define ROM_READ(b_, o_, r_) b_[((o_) / sizeof(uint32_t)) + (r_)]
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if (depth > 16) {
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rtems_debugger_printf("]] rom: too deep\n");
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return;
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}
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for (r = 0; r < 4; ++r)
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pidr[r] = ROM_READ(rom, 0xfe0, r) & 0xff;
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for (r = 0; r < 3; ++r)
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pidr[r + 4] = ROM_READ(rom, 0xfd0, r) & 0xff;
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for (r = 0; r < 4; ++r)
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cidr[r] = ROM_READ(rom, 0xff0, r) & 0xff;
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memtype = ROM_READ(rom, 0xfcc, 0);
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pidr4_4KB_count = pidr[4] & (((1 << (7 - 4)) - 1) >> 4);
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rtems_debugger_printf("]] rom = %p\n", rom);
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rtems_debugger_printf(" PIDR: %08x %08x %08x %08x %08x %08x %08x\n",
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pidr[0], pidr[1], pidr[2], pidr[3],
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pidr[4], pidr[5], pidr[6]);
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rtems_debugger_printf(" CIDR: %08x %08x %08x %08x\n",
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cidr[0], cidr[1], cidr[2], cidr[3]);
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rtems_debugger_printf(" 4KB count: %u\n", pidr4_4KB_count);
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if ((memtype & 0x01) != 0)
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rtems_debugger_printf(" MEMTYPE sys memory present on bus\n");
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else
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rtems_debugger_printf(" MEMTYPE sys memory not present: dedicated debug bus\n");
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/*
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* Read ROM table entries until we get 0
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*/
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for (r = 0; rom[r] != 0; ++r) {
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uint32_t romentry = rom[r];
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uint32_t c_pidr[7];
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uint32_t c_cidr[4];
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uint32_t* c_base;
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uint32_t table_type;
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size_t i;
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c_base = (uint32_t*) ((intptr_t) rom + (romentry & 0xFFFFF000));
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/*
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* Read the IDs.
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*/
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for (i = 0; i < 4; ++i)
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c_pidr[i] = ROM_READ(c_base, 0xfe0, i) & 0xff;
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for (i = 0; i < 3; ++i)
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c_pidr[i + 4] = ROM_READ(c_base, 0xfd0, i) & 0xff;
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for (i = 0; i < 4; ++i)
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c_cidr[i] = ROM_READ(c_base, 0xff0, i) & 0xff;
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table_type = ROM_READ(c_base, 0xfcc, 0);
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rtems_debugger_printf(" > Base: %p, start: 0x%" PRIx32 "\n",
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c_base,
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/* component may take multiple 4K pages */
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(uint32_t)((intptr_t) c_base - 0x1000 * (c_pidr[4] >> 4)));
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rtems_debugger_printf(" Class is 0x%x, %s\n",
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(c_cidr[1] >> 4) & 0xf, table_class[(c_cidr[1] >> 4) & 0xf]);
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if (((c_cidr[1] >> 4) & 0x0f) == 1) {
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arm_debug_dump_rom_table(c_base, depth + 1);
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}
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else if (((c_cidr[1] >> 4) & 0x0f) == 9) {
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const char* major = "reserved";
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const char* subtype = "reserved";
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unsigned minor = (table_type >> 4) & 0x0f;
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switch (table_type & 0x0f) {
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case 0:
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major = "Miscellaneous";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 4:
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subtype = "Validation component";
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break;
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}
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break;
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case 1:
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major = "Trace Sink";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Port";
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break;
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case 2:
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subtype = "Buffer";
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break;
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case 3:
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subtype = "Router";
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break;
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}
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break;
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case 2:
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major = "Trace Link";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Funnel, router";
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break;
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case 2:
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subtype = "Filter";
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break;
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case 3:
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subtype = "FIFO, buffer";
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break;
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}
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break;
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case 3:
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major = "Trace Source";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Processor";
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break;
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case 2:
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subtype = "DSP";
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break;
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case 3:
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subtype = "Engine/Coprocessor";
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break;
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case 4:
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subtype = "Bus";
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break;
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case 6:
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subtype = "Software";
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break;
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}
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break;
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case 4:
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major = "Debug Control";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Trigger Matrix";
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break;
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case 2:
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subtype = "Debug Auth";
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break;
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case 3:
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subtype = "Power Requestor";
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break;
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}
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break;
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case 5:
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major = "Debug Logic";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Processor";
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break;
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case 2:
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subtype = "DSP";
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break;
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case 3:
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subtype = "Engine/Coprocessor";
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break;
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case 4:
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subtype = "Bus";
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break;
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case 5:
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subtype = "Memory";
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}
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break;
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case 6:
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major = "Perfomance Monitor";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Processor";
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break;
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case 2:
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subtype = "DSP";
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break;
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case 3:
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subtype = "Engine/Coprocessor";
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break;
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case 4:
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subtype = "Bus";
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break;
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case 5:
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subtype = "Memory";
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break;
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}
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break;
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}
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rtems_debugger_printf(" Type: 0x%02" PRIx32 ", %s, %s\n",
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table_type & 0xff, major, subtype);
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rtems_debugger_printf(" PID[4..0]: %02x %02x %02x %02x %02x\n",
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c_pidr[4], c_pidr[3], c_pidr[2], c_pidr[1], c_pidr[0]);
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if (((c_cidr[1] >> 4) & 0x0f) == 1) {
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arm_debug_dump_rom_table(c_base, depth + 1);
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}
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}
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}
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}
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static int
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arm_debug_rom_discover(uint32_t* rom, uint32_t comp, uint32_t** addr, int* index)
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{
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size_t r = 0;
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*addr = 0;
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while ((rom[r] & 1) != 0) {
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uint32_t* c_base = (uint32_t*) ((intptr_t) rom + (rom[r] & 0xfffff000));
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uint32_t c_cid1 = c_base[0xff4 / sizeof(uint32_t)];
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uint32_t type;
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if (((c_cid1 >> 4) & 0x0f) == 1) {
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if (arm_debug_rom_discover(c_base, comp, addr, index))
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return true;
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}
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type = c_base[0xfcc / sizeof(uint32_t)] & 0xff;
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if (comp == type) {
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if (*index > 0)
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--(*index);
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else {
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*addr = c_base;
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return true;
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}
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}
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++r;
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}
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return false;
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}
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static int
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arm_debug_mmap_enable(rtems_debugger_target* target, uint32_t dbgdidr)
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{
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uint32_t rom;
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uint32_t val;
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void* abort_handler;
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int rc = -1;
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@@ -562,15 +832,29 @@ arm_debug_mmap_enable(rtems_debugger_target* target, uint32_t dbgdidr)
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arm_debug_retries = 5;
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/*
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* The DBGDSAR is a signed offset from DBGDRAR. Both need to be
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* valid for the debug register address to be valid. Currently there
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* is no support to decode a ROM table.
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* The DBGDSAR (DSAR) is a signed offset from DBGDRAR. Both need to
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* be valid for the debug register address to be valid. Read the
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* DBGRAR first.
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*/
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ARM_CP14_READ(rom, 1, 0, 0);
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if ((rom & 3) == 3) {
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ARM_CP14_READ(val, 2, 0, 0);
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if ((val & 3) == 3 ) {
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debug_registers = (void*) ((rom & ~3) + ((int32_t) (val & ~3)));
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ARM_CP14_READ(val, 1, 0, 0);
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if ((val & 3) == 3) {
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uint32_t* rom = (uint32_t*) (val & 0xfffff000);
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uint32_t* comp_base = NULL;
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int core = (int) _SMP_Get_current_processor();
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if (ARM_DUMP_ROM_TABLES)
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arm_debug_dump_rom_table(rom, 0);
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debug_registers = NULL;
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if (arm_debug_rom_discover(rom, 0x15, &comp_base, &core)) {
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debug_registers = comp_base;
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rtems_debugger_printf("rtems-db: ram debug: ROM Base: %p\n", comp_base);
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} else {
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ARM_CP14_READ(val, 2, 0, 0);
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if ((val & 3) == 3 ) {
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debug_registers = (void*) ((intptr_t) rom + (val & ~3));
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}
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}
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}
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@@ -580,6 +864,7 @@ arm_debug_mmap_enable(rtems_debugger_target* target, uint32_t dbgdidr)
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rtems_debugger_printf("rtems-db: arm debug: no valid register map\n");
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return -1;
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}
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rtems_debugger_printf("rtems-db: arm debug: BSP Base: %p\n", debug_registers);
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}
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/*
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