arm/xilinx-zynqmp-rpu: Add split mode BSP variants

Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to
emphasize that this BSP is for the lock-step mode RPU configuration.
Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split
mode RPU configuration for core 0 and 1 respectively.

bsps/arm/xilinx-zynqmp-rpu/include/bsp.h

@@ -56,7 +56,6 @@
 #include <rtems.h>
 
 #include <bsp/default-initial-extension.h>
-#include <bsp/start.h>
 
 #include <dev/serial/zynq-uart-zynqmp.h>
 
@@ -69,12 +68,9 @@ extern "C" {
 
 #define BSP_ARM_GIC_DIST_BASE 0xF9000000
 
-/**
+#if !defined(ZYNQMP_RPU_LOCK_STEP_MODE) && ZYNQMP_RPU_CORE_INDEX != 0
- * @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
+#define BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY
- *
+#endif
- * Provide in the application to override the defaults in the BSP.
- */
-BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void);
 
 void zynqmp_debug_console_flush(void);
 

bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h

@@ -41,6 +41,7 @@
 
 #include <rtems.h>
 
+#include <bspopts.h>
 #include <dev/irq/arm-gic-irq.h>
 #include <peripheral_maps/xilinx_zynqmp.h>
 
@@ -48,6 +49,10 @@
 extern "C" {
 #endif /* __cplusplus */
 
+#ifndef ZYNQMP_RPU_LOCK_STEP_MODE
+#define BSP_IRQ_HAVE_GET_SET_AFFINITY
+#endif
+
 #define BSP_INTERRUPT_VECTOR_COUNT 188
 
 /** @} */

bsps/arm/xilinx-zynqmp-rpu/include/bsp/memory.h

@@ -0,0 +1,107 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMZynqMPRPU
+ *
+ * @brief This header file provides BSP-specific memory interfaces.
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2023 Reflex Aerospace GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQMP_RPU_BSP_MEMORY_H
+#define LIBBSP_ARM_XILINX_ZYNQMP_RPU_BSP_MEMORY_H
+
+#include <rtems/score/armv7-pmsa.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @addtogroup RTEMSBSPsARMZynqMPRPU
+ *
+ * @{
+ */
+
+extern char zynqmp_memory_atcm_begin[];
+extern char zynqmp_memory_atcm_end[];
+extern char zynqmp_memory_atcm_size[];
+
+extern char zynqmp_memory_btcm_begin[];
+extern char zynqmp_memory_btcm_end[];
+extern char zynqmp_memory_btcm_size[];
+
+extern char zynqmp_memory_ddr_begin[];
+extern char zynqmp_memory_ddr_end[];
+extern char zynqmp_memory_ddr_size[];
+
+extern char zynqmp_memory_nocache_begin[];
+extern char zynqmp_memory_nocache_end[];
+extern char zynqmp_memory_nocache_size[];
+
+extern char zynqmp_memory_devpl_begin[];
+extern char zynqmp_memory_devpl_end[];
+extern char zynqmp_memory_devpl_size[];
+
+extern char zynqmp_memory_devps_begin[];
+extern char zynqmp_memory_devps_end[];
+extern char zynqmp_memory_devps_size[];
+
+extern char zynqmp_memory_ocm_begin[];
+extern char zynqmp_memory_ocm_end[];
+extern char zynqmp_memory_ocm_size[];
+
+/**
+ * @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
+ *
+ * Provide in the application to override the defaults in the BSP.
+ */
+void zynqmp_setup_mpu_and_cache(void);
+
+/**
+ * @brief This table defines the Zynq UltraScale+ MPSoC or RFSoC specific MPU
+ * regions.
+ *
+ * The table entry count is provided by ::zynqmp_mpu_region_count.
+ *
+ * The application may provide this table to override the defaults in the BSP.
+ */
+extern const ARMV7_PMSA_Region zynqmp_mpu_regions[];
+
+/**
+ * @brief This constant contains the entry count of the ::zynqmp_mpu_regions
+ *   table.
+ */
+extern const size_t zynqmp_mpu_region_count;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQMP_RPU_BSP_MEMORY_H */

bsps/arm/xilinx-zynqmp-rpu/start/bspstarthooks.c

@@ -34,8 +34,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <bsp.h>
 #include <bsp/start.h>
+#include <bsp/memory.h>
 
 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
 {

bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c

@@ -36,117 +36,23 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <bsp.h>
+#include <bsp/memory.h>
 #include <bsp/start.h>
 
 #include <xil_mpu.h>
 #include <xil_cache.h>
 #include <xreg_cortexr5.h>
 
-static BSP_START_TEXT_SECTION void zynqmp_configure_mpu_sections(void);
-
-/*
- * Make weak and let the user override.
- */
-BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void) __attribute__ ((weak));
-
 BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void)
 {
-  zynqmp_configure_mpu_sections();
+  for (size_t i = 0; i < zynqmp_mpu_region_count; ++i) {
+    const ARMV7_PMSA_Region *region = &zynqmp_mpu_regions[i];
+    if (region->size > 0) {
+      Xil_SetMPURegion(region->begin, region->size, region->attributes);
+    }
+  }
+
   Xil_EnableMPU();
   Xil_DCacheEnable();
   Xil_ICacheEnable();
 }
-
-/*
- * Setup MPU sections.
- *
- * The MPU on the ZynqMP RPU only supports 16 regions.
- * Regions must align on boundaries equal to the size of the region
- * Regions may overlap or be nested with the later definition taking precedence
- *
- * Note: LWIP for Zynq requires an available region in xemacpsif_dma.c:init_dma()
- *       this is used for the BD memory.
- *
- * The following code attempts to implement the section map from Init_MPU() in
- * https://github.com/Xilinx/embeddedsw/blob/master/lib/bsp/standalone/src/arm/cortexr5/platform/ZynqMP/mpu.c
- * and from ARMV7_CP15_START_DEFAULT_SECTIONS in bsps/arm/include/bsp/arm-cp15-start.h
- * Due to the limitation on number of regions, some compromises have been made.
- *  - Merges device memories instead of configuring each one independently
- *  - For DRAM, assumes a baseline of `Normal write-back Cacheable` `Full Access`
- *    then uses precedence to set no-cache and RO sections
- *
- * Reference:
- * https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/System-Address-Map-Interconnects
- * https://developer.arm.com/documentation/ddi0460/c/Memory-Protection-Unit
- *
- *|                 | Memory Range            | Attributes of MPURegion     |
- *|-----------------|-------------------------|-----------------------------|
- *| DDR             | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
- *|  -rodata        |                         |  + PRIV_RO_USER_RO          |
- *|  -nocache       |                         | Normal non-cacheable        |
- *|  -nocachenoload |                         | Normal non-cacheable        |
- *| PL              | 0x80000000 - 0xBFFFFFFF | Strongly Ordered            |
- *| Devices         | 0xC0000000 - 0xFFFFFFFF | Device Memory               |
- *| -QSPI           | 0xC0000000 - 0xDFFFFFFF |                             |
- *| -PCIe           | 0xE0000000 - 0xEFFFFFFF |                             |
- *| -Reserved       | 0xF0000000 - 0xF7FFFFFF |                             |
- *| -STM_CORESIGHT  | 0xF8000000 - 0xF8FFFFFF |                             |
- *| -RPU_R5_GIC     | 0xF9000000 - 0xF90FFFFF |                             |
- *| -Reserved       | 0xF9100000 - 0xFCFFFFFF |                             |
- *| -FPS            | 0xFD000000 - 0xFDFFFFFF |                             |
- *| -LPS            | 0xFE000000 - 0xFFFFFFFF | (1)                         |
- *| OCM             | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable |
- *
- * Note 1: Actual range for LPS goes to 0xFFBFFFFF,  to use less sections go to
- *         0xFFFFFFFF and use precedence to configure OCM
- */
-
-static BSP_START_TEXT_SECTION void zynqmp_configure_mpu_sections(void)
-{
-  u32 addr;
-  u64 size;
-  u32 attrib;
-
-  // Configure baseline DDR memory 0x00000000 - 0x7FFFFFFF
-  addr = 0x00000000U;
-  size = 0x80000000U;
-  attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
-  Xil_SetMPURegion(addr, size, attrib);
-
-  // Configure PL interfaces 0x80000000 - 0xBFFFFFFF
-  addr = 0x80000000U;
-  size = 0x40000000U;
-  attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW;
-  Xil_SetMPURegion(addr, size, attrib);
-
-  // Configure devices 0xC0000000 - 0xFFFFFFFF
-  addr = 0xC0000000U;
-  size = 0x40000000U;
-  attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW;
-  Xil_SetMPURegion(addr, size, attrib);
-
-  // Configure OCM 0xFFFC0000 - 0xFFFFFFFF
-  addr = 0xFFFC0000U;
-  size = 0x00040000U;
-  attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
-  Xil_SetMPURegion(addr, size, attrib);
-
-  // Add RO region for RO section
-  addr = (u32) bsp_section_rodata_begin;
-  size = bsp_section_rodata_end - bsp_section_rodata_begin;
-  attrib = NORM_NSHARED_WB_WA | PRIV_RO_USER_RO;
-  Xil_SetMPURegion(addr, size, attrib);
-
-  // Add no cache region for no cache section
-  addr = (u32) bsp_section_nocache_begin;
-  size = bsp_section_nocache_end - bsp_section_nocache_begin;
-  attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
-  Xil_SetMPURegion(addr, size, attrib);
-
-  // Add no cache region for no cache no load section
-  addr = (u32) bsp_section_nocachenoload_begin;
-  size = bsp_section_nocachenoload_end - bsp_section_nocachenoload_begin;
-  attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
-  Xil_SetMPURegion(addr, size, attrib);
-}

bsps/arm/xilinx-zynqmp-rpu/start/mpu-config.c

@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMZynqMPRPU
+ *
+ * @brief This source file contains the implementation of
+ * zynqmp_setup_mpu_and_cache().
+ */
+
+/*
+ * Copyright (C) 2023 Reflex Aerospace GmbH
+ *
+ * Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/memory.h>
+#include <bsp/start.h>
+
+#include <xreg_cortexr5.h>
+
+BSP_START_DATA_SECTION const ARMV7_PMSA_Region
+zynqmp_mpu_regions[] = {
+  {
+    .begin = (uintptr_t)zynqmp_memory_atcm_begin,
+    .size = (uintptr_t)zynqmp_memory_atcm_size,
+    .attributes = NORM_NSHARED_NCACHE | PRIV_RW_USER_RW,
+  }, {
+    .begin = (uintptr_t)zynqmp_memory_btcm_begin,
+    .size = (uintptr_t)zynqmp_memory_btcm_size,
+    .attributes = NORM_NSHARED_NCACHE | PRIV_RW_USER_RW,
+  }, {
+    .begin = (uintptr_t)zynqmp_memory_ddr_begin,
+    .size = (uintptr_t)zynqmp_memory_ddr_size,
+    .attributes = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW,
+  }, {
+    .begin = (uintptr_t)zynqmp_memory_devpl_begin,
+    .size = (uintptr_t)zynqmp_memory_devpl_size,
+    .attributes = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW,
+  }, {
+    .begin = (uintptr_t)zynqmp_memory_devps_begin,
+    .size = (uintptr_t)zynqmp_memory_devps_size,
+    .attributes = DEVICE_NONSHARED | PRIV_RW_USER_RW,
+  }, {
+    .begin = (uintptr_t)zynqmp_memory_ocm_begin,
+    .size = (uintptr_t)zynqmp_memory_ocm_size,
+    .attributes = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW,
+  }, {
+    .begin = (uintptr_t)bsp_section_rodata_begin,
+    .size = (uintptr_t)bsp_section_rodata_size,
+    .attributes = NORM_NSHARED_WB_WA | PRIV_RO_USER_RO,
+  }, {
+    .begin = (uintptr_t)zynqmp_memory_nocache_begin,
+    .size = (uintptr_t)zynqmp_memory_nocache_size,
+    .attributes = NORM_SHARED_NCACHE | PRIV_RW_USER_RW,
+  }
+};
+
+BSP_START_DATA_SECTION const size_t
+zynqmp_mpu_region_count = RTEMS_ARRAY_SIZE(zynqmp_mpu_regions);

bsps/shared/dev/clock/xil-ttc.c

@@ -38,11 +38,12 @@
  */
 
 #include <bsp.h>
-#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
 #include <bsp/fatal.h>
 #include <dev/clock/xttcps_hw.h>
 #include <rtems/sysinit.h>
 #include <rtems/timecounter.h>
+#include <rtems/score/processormaskimpl.h>
 
 #if XTTCPS_COUNT_VALUE_MASK != UINT32_MAX
 #error "unexpected XTTCPS_COUNT_VALUE_MASK value"
@@ -184,6 +185,16 @@ static void xil_ttc_clock_driver_support_install_isr(
 {
   rtems_status_code sc;
 
+#if !defined(ZYNQMP_RPU_LOCK_STEP_MODE) && ZYNQMP_RPU_SPLIT_INDEX != 0
+  Processor_mask affinity;
+  _Processor_mask_From_uint32_t(
+    &affinity,
+    UINT32_C(1) << ZYNQMP_RPU_SPLIT_INDEX,
+    0
+  );
+  (void) bsp_interrupt_set_affinity(XIL_CLOCK_TTC_IRQ, &affinity);
+#endif
+
   rtems_interrupt_entry_initialize(
     &xil_ttc_interrupt_entry,
     handler,

spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu.yml

@@ -1,6 +1,6 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 arch: arm
-bsp: xilinx_zynqmp_rpu
+bsp: zynqmp_rpu_lock_step
 build-type: bsp
 cflags: []
 copyrights:

spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu0.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: zynqmp_rpu_split_0
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH
+cppflags: []
+enabled-by: true
+family: xilinx-zynqmp-rpu
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+source: []
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu1.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: zynqmp_rpu_split_1
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH
+cppflags: []
+enabled-by: true
+family: xilinx-zynqmp-rpu
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+source: []
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml

@@ -18,6 +18,38 @@ links:
   uid: ../start
 - role: build-dependency
   uid: abi
+- role: build-dependency
+  uid: optlockstep
+- role: build-dependency
+  uid: optsplitindex
+- role: build-dependency
+  uid: optmematcmori
+- role: build-dependency
+  uid: optmematcmlen
+- role: build-dependency
+  uid: optmembtcmori
+- role: build-dependency
+  uid: optmembtcmlen
+- role: build-dependency
+  uid: optmemocmori
+- role: build-dependency
+  uid: optmemocmlen
+- role: build-dependency
+  uid: optmemddrori
+- role: build-dependency
+  uid: optmemddrlen
+- role: build-dependency
+  uid: optmemnocacheori
+- role: build-dependency
+  uid: optmemnocachelen
+- role: build-dependency
+  uid: optmemdevplori
+- role: build-dependency
+  uid: optmemdevpllen
+- role: build-dependency
+  uid: optmemdevpsori
+- role: build-dependency
+  uid: optmemdevpslen
 - role: build-dependency
   uid: optclkuart
 - role: build-dependency
@@ -28,22 +60,8 @@ links:
   uid: ../../optxilclockttcirq
 - role: build-dependency
   uid: ../../optxilclockttcrefclk
-- role: build-dependency
-  uid: optint0len
-- role: build-dependency
-  uid: optint0ori
-- role: build-dependency
-  uid: optint1len
-- role: build-dependency
-  uid: optint1ori
-- role: build-dependency
-  uid: optramlen
-- role: build-dependency
-  uid: optramori
 - role: build-dependency
   uid: optresetvec
-- role: build-dependency
-  uid: optnocachelen
 - role: build-dependency
   uid: obj
 - role: build-dependency
@@ -64,6 +82,8 @@ links:
   uid: ../../opto2
 - role: build-dependency
   uid: linkcmds
+- role: build-dependency
+  uid: linkcmdsmemory
 - role: build-dependency
   uid: ../../bspopts
 - role: build-dependency

spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml

@@ -1,35 +1,28 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 build-type: config-file
 content: |
-  MEMORY {
+  INCLUDE linkcmds.memory
-    RAM_INT_0 : ORIGIN = ${ZYNQMP_RPU_RAM_INT_0_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_INT_0_LENGTH:#010x}
-    RAM_INT_1 : ORIGIN = ${ZYNQMP_RPU_RAM_INT_1_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_INT_1_LENGTH:#010x}
-    RAM       : ORIGIN = ${ZYNQMP_RPU_RAM_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_LENGTH:#010x} - ${ZYNQMP_RPU_RAM_NOCACHE_LENGTH:#010x}
-    NOCACHE   : ORIGIN = ${ZYNQMP_RPU_RAM_ORIGIN:#010x} + ${ZYNQMP_RPU_RAM_LENGTH:#010x} - ${ZYNQMP_RPU_RAM_NOCACHE_LENGTH:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_NOCACHE_LENGTH:#010x}
-  }
 
-  REGION_ALIAS ("REGION_START",          RAM_INT_0);
+  REGION_ALIAS ("REGION_START", ATCM);
-  REGION_ALIAS ("REGION_VECTOR",         RAM_INT_0);
+  REGION_ALIAS ("REGION_VECTOR", ATCM);
-  REGION_ALIAS ("REGION_TEXT",           RAM);
+  REGION_ALIAS ("REGION_TEXT", DDR);
-  REGION_ALIAS ("REGION_TEXT_LOAD",      RAM);
+  REGION_ALIAS ("REGION_TEXT_LOAD", DDR);
-  REGION_ALIAS ("REGION_RODATA",         RAM);
+  REGION_ALIAS ("REGION_RODATA", DDR);
-  REGION_ALIAS ("REGION_RODATA_LOAD",    RAM);
+  REGION_ALIAS ("REGION_RODATA_LOAD", DDR);
-  REGION_ALIAS ("REGION_DATA",           RAM);
+  REGION_ALIAS ("REGION_DATA", DDR);
-  REGION_ALIAS ("REGION_DATA_LOAD",      RAM);
+  REGION_ALIAS ("REGION_DATA_LOAD", DDR);
-  REGION_ALIAS ("REGION_FAST_TEXT",      RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT", ATCM);
-  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ATCM);
-  REGION_ALIAS ("REGION_FAST_DATA",      RAM);
+  REGION_ALIAS ("REGION_FAST_DATA", ${ZYNQMP_MEMORY_ATCM_OR_BTCM});
-  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", ${ZYNQMP_MEMORY_ATCM_OR_BTCM});
-  REGION_ALIAS ("REGION_BSS",            RAM);
+  REGION_ALIAS ("REGION_BSS", DDR);
-  REGION_ALIAS ("REGION_WORK",           RAM);
+  REGION_ALIAS ("REGION_WORK", DDR);
-  REGION_ALIAS ("REGION_STACK",          RAM);
+  REGION_ALIAS ("REGION_STACK", ${ZYNQMP_MEMORY_ATCM_OR_BTCM});
-  REGION_ALIAS ("REGION_NOCACHE",        NOCACHE);
+  REGION_ALIAS ("REGION_NOCACHE", NOCACHE);
-  REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
+  REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE);
 
   bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
 
-  bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
-
   bsp_vector_table_in_start_section = 1;
 
   INCLUDE linkcmds.armv4
@@ -38,7 +31,7 @@ content: |
   _stack_end = bsp_section_stack_end;
   __undef_stack = bsp_section_stack_begin;
 copyrights:
-- Copyright (C) 2023 Reflex Aerospace GmbH
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
 enabled-by: true
 install-path: ${BSP_LIBDIR}
 links: []

spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmdsmemory.yml

@@ -0,0 +1,47 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  MEMORY {
+    ATCM : ORIGIN = ${ZYNQMP_MEMORY_ATCM_ORIGIN:#010x}, LENGTH = ${ZYNQMP_MEMORY_ATCM_LENGTH:#010x}
+    BTCM : ORIGIN = ${ZYNQMP_MEMORY_BTCM_ORIGIN:#010x}, LENGTH = ${ZYNQMP_MEMORY_BTCM_LENGTH:#010x}
+    DDR : ORIGIN = ${ZYNQMP_MEMORY_DDR_ORIGIN:#010x}, LENGTH = ${ZYNQMP_MEMORY_DDR_LENGTH:#010x}
+    NOCACHE : ORIGIN = ${ZYNQMP_MEMORY_NOCACHE_ORIGIN:#010x}, LENGTH = ${ZYNQMP_MEMORY_NOCACHE_LENGTH:#010x}
+    DEVPL : ORIGIN = ${ZYNQMP_MEMORY_DEVPL_ORIGIN:#010x}, LENGTH = ${ZYNQMP_MEMORY_DEVPL_LENGTH:#010x}
+    DEVPS : ORIGIN = ${ZYNQMP_MEMORY_DEVPS_ORIGIN:#010x}, LENGTH = ${ZYNQMP_MEMORY_DEVPS_LENGTH:#010x}
+    OCM : ORIGIN = ${ZYNQMP_MEMORY_OCM_ORIGIN:#010x}, LENGTH = ${ZYNQMP_MEMORY_OCM_LENGTH:#010x}
+  }
+
+  zynqmp_memory_atcm_begin = ORIGIN (ATCM);
+  zynqmp_memory_atcm_end = ORIGIN (ATCM) + LENGTH (ATCM);
+  zynqmp_memory_atcm_size = LENGTH (ATCM);
+
+  zynqmp_memory_btcm_begin = ORIGIN (BTCM);
+  zynqmp_memory_btcm_end = ORIGIN (BTCM) + LENGTH (BTCM);
+  zynqmp_memory_btcm_size = LENGTH (BTCM);
+
+  zynqmp_memory_ddr_begin = ORIGIN (DDR);
+  zynqmp_memory_ddr_end = ORIGIN (DDR) + LENGTH (DDR);
+  zynqmp_memory_ddr_size = LENGTH (DDR);
+
+  zynqmp_memory_nocache_begin = ORIGIN (NOCACHE);
+  zynqmp_memory_nocache_end = ORIGIN (NOCACHE) + LENGTH (NOCACHE);
+  zynqmp_memory_nocache_size = LENGTH (NOCACHE);
+
+  zynqmp_memory_devpl_begin = ORIGIN (DEVPL);
+  zynqmp_memory_devpl_end = ORIGIN (DEVPL) + LENGTH (DEVPL);
+  zynqmp_memory_devpl_size = LENGTH (DEVPL);
+
+  zynqmp_memory_devps_begin = ORIGIN (DEVPS);
+  zynqmp_memory_devps_end = ORIGIN (DEVPS) + LENGTH (DEVPS);
+  zynqmp_memory_devps_size = LENGTH (DEVPS);
+
+  zynqmp_memory_ocm_begin = ORIGIN (OCM);
+  zynqmp_memory_ocm_end = ORIGIN (OCM) + LENGTH (OCM);
+  zynqmp_memory_ocm_size = LENGTH (OCM);
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds.memory
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/obj.yml

@@ -14,6 +14,7 @@ install:
 - destination: ${BSP_INCLUDEDIR}/bsp
   source:
   - bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
+  - bsps/arm/xilinx-zynqmp-rpu/include/bsp/memory.h
 - destination: ${BSP_INCLUDEDIR}/peripheral_maps
   source:
   - bsps/include/peripheral_maps/xilinx_zynqmp.h
@@ -28,6 +29,7 @@ source:
 - bsps/arm/xilinx-zynqmp-rpu/start/bspstart.c
 - bsps/arm/xilinx-zynqmp-rpu/start/bspstarthooks.c
 - bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
+- bsps/arm/xilinx-zynqmp-rpu/start/mpu-config.c
 - bsps/shared/dev/clock/xil-ttc.c
 - bsps/shared/dev/btimer/btimer-cpucounter.c
 - bsps/shared/dev/getentropy/getentropy-cpucounter.c

spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml

@@ -1,18 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-integer: null
-- assert-uint32: null
-- env-assign: null
-- format-and-define: null
-build-type: option
-copyrights:
-- Copyright (C) 2020 embedded brains GmbH & Co. KG
-default:
-- enabled-by: true
-  value: 0x00010000
-description: ''
-enabled-by: true
-format: '{:#010x}'
-links: []
-name: ZYNQMP_RPU_RAM_INT_0_LENGTH
-type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optlockstep.yml

@@ -0,0 +1,37 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+- env-enable: null
+- comment: |
+    In lock step mode, the ATCM and BTCM can be used together as a contiguous
+    memory region.  In this case, we set the ATCM size to the combined size,
+    the BTCM size is set to zero, and the ZYNQMP_MEMORY_ATCM_OR_BTCM
+    environment variable is set to ATCM.  In split mode, the ATCM and BTCM are
+    separate memory regions.  In this case, the ZYNQMP_MEMORY_ATCM_OR_BTCM
+    environment variable is set to BTCM.  The ZYNQMP_MEMORY_ATCM_OR_BTCM
+    environment variable is used by the linker script to select memory regions.
+- set-value-enabled-by:
+  - enabled-by: ZYNQMP_RPU_LOCK_STEP_MODE
+    value: ATCM
+  - enabled-by: true
+    value: BTCM
+- env-assign: ZYNQMP_MEMORY_ATCM_OR_BTCM
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by:
+  - arm/zynqmp_rpu_split_0
+  - arm/zynqmp_rpu_split_1
+  value: false
+- enabled-by: true
+  value: true
+description: |
+  If this option is true, then the Cortex-R5F cores of the RPU shall operate in
+  lock-step mode, otherwise they shall operate in split mode.
+enabled-by: true
+format: '{}'
+links: []
+name: ZYNQMP_RPU_LOCK_STEP_MODE
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmematcmlen.yml

@@ -0,0 +1,22 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: ZYNQMP_RPU_LOCK_STEP_MODE
+  value: 0x00040000
+- enabled-by: true
+  value: 0x00020000
+description: |
+  This option defines the length in bytes of the tightly-coupled memory A
+  (ATCM).
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_MEMORY_ATCM_LENGTH
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmematcmori.yml

@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x00000000
+description: |
+  This option defines the address of the tightly-coupled memory A (ATCM)
+  origin.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_MEMORY_ATCM_ORIGIN
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmembtcmlen.yml

@@ -0,0 +1,22 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: ZYNQMP_RPU_LOCK_STEP_MODE
+  value: 0x00000000
+- enabled-by: true
+  value: 0x00020000
+description: |
+  This option defines the length in bytes of the tightly-coupled memory B
+  (BTCM).
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_MEMORY_BTCM_LENGTH
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmembtcmori.yml

@@ -6,13 +6,15 @@ actions:
 - format-and-define: null
 build-type: option
 copyrights:
-- Copyright (C) 2020 embedded brains GmbH & Co. KG
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
 default:
 - enabled-by: true
   value: 0x00020000
-description: ''
+description: |
+  This option defines the address for the tightly-coupled memory B (BTCM)
+  origin.
 enabled-by: true
 format: '{:#010x}'
 links: []
-name: ZYNQMP_RPU_RAM_INT_1_ORIGIN
+name: ZYNQMP_MEMORY_BTCM_ORIGIN
 type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemddrlen.yml

@@ -0,0 +1,24 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by:
+    not: ZYNQMP_RPU_LOCK_STEP_MODE
+  value: 0x20000000
+- enabled-by: true
+  value: 0x40000000
+description: |
+  This option defines the length in bytes of the DDR memory area used by the
+  RPU.  If the non-cacheble memory area is located in the DDR memory, then this
+  area shall be excluded from the area specified by this option.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_MEMORY_DDR_LENGTH
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemddrori.yml

@@ -0,0 +1,23 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: ZYNQMP_RPU_SPLIT_INDEX_1
+  value: 0x60000000
+- enabled-by: true
+  value: 0x40000000
+description: |
+  This option defines the address of the DDR memory area used by the RPU.  If
+  the non-cacheble memory area is located in the DDR memory, then this area
+  shall be excluded from the area specified by this option.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_MEMORY_DDR_ORIGIN
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemdevpllen.yml

@@ -6,13 +6,14 @@ actions:
 - format-and-define: null
 build-type: option
 copyrights:
-- Copyright (C) 2020 embedded brains GmbH & Co. KG
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
 default:
 - enabled-by: true
-  value: 0x00010000
+  value: 0x40000000
-description: ''
+description: |
+  This option defines the length in bytes of the PL device memory area.
 enabled-by: true
 format: '{:#010x}'
 links: []
-name: ZYNQMP_RPU_RAM_INT_1_LENGTH
+name: ZYNQMP_MEMORY_DEVPL_LENGTH
 type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemdevplori.yml

@@ -6,14 +6,14 @@ actions:
 - format-and-define: null
 build-type: option
 copyrights:
-- Copyright (C) 2020 embedded brains GmbH & Co. KG
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
 default:
 - enabled-by: true
-  value: 0x00100000
+  value: 0x80000000
 description: |
-  length of nocache RAM region
+  This option defines the address of the PL device memory area.
 enabled-by: true
 format: '{:#010x}'
 links: []
-name: ZYNQMP_RPU_RAM_NOCACHE_LENGTH
+name: ZYNQMP_MEMORY_DEVPL_ORIGIN
 type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemdevpslen.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x40000000
+description: |
+  This option defines the length in bytes of the PL device memory area.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_MEMORY_DEVPS_LENGTH
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemdevpsori.yml

@@ -6,14 +6,14 @@ actions:
 - format-and-define: null
 build-type: option
 copyrights:
-- Copyright (C) 2020 embedded brains GmbH & Co. KG
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
 default:
 - enabled-by: true
-  value: 0x10000000
+  value: 0xc0000000
 description: |
-  override a BSP's default RAM length
+  This option defines the address of the PL device memory area.
 enabled-by: true
 format: '{:#010x}'
 links: []
-name: ZYNQMP_RPU_RAM_LENGTH
+name: ZYNQMP_MEMORY_DEVPS_ORIGIN
 type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemnocachelen.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x00000000
+description: |
+  This option defines the length in bytes of the non-cacheable memory area.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_MEMORY_NOCACHE_LENGTH
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemnocacheori.yml

@@ -6,13 +6,14 @@ actions:
 - format-and-define: null
 build-type: option
 copyrights:
-- Copyright (C) 2020 embedded brains GmbH & Co. KG
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
 default:
 - enabled-by: true
   value: 0x00000000
-description: ''
+description: |
+  This option defines the address of the non-cacheable memory area.
 enabled-by: true
 format: '{:#010x}'
 links: []
-name: ZYNQMP_RPU_RAM_INT_0_ORIGIN
+name: ZYNQMP_MEMORY_NOCACHE_ORIGIN
 type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemocmlen.yml

@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x00040000
+description: |
+  This option defines the length in bytes of the On-Chip Memory (OCM).
+  Please note that the OCM may be also used by bootloaders or the
+  ARM Trusted Firmware (ATF).
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_MEMORY_OCM_LENGTH
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optmemocmori.yml

@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0xfffc0000
+description: |
+  This option defines the address of the On-Chip Memory (OCM).
+  Please note that the OCM may be also used by bootloaders or the
+  ARM Trusted Firmware (ATF).
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_MEMORY_OCM_ORIGIN
+type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml

@@ -1,17 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-boolean: null
-- define-condition: null
-build-type: option
-copyrights:
-- Copyright (C) 2023 Reflex Aerospace GmbH
-default:
-- enabled-by: true
-  value: true
-description: |
-  Sets the target processing unit to the RPU (R5F) cores.
-enabled-by: true
-format: '{}'
-links: []
-name: ZYNQMP_PROC_UNIT_RPU
-type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml

@@ -1,18 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-integer: null
-- assert-uint32: null
-- env-assign: null
-- format-and-define: null
-build-type: option
-copyrights:
-- Copyright (C) 2020 embedded brains GmbH & Co. KG
-default:
-- enabled-by: true
-  value: 0x00100000
-description: ''
-enabled-by: true
-format: '{:#010x}'
-links: []
-name: ZYNQMP_RPU_RAM_ORIGIN
-type: build

spec/build/bsps/arm/xilinx-zynqmp-rpu/optsplitindex.yml

@@ -0,0 +1,27 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-in-set:
+  - 0
+  - 1
+- format-and-define: null
+- env-assign: null
+- set-value: ZYNQMP_RPU_SPLIT_INDEX_${ZYNQMP_RPU_SPLIT_INDEX}
+- substitute: null
+- env-append: ENABLE
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: arm/zynqmp_rpu_split_1
+  value: 1
+- enabled-by: true
+  value: 0
+description: |
+  This option defines the RPU core index (0 or 1).
+enabled-by:
+  not: ZYNQMP_RPU_LOCK_STEP_MODE
+format: '{}'
+links: []
+name: ZYNQMP_RPU_SPLIT_INDEX
+type: build

spec/build/bsps/optxilclockttcbaseaddr.yml

@@ -6,6 +6,8 @@ build-type: option
 copyrights:
 - Copyright (C) 2024 embedded brains GmbH & Co. KG
 default:
+- enabled-by: ZYNQMP_RPU_SPLIT_INDEX_1
+  value: 0xff110004
 - enabled-by: true
   value: 0xff110000
 description: |

spec/build/bsps/optxilclockttcirq.yml

@@ -6,6 +6,8 @@ build-type: option
 copyrights:
 - Copyright (C) 2024 embedded brains GmbH & Co. KG
 default:
+- enabled-by: ZYNQMP_RPU_SPLIT_INDEX_1
+  value: 69
 - enabled-by: true
   value: 68
 description: |

spec/build/bsps/optzynquartkernbase.yml

@@ -8,6 +8,7 @@ copyrights:
 default:
 - enabled-by:
   - bsps/aarch64/xilinx-zynqmp
+  - ZYNQMP_RPU_SPLIT_INDEX_0
   value: ZYNQ_UART_0_BASE_ADDR
 - enabled-by: true
   value: ZYNQ_UART_1_BASE_ADDR