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More automatically generated. Many files renamed behind the scenes.

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This commit is contained in:
Joel Sherrill
1998-10-19 17:30:01 +00:00
parent e4f7860f54
commit dcc1a53020
10 changed files with 44 additions and 871 deletions
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63
doc/supplements/hppa1_1/Makefile
View File

@@ -20,12 +20,14 @@ dirs:
COMMON_FILES=../../common/cpright.texi ../../common/setup.texi
GENERATED_FILES= \
cpumodel.texi timing.texi wksheets.texi
GENERATED_FILES=\
cpumodel.texi callconv.texi memmodel.texi intr.texi fatalerr.texi \
bsp.texi cputable.texi wksheets.texi
# timing.texi timeBSP.texi
FILES= $(PROJECT).texi \
bsp.texi callconv.texi cputable.texi fatalerr.texi \
intr.texi memmodel.texi preface.texi timetbl.texi timedata.texi \
preface.texi timetbl.texi timedata.texi \
$(GENERATED_FILES)
info: dirs c_hppa1_1
@@ -55,20 +57,43 @@ cpumodel.texi: cpumodel.t Makefile
-u "Top" \
-n "Calling Conventions" ${*}.t
# Calling Conventions
# Memory Model
callconv.texi: callconv.t Makefile
$(BMENU) -p "CPU Model Dependent Features CPU Model Name" \
-u "Top" \
-n "Memory Model" ${*}.t
memmodel.texi: memmodel.t Makefile
$(BMENU) -p "Calling Conventions User-Provided Routines" \
-u "Top" \
-n "Interrupt Processing" ${*}.t
# Interrupt Chapter:
# 1. Replace Times and Sizes
# 2. Build Node Structure
intr.texi: intr.t TIMES
${REPLACE} -p TIMES intr.t
mv intr.t.fixed intr.texi
intr.t: intr_NOTIMES.t SIMHPPA_TIMES
${REPLACE} -p SIMHPPA_TIMES intr_NOTIMES.t
mv intr_NOTIMES.t.fixed intr.t
intr.texi: intr.t Makefile
$(BMENU) -p "Memory Model Flat Memory Model" \
-u "Top" \
fatalerr.texi: fatalerr.t Makefile
$(BMENU) -p "Interrupt Processing Interrupt Stack" \
-u "Top" \
-n "Board Support Packages" ${*}.t
bsp.texi: bsp.t Makefile
$(BMENU) -p "Default Fatal Error Processing Default Fatal Error Handler Operations" \
-u "Top" \
-n "Processor Dependent Information Table" ${*}.t
cputable.texi: cputable.t Makefile
$(BMENU) -p "Board Support Packages Processor Initialization" \
-u "Top" \
-n "Memory Requirements" ${*}.t
# Fatal Error
# BSP
# CPU Table
# Worksheets Chapter:
# 1. Obtain the Shared File
@@ -78,8 +103,8 @@ intr.texi: intr.t TIMES
wksheets_NOTIMES.t: ../../common/wksheets.t
cp ../../common/wksheets.t wksheets_NOTIMES.t
wksheets.t: wksheets_NOTIMES.t TIMES
${REPLACE} -p TIMES wksheets_NOTIMES.t
wksheets.t: wksheets_NOTIMES.t SIMHPPA_TIMES
${REPLACE} -p SIMHPPA_TIMES wksheets_NOTIMES.t
mv wksheets_NOTIMES.t.fixed wksheets.t
wksheets.texi: wksheets.t Makefile
@@ -105,12 +130,12 @@ timetbl.t: ../../common/timetbl.t
sed -e 's/TIMETABLE_NEXT_LINK/Command and Variable Index/' \
<../../common/timetbl.t >timetbl.t
timetbl.texi: timetbl.t TIMES
${REPLACE} -p TIMES timetbl.t
timetbl.texi: timetbl.t SIMHPPA_TIMES
${REPLACE} -p SIMHPPA_TIMES timetbl.t
mv timetbl.t.fixed timetbl.texi
timedata.texi: timedata.t TIMES
${REPLACE} -p TIMES timedata.t
timedata.texi: timedata.t SIMHPPA_TIMES
${REPLACE} -p SIMHPPA_TIMES timedata.t
mv timedata.t.fixed timedata.texi
html: dirs $(FILES)
@@ -123,7 +148,7 @@ clean:
rm -f *.dvi *.ps *.log *.aux *.cp *.fn *.ky *.pg *.toc *.tp *.vr $(BASE)
rm -f $(PROJECT) $(PROJECT)-*
rm -f c_hppa1_1 c_hppa1_1-*
rm -f timedata.texi timetbl.texi timetbl.t intr.texi
rm -f timedata.texi timetbl.texi timetbl.t intr.t
rm -f timing.t timing.texi
rm -f wksheets.t wksheets_NOTIMES.t $(GENERATED_FILES)
rm -f *.fixed _*

247
doc/supplements/hppa1_1/TIMES
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@@ -1,247 +0,0 @@
#
# PA-RISC Timing and Size Information
#
# $Id$
#
#
# CPU Model Information
#
RTEMS_BSP simhppa
RTEMS_CPU_MODEL HP-7100
#
# Interrupt Latency
#
# NOTE: In general, the text says it is hand-calculated to be
# RTEMS_MAXIMUM_DISABLE_PERIOD at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
# Mhz and this was last calculated for Release
# RTEMS_VERSION_FOR_MAXIMUM_DISABLE_PERIOD.
#
RTEMS_MAXIMUM_DISABLE_PERIOD TBD
RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ TBD
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD TBD
#
# Context Switch Times
#
RTEMS_NO_FP_CONTEXTS 1
RTEMS_RESTORE_1ST_FP_TASK 2
RTEMS_SAVE_INIT_RESTORE_INIT 3
RTEMS_SAVE_IDLE_RESTORE_INIT 4
RTEMS_SAVE_IDLE_RESTORE_IDLE 5
#
# Task Manager Times
#
RTEMS_TASK_CREATE_ONLY 6
RTEMS_TASK_IDENT_ONLY 7
RTEMS_TASK_START_ONLY 8
RTEMS_TASK_RESTART_CALLING_TASK 9
RTEMS_TASK_RESTART_SUSPENDED_RETURNS_TO_CALLER 9
RTEMS_TASK_RESTART_BLOCKED_RETURNS_TO_CALLER 10
RTEMS_TASK_RESTART_READY_RETURNS_TO_CALLER 11
RTEMS_TASK_RESTART_SUSPENDED_PREEMPTS_CALLER 12
RTEMS_TASK_RESTART_BLOCKED_PREEMPTS_CALLER 13
RTEMS_TASK_RESTART_READY_PREEMPTS_CALLER 14
RTEMS_TASK_DELETE_CALLING_TASK 15
RTEMS_TASK_DELETE_SUSPENDED_TASK 16
RTEMS_TASK_DELETE_BLOCKED_TASK 17
RTEMS_TASK_DELETE_READY_TASK 18
RTEMS_TASK_SUSPEND_CALLING_TASK 19
RTEMS_TASK_SUSPEND_RETURNS_TO_CALLER 20
RTEMS_TASK_RESUME_TASK_READIED_RETURNS_TO_CALLER 21
RTEMS_TASK_RESUME_TASK_READIED_PREEMPTS_CALLER 22
RTEMS_TASK_SET_PRIORITY_OBTAIN_CURRENT_PRIORITY 23
RTEMS_TASK_SET_PRIORITY_RETURNS_TO_CALLER 24
RTEMS_TASK_SET_PRIORITY_PREEMPTS_CALLER 25
RTEMS_TASK_MODE_OBTAIN_CURRENT_MODE 26
RTEMS_TASK_MODE_NO_RESCHEDULE 27
RTEMS_TASK_MODE_RESCHEDULE_RETURNS_TO_CALLER 28
RTEMS_TASK_MODE_RESCHEDULE_PREEMPTS_CALLER 29
RTEMS_TASK_GET_NOTE_ONLY 30
RTEMS_TASK_SET_NOTE_ONLY 31
RTEMS_TASK_WAKE_AFTER_YIELD_RETURNS_TO_CALLER 32
RTEMS_TASK_WAKE_AFTER_YIELD_PREEMPTS_CALLER 33
RTEMS_TASK_WAKE_WHEN_ONLY 34
#
# Interrupt Manager
#
RTEMS_INTR_ENTRY_RETURNS_TO_NESTED 35
RTEMS_INTR_ENTRY_RETURNS_TO_INTERRUPTED_TASK 36
RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 37
RTEMS_INTR_EXIT_RETURNS_TO_NESTED 38
RTEMS_INTR_EXIT_RETURNS_TO_INTERRUPTED_TASK 39
RTEMS_INTR_EXIT_RETURNS_TO_PREEMPTING_TASK 40
#
# Clock Manager
#
RTEMS_CLOCK_SET_ONLY 41
RTEMS_CLOCK_GET_ONLY 42
RTEMS_CLOCK_TICK_ONLY 43
#
# Timer Manager
#
RTEMS_TIMER_CREATE_ONLY 44
RTEMS_TIMER_IDENT_ONLY 45
RTEMS_TIMER_DELETE_INACTIVE 46
RTEMS_TIMER_DELETE_ACTIVE 47
RTEMS_TIMER_FIRE_AFTER_INACTIVE 48
RTEMS_TIMER_FIRE_AFTER_ACTIVE 49
RTEMS_TIMER_FIRE_WHEN_INACTIVE 50
RTEMS_TIMER_FIRE_WHEN_ACTIVE 51
RTEMS_TIMER_RESET_INACTIVE 52
RTEMS_TIMER_RESET_ACTIVE 53
RTEMS_TIMER_CANCEL_INACTIVE 54
RTEMS_TIMER_CANCEL_ACTIVE 55
#
# Semaphore Manager
#
RTEMS_SEMAPHORE_CREATE_ONLY 56
RTEMS_SEMAPHORE_IDENT_ONLY 57
RTEMS_SEMAPHORE_DELETE_ONLY 58
RTEMS_SEMAPHORE_OBTAIN_AVAILABLE 59
RTEMS_SEMAPHORE_OBTAIN_NOT_AVAILABLE_NO_WAIT 60
RTEMS_SEMAPHORE_OBTAIN_NOT_AVAILABLE_CALLER_BLOCKS 61
RTEMS_SEMAPHORE_RELEASE_NO_WAITING_TASKS 62
RTEMS_SEMAPHORE_RELEASE_TASK_READIED_RETURNS_TO_CALLER 63
RTEMS_SEMAPHORE_RELEASE_TASK_READIED_PREEMPTS_CALLER 64
#
# Message Manager
#
RTEMS_MESSAGE_QUEUE_CREATE_ONLY 65
RTEMS_MESSAGE_QUEUE_IDENT_ONLY 66
RTEMS_MESSAGE_QUEUE_DELETE_ONLY 67
RTEMS_MESSAGE_QUEUE_SEND_NO_WAITING_TASKS 68
RTEMS_MESSAGE_QUEUE_SEND_TASK_READIED_RETURNS_TO_CALLER 69
RTEMS_MESSAGE_QUEUE_SEND_TASK_READIED_PREEMPTS_CALLER 70
RTEMS_MESSAGE_QUEUE_URGENT_NO_WAITING_TASKS 71
RTEMS_MESSAGE_QUEUE_URGENT_TASK_READIED_RETURNS_TO_CALLER 72
RTEMS_MESSAGE_QUEUE_URGENT_TASK_READIED_PREEMPTS_CALLER 73
RTEMS_MESSAGE_QUEUE_BROADCAST_NO_WAITING_TASKS 74
RTEMS_MESSAGE_QUEUE_BROADCAST_TASK_READIED_RETURNS_TO_CALLER 75
RTEMS_MESSAGE_QUEUE_BROADCAST_TASK_READIED_PREEMPTS_CALLER 76
RTEMS_MESSAGE_QUEUE_RECEIVE_AVAILABLE 77
RTEMS_MESSAGE_QUEUE_RECEIVE_NOT_AVAILABLE_NO_WAIT 78
RTEMS_MESSAGE_QUEUE_RECEIVE_NOT_AVAILABLE_CALLER_BLOCKS 79
RTEMS_MESSAGE_QUEUE_FLUSH_NO_MESSAGES_FLUSHED 80
RTEMS_MESSAGE_QUEUE_FLUSH_MESSAGES_FLUSHED 81
#
# Event Manager
#
RTEMS_EVENT_SEND_NO_TASK_READIED 82
RTEMS_EVENT_SEND_TASK_READIED_RETURNS_TO_CALLER 83
RTEMS_EVENT_SEND_TASK_READIED_PREEMPTS_CALLER 84
RTEMS_EVENT_RECEIVE_OBTAIN_CURRENT_EVENTS 85
RTEMS_EVENT_RECEIVE_AVAILABLE 86
RTEMS_EVENT_RECEIVE_NOT_AVAILABLE_NO_WAIT 87
RTEMS_EVENT_RECEIVE_NOT_AVAILABLE_CALLER_BLOCKS 88
#
# Signal Manager
#
RTEMS_SIGNAL_CATCH_ONLY 89
RTEMS_SIGNAL_SEND_RETURNS_TO_CALLER 90
RTEMS_SIGNAL_SEND_SIGNAL_TO_SELF 91
RTEMS_SIGNAL_EXIT_ASR_OVERHEAD_RETURNS_TO_CALLING_TASK 92
RTEMS_SIGNAL_EXIT_ASR_OVERHEAD_RETURNS_TO_PREEMPTING_TASK 93
#
# Partition Manager
#
RTEMS_PARTITION_CREATE_ONLY 94
RTEMS_PARTITION_IDENT_ONLY 95
RTEMS_PARTITION_DELETE_ONLY 96
RTEMS_PARTITION_GET_BUFFER_AVAILABLE 97
RTEMS_PARTITION_GET_BUFFER_NOT_AVAILABLE 98
RTEMS_PARTITION_RETURN_BUFFER_ONLY 99
#
# Region Manager
#
RTEMS_REGION_CREATE_ONLY 100
RTEMS_REGION_IDENT_ONLY 101
RTEMS_REGION_DELETE_ONLY 102
RTEMS_REGION_GET_SEGMENT_AVAILABLE 103
RTEMS_REGION_GET_SEGMENT_NOT_AVAILABLE_NO_WAIT 104
RTEMS_REGION_GET_SEGMENT_NOT_AVAILABLE_CALLER_BLOCKS 105
RTEMS_REGION_RETURN_SEGMENT_NO_WAITING_TASKS 106
RTEMS_REGION_RETURN_SEGMENT_TASK_READIED_RETURNS_TO_CALLER 107
RTEMS_REGION_RETURN_SEGMENT_TASK_READIED_PREEMPTS_CALLER 108
#
# Dual-Ported Memory Manager
#
RTEMS_PORT_CREATE_ONLY 109
RTEMS_PORT_IDENT_ONLY 110
RTEMS_PORT_DELETE_ONLY 111
RTEMS_PORT_INTERNAL_TO_EXTERNAL_ONLY 112
RTEMS_PORT_EXTERNAL_TO_INTERNAL_ONLY 113
#
# IO Manager
#
RTEMS_IO_INITIALIZE_ONLY 114
RTEMS_IO_OPEN_ONLY 115
RTEMS_IO_CLOSE_ONLY 116
RTEMS_IO_READ_ONLY 117
RTEMS_IO_WRITE_ONLY 118
RTEMS_IO_CONTROL_ONLY 119
#
# Rate Monotonic Manager
#
RTEMS_RATE_MONOTONIC_CREATE_ONLY 120
RTEMS_RATE_MONOTONIC_IDENT_ONLY 121
RTEMS_RATE_MONOTONIC_CANCEL_ONLY 122
RTEMS_RATE_MONOTONIC_DELETE_ACTIVE 123
RTEMS_RATE_MONOTONIC_DELETE_INACTIVE 124
RTEMS_RATE_MONOTONIC_PERIOD_INITIATE_PERIOD_RETURNS_TO_CALLER 125
RTEMS_RATE_MONOTONIC_PERIOD_CONCLUDE_PERIOD_CALLER_BLOCKS 126
RTEMS_RATE_MONOTONIC_PERIOD_OBTAIN_STATUS 127
#
# Size Information
#
#
# xxx alloted for numbers
#
RTEMS_DATA_SPACE 128
RTEMS_MINIMUM_CONFIGURATION xx,129
RTEMS_MAXIMUM_CONFIGURATION xx,130
# x,xxx alloted for numbers
RTEMS_CORE_CODE_SIZE x,131
RTEMS_INITIALIZATION_CODE_SIZE x,132
RTEMS_TASK_CODE_SIZE x,133
RTEMS_INTERRUPT_CODE_SIZE x,134
RTEMS_CLOCK_CODE_SIZE x,135
RTEMS_TIMER_CODE_SIZE x,136
RTEMS_SEMAPHORE_CODE_SIZE x,137
RTEMS_MESSAGE_CODE_SIZE x,138
RTEMS_EVENT_CODE_SIZE x,139
RTEMS_SIGNAL_CODE_SIZE x,140
RTEMS_PARTITION_CODE_SIZE x,141
RTEMS_REGION_CODE_SIZE x,142
RTEMS_DPMEM_CODE_SIZE x,143
RTEMS_IO_CODE_SIZE x,144
RTEMS_FATAL_ERROR_CODE_SIZE x,145
RTEMS_RATE_MONOTONIC_CODE_SIZE x,146
RTEMS_MULTIPROCESSING_CODE_SIZE x,147
# xxx alloted for numbers
RTEMS_TIMER_CODE_OPTSIZE 148
RTEMS_SEMAPHORE_CODE_OPTSIZE 149
RTEMS_MESSAGE_CODE_OPTSIZE 150
RTEMS_EVENT_CODE_OPTSIZE 151
RTEMS_SIGNAL_CODE_OPTSIZE 152
RTEMS_PARTITION_CODE_OPTSIZE 153
RTEMS_REGION_CODE_OPTSIZE 154
RTEMS_DPMEM_CODE_OPTSIZE 155
RTEMS_IO_CODE_OPTSIZE 156
RTEMS_RATE_MONOTONIC_CODE_OPTSIZE 157
RTEMS_MULTIPROCESSING_CODE_OPTSIZE 158
# xxx alloted for numbers
RTEMS_BYTES_PER_TASK 159
RTEMS_BYTES_PER_TIMER 160
RTEMS_BYTES_PER_SEMAPHORE 161
RTEMS_BYTES_PER_MESSAGE_QUEUE 162
RTEMS_BYTES_PER_REGION 163
RTEMS_BYTES_PER_PARTITION 164
RTEMS_BYTES_PER_PORT 165
RTEMS_BYTES_PER_PERIOD 166
RTEMS_BYTES_PER_EXTENSION 167
RTEMS_BYTES_PER_FP_TASK 168
RTEMS_BYTES_PER_NODE 169
RTEMS_BYTES_PER_GLOBAL_OBJECT 170
RTEMS_BYTES_PER_PROXY 171
# x,xxx alloted for numbers
RTEMS_BYTES_OF_FIXED_SYSTEM_REQUIREMENTS x,172

72
doc/supplements/hppa1_1/bsp.texi
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@@ -1,72 +0,0 @@
@c
@c COPYRIGHT (c) 1988-1998.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c $Id$
@c
@ifinfo
@node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top
@end ifinfo
@chapter Board Support Packages
@ifinfo
@menu
* Board Support Packages Introduction::
* Board Support Packages System Reset::
* Board Support Packages Processor Initialization::
@end menu
@end ifinfo
@ifinfo
@node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages
@end ifinfo
@section Introduction
An RTEMS Board Support Package (BSP) must be designed
to support a particular processor and target board combination.
This chapter presents a discussion of PA-RISC specific BSP
issues. For more information on developing a BSP, refer to the
chapter titled Board Support Packages in the RTEMS
Applications User's Guide.
@ifinfo
@node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages
@end ifinfo
@section System Reset
An RTEMS based application is initiated or
re-initiated when the PA-RISC processor is reset. The behavior
of a PA-RISC upon reset is implementation defined and thus is
beyond the scope of this manual.
@ifinfo
@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages
@end ifinfo
@section Processor Initialization
The precise requirements for initialization of a
particular implementation of the PA-RISC architecture are
implementation defined. Thus it is impossible to provide exact
details of this procedure in this manual. However, the
requirements of RTEMS which must be satisfied by this
initialization code can be discussed.
RTEMS assumes that interrupts are disabled when the
initialize_executive directive is invoked. Interrupts are
enabled automatically by RTEMS as part of the initialize
executive directive and device driver initialization occurs
after interrupts are enabled. Thus all interrupt sources should
be quiescent until the system's device drivers have been
initialized and installed their interrupt handlers.
If the processor requires initialization of the
cache, then it should be be done during the reset application
initialization code.
Finally, the requirements in the Board Support
Packages chapter of the Applications User's Manual for the
reset code which is executed before the call to initialize
executive must be satisfied.

31
doc/supplements/hppa1_1/callconv.t
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@@ -6,24 +6,8 @@
@c $Id$
@c
@ifinfo
@node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features CPU Model Name, Top
@end ifinfo
@chapter Calling Conventions
@ifinfo
@menu
* Calling Conventions Introduction::
* Calling Conventions Processor Background::
* Calling Conventions Calling Mechanism::
* Calling Conventions Register Usage::
* Calling Conventions Parameter Passing::
* Calling Conventions User-Provided Routines::
@end menu
@end ifinfo
@ifinfo
@node Calling Conventions Introduction, Calling Conventions Processor Background, Calling Conventions, Calling Conventions
@end ifinfo
@section Introduction
Each high-level language compiler generates
@@ -50,9 +34,6 @@ This chapter describes the calling conventions used
by the GNU C and standard HP-UX compilers for the PA-RISC
architecture.
@ifinfo
@node Calling Conventions Processor Background, Calling Conventions Calling Mechanism, Calling Conventions Introduction, Calling Conventions
@end ifinfo
@section Processor Background
The PA-RISC architecture supports a simple yet
@@ -72,9 +53,6 @@ not automatically save or restore any registers. It is the
responsibility of the high-level language compiler to define the
register preservation and usage convention.
@ifinfo
@node Calling Conventions Calling Mechanism, Calling Conventions Register Usage, Calling Conventions Processor Background, Calling Conventions
@end ifinfo
@section Calling Mechanism
All RTEMS directives are invoked as standard
@@ -82,9 +60,6 @@ subroutines via a bl or a blr instruction with the return address
assumed to be in r2 and return to the user application via the
bv instruction.
@ifinfo
@node Calling Conventions Register Usage, Calling Conventions Parameter Passing, Calling Conventions Calling Mechanism, Calling Conventions
@end ifinfo
@section Register Usage
As discussed above, the bl and blr instructions do
@@ -131,9 +106,6 @@ possible to modify the PA-RISC specific code such that all tasks
are considered floating point only when this option is not used.
@end itemize
@ifinfo
@node Calling Conventions Parameter Passing, Calling Conventions User-Provided Routines, Calling Conventions Register Usage, Calling Conventions
@end ifinfo
@section Parameter Passing
RTEMS assumes that the first four (4) arguments are
@@ -160,9 +132,6 @@ as the stack pointer. The standard stack frame consists of a
minimum of sixty-four (64) bytes and is the responsibility of
the callee to maintain.
@ifinfo
@node Calling Conventions User-Provided Routines, Memory Model, Calling Conventions Parameter Passing, Calling Conventions
@end ifinfo
@section User-Provided Routines
All user-provided routines invoked by RTEMS, such as

71
doc/supplements/hppa1_1/cpumodel.texi
View File

@@ -1,71 +0,0 @@
@c
@c COPYRIGHT (c) 1988-1998.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c $Id$
@c
@ifinfo
@node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top
@end ifinfo
@chapter CPU Model Dependent Features
@ifinfo
@menu
* CPU Model Dependent Features Introduction::
* CPU Model Dependent Features CPU Model Name::
@end menu
@end ifinfo
@ifinfo
@node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features, CPU Model Dependent Features
@end ifinfo
@section Introduction
Microprocessors are generally classified into
families with a variety of CPU models or implementations within
that family. Within a processor family, there is a high level
of binary compatibility. This family may be based on either an
architectural specification or on maintaining compatibility with
a popular processor. Recent microprocessor families such as the
SPARC or PA-RISC are based on an architectural specification
which is independent or any particular CPU model or
implementation. Older families such as the M68xxx and the iX86
evolved as the manufacturer strived to produce higher
performance processor models which maintained binary
compatibility with older models.
RTEMS takes advantage of the similarity of the
various models within a CPU family. Although the models do vary
in significant ways, the high level of compatibility makes it
possible to share the bulk of the CPU dependent executive code
across the entire family. Each processor family supported by
RTEMS has a list of features which vary between CPU models
within a family. For example, the most common model dependent
feature regardless of CPU family is the presence or absence of a
floating point unit or coprocessor. When defining the list of
features present on a particular CPU model, one simply notes
that floating point hardware is or is not present and defines a
single constant appropriately. Conditional compilation is
utilized to include the appropriate source code for this CPU
model's feature set. It is important to note that this means
that RTEMS is thus compiled using the appropriate feature set
and compilation flags optimal for this CPU model used. The
alternative would be to generate a binary which would execute on
all family members using only the features which were always
present.
This chapter presents the set of features which vary
across PA-RISC implementations and are of importance to RTEMS.
The set of CPU model feature macros are defined in the file
c/src/exec/score/cpu/hppa1_1/hppa.h based upon the particular CPU
model defined on the compilation command line.
@ifinfo
@node CPU Model Dependent Features CPU Model Name, Calling Conventions, CPU Model Dependent Features Introduction, CPU Model Dependent Features
@end ifinfo
@section CPU Model Name
The macro CPU_MODEL_NAME is a string which designates
the name of this CPU model. For example, for the Hewlett Packard
PA-7100 CPU model, this macro is set to the string "hppa 7100".

132
doc/supplements/hppa1_1/cputable.texi
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@@ -1,132 +0,0 @@
@c
@c COPYRIGHT (c) 1988-1998.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c $Id$
@c
@ifinfo
@node Processor Dependent Information Table, Processor Dependent Information Table Introduction, Board Support Packages Processor Initialization, Top
@end ifinfo
@chapter Processor Dependent Information Table
@ifinfo
@menu
* Processor Dependent Information Table Introduction::
* Processor Dependent Information Table CPU Dependent Information Table::
@end menu
@end ifinfo
@ifinfo
@node Processor Dependent Information Table Introduction, Processor Dependent Information Table CPU Dependent Information Table, Processor Dependent Information Table, Processor Dependent Information Table
@end ifinfo
@section Introduction
Any highly processor dependent information required
to describe a processor to RTEMS is provided in the CPU
Dependent Information Table. This table is not required for all
processors supported by RTEMS. This chapter describes the
contents, if any, for a particular processor type.
@ifinfo
@node Processor Dependent Information Table CPU Dependent Information Table, Memory Requirements, Processor Dependent Information Table Introduction, Processor Dependent Information Table
@end ifinfo
@section CPU Dependent Information Table
The PA-RISC version of the RTEMS CPU Dependent
Information Table contains the information required to interface
a Board Support Package and RTEMS on the PA-RISC. This
information is provided to allow RTEMS to interoperate
effectively with the BSP. The C structure definition is given
here:
@example
typedef struct @{
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void * );
/* end of fields required on all CPUs */
hppa_rtems_isr_entry spurious_handler;
unsigned32 itimer_clicks_per_microsecond; /* for use by Clock driver */
@} rtems_cpu_table;
@end example
@table @code
@item pretasking_hook
is the address of the
user provided routine which is invoked once RTEMS initialization
is complete but before interrupts and tasking are enabled. This
field may be NULL to indicate that the hook is not utilized.
@item predriver_hook
is the address of the user provided
routine which is invoked with tasking enabled immediately before
the MPCI and device drivers are initialized. RTEMS
initialization is complete, interrupts and tasking are enabled,
but no device drivers are initialized. This field may be NULL to
indicate that the hook is not utilized.
@item postdriver_hook
is the address of the user provided
routine which is invoked with tasking enabled immediately after
the MPCI and device drivers are initialized. RTEMS
initialization is complete, interrupts and tasking are enabled,
and the device drivers are initialized. This field may be NULL
to indicate that the hook is not utilized.
@item idle_task
is the address of the optional user
provided routine which is used as the system's IDLE task. If
this field is not NULL, then the RTEMS default IDLE task is not
used. This field may be NULL to indicate that the default IDLE
is to be used.
@item do_zero_of_workspace
indicates whether RTEMS should
zero the Workspace as part of its initialization. If set to
TRUE, the Workspace is zeroed. Otherwise, it is not.
@item idle_task_stack_size
is the size of the RTEMS idle task stack in bytes.
If this number is less than MINIMUM_STACK_SIZE, then the
idle task's stack will be MINIMUM_STACK_SIZE in byte.
@item interrupt_stack_size
is the size of the RTEMS allocated interrupt stack in bytes.
This value must be at least as large as MINIMUM_STACK_SIZE.
@item extra_mpci_receive_server_stack
is the extra stack space allocated for the RTEMS MPCI receive server task
in bytes. The MPCI receive server may invoke nearly all directives and
may require extra stack space on some targets.
@item stack_allocate_hook
is the address of the optional user provided routine which allocates
memory for task stacks. If this hook is not NULL, then a stack_free_hook
must be provided as well.
@item stack_free_hook
is the address of the optional user provided routine which frees
memory for task stacks. If this hook is not NULL, then a stack_allocate_hook
must be provided as well.
@item spurious_handler
is the address of the optional user provided routine which is invoked
when a spurious external interrupt occurs. A spurious interrupt is one
for which no handler is installed.
@item itimer_clicks_per_microsecond
is the number of countdowns in the on-CPU timer which corresponds
to a microsecond. This is a function of the clock speed of the CPU
being used.
@end table

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@@ -1,47 +0,0 @@
@c
@c COPYRIGHT (c) 1988-1998.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c $Id$
@c
@ifinfo
@node Default Fatal Error Processing, Default Fatal Error Processing Introduction, Interrupt Processing Disabling of Interrupts by RTEMS, Top
@end ifinfo
@chapter Default Fatal Error Processing
@ifinfo
@menu
* Default Fatal Error Processing Introduction::
* Default Fatal Error Processing Default Fatal Error Handler Operations::
@end menu
@end ifinfo
@ifinfo
@node Default Fatal Error Processing Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Default Fatal Error Processing, Default Fatal Error Processing
@end ifinfo
@section Introduction
Upon detection of a fatal error by either the
application or RTEMS the fatal error manager is invoked. The
fatal error manager will invoke a user-supplied fatal error
handler. If no user-supplied handler is configured, the RTEMS
provided default fatal error handler is invoked. If the
user-supplied fatal error handler returns to the executive the
default fatal error handler is then invoked. This chapter
describes the precise operations of the default fatal error
handler.
@ifinfo
@node Default Fatal Error Processing Default Fatal Error Handler Operations, Board Support Packages, Default Fatal Error Processing Introduction, Default Fatal Error Processing
@end ifinfo
@section Default Fatal Error Handler Operations
The default fatal error handler which is invoked by
the fatal_error_occurred directive when there is no user handler
configured or the user handler returns control to RTEMS. The
default fatal error handler disables processor interrupts (i.e.
sets the I bit in the PSW register to 0), places the error code
in r1, and executes a break instruction to simulate a halt
processor instruction.

222
doc/supplements/hppa1_1/intr.t
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@@ -1,222 +0,0 @@
@c
@c COPYRIGHT (c) 1988-1998.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c $Id$
@c
@ifinfo
@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top
@end ifinfo
@chapter Interrupt Processing
@ifinfo
@menu
* Interrupt Processing Introduction::
* Interrupt Processing Vectoring of Interrupt Handler::
* Interrupt Processing Interrupt Stack Frame::
* Interrupt Processing External Interrupts and Traps::
* Interrupt Processing Interrupt Levels::
* Interrupt Processing Disabling of Interrupts by RTEMS::
@end menu
@end ifinfo
@ifinfo
@node Interrupt Processing Introduction, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing, Interrupt Processing
@end ifinfo
@section Introduction
Different types of processors respond to the
occurence of an interrupt in their own unique fashion. In
addition, each processor type provides a control mechanism to
allow for the proper handling of an interrupt. The processor
dependent response to the interrupt modifies the current
execution state and results in a change in the execution stream.
Most processors require that an interrupt handler utilize some
special control mechanisms to return to the normal processing
stream. Although RTEMS hides many of the processor dependent
details of interrupt processing, it is important to understand
how the RTEMS interrupt manager is mapped onto the processor's
unique architecture. Discussed in this chapter are the PA-RISC's
interrupt response and control mechanisms as they pertain to
RTEMS.
@ifinfo
@node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Stack Frame, Interrupt Processing Introduction, Interrupt Processing
@end ifinfo
@section Vectoring of Interrupt Handler
Upon receipt of an interrupt the PA-RISC
automatically performs the following actions:
@itemize @bullet
@item The PSW (Program Status Word) is saved in the IPSW
(Interrupt Program Status Word).
@item The current privilege level is set to 0.
@item The following defined bits in the PSW are set:
@item E bit is set to the default endian bit
@item M bit is set to 1 if the interrupt is a high-priority
machine check and 0 otherwise
@item Q bit is set to zero thuse freezing the IIA
(Instruction Address) queues
@item C and D bits are set to zero thus disabling all
protection and translation.
@item I bit is set to zero this disabling all external,
powerfail, and low-priority machine check interrupts.
@item All others bits are set to zero.
@item General purpose registers r1, r8, r9, r16, r17, r24, and
r25 are copied to the shadow registers.
@item Execution begins at the address given by the formula:
Interruption Vector Address + (32 * interrupt vector number).
@end itemize
Once the processor has completed the actions it is is
required to perform for each interrupt, the RTEMS interrupt
management code (the beginning of which is stored in the
Interruption Vector Table) gains control and performs the
following actions upon each interrupt:
@itemize @bullet
@item returns the processor to "virtual mode" thus reenabling
all code and data address translation.
@item saves all necessary interrupt state information
@item saves all floating point registers
@item saves all integer registers
@item switches the current stack to the interrupt stack
@item dispatches to the appropriate user provided interrupt
service routine (ISR). If the ISR was installed with the
interrupt_catch directive, then it will be executed at this.
Because, the RTEMS interrupt handler saves all registers which
are not preserved according to the calling conventions and
invokes the application's ISR, the ISR can easily be written in
a high-level language.
@end itemize
RTEMS refers to the combination of the interrupt
state information and registers saved when vectoring an
interrupt as the Interrupt Stack Frame (ISF). A nested
interrupt is processed similarly by the PA-RISC and RTEMS with
the exception that the nested interrupt occurred while executing
on the interrupt stack and, thus, the current stack need not be
switched.
@ifinfo
@node Interrupt Processing Interrupt Stack Frame, Interrupt Processing External Interrupts and Traps, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
@end ifinfo
@section Interrupt Stack Frame
The PA-RISC architecture does not alter the stack
while processing interrupts. However, RTEMS does save
information on the stack as part of processing an interrupt.
This following shows the format of the Interrupt Stack Frame for
the PA-RISC as defined by RTEMS:
@example
@group
+------------------------+
| Interrupt Context | 0xXXX
+------------------------+
| Integer Context | 0xXXX
+------------------------+
| Floating Point Context | 0xXXX
+------------------------+
@end group
@end example
@ifinfo
@node Interrupt Processing External Interrupts and Traps, Interrupt Processing Interrupt Levels, Interrupt Processing Interrupt Stack Frame, Interrupt Processing
@end ifinfo
@section External Interrupts and Traps
In addition to the thirty-two unique interrupt
sources supported by the PA-RISC architecture, RTEMS also
supports the installation of handlers for each of the thirty-two
external interrupts supported by the PA-RISC architecture.
Except for interrupt vector 4, each of the interrupt vectors 0
through 31 may be associated with a user-provided interrupt
handler. Interrupt vector 4 is used for external interrupts.
When an external interrupt occurs, the RTEMS external interrupt
handler is invoked and the actual interrupt source is indicated
by status bits in the EIR (External Interrupt Request) register.
The RTEMS external interrupt handler (or interrupt vector four)
examines the EIR to determine which interrupt source requires
servicing.
RTEMS supports sixty-four interrupt vectors for the
PA-RISC. Vectors 0 through 31 map to the normal interrupt
sources while RTEMS interrupt vectors 32 through 63 are directly
associated with the external interrupt sources indicated by bits
0 through 31 in the EIR.
The exact set of interrupt sources which are checked
for by the RTEMS external interrupt handler and the order in
which they are checked are configured by the user in the CPU
Configuration Table. If an external interrupt occurs which does
not have a handler configured, then the spurious interrupt
handler will be invoked. The spurious interrupt handler may
also be specifiec by the user in the CPU Configuration Table.
@ifinfo
@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing External Interrupts and Traps, Interrupt Processing
@end ifinfo
@section Interrupt Levels
Two levels (enabled and disabled) of interrupt
priorities are supported by the PA-RISC architecture. Level
zero (0) indicates that interrupts are fully enabled (i.e. the I
bit of the PSW is 1). Level one (1) indicates that interrupts
are disabled (i.e. the I bit of the PSW is 0). Thirty-two
independent sources of external interrupts are supported by the
PA-RISC architecture. Each of these interrupts sources may be
individually enabled or disabled. When processor interrupts are
disabled, all sources of external interrupts are ignored. When
processor interrupts are enabled, the EIR (External Interrupt
Request) register is used to determine which sources are
currently allowed to generate interrupts.
Although RTEMS supports 256 interrupt levels, the
PA-RISC architecture only supports two. RTEMS interrupt level 0
indicates that interrupts are enabled and level 1 indicates that
interrupts are disabled. All other RTEMS interrupt levels are
undefined and their behavior is unpredictable.
@ifinfo
@node Interrupt Processing Disabling of Interrupts by RTEMS, Default Fatal Error Processing, Interrupt Processing Interrupt Levels, Interrupt Processing
@end ifinfo
@section Disabling of Interrupts by RTEMS
During the execution of directive calls, critical
sections of code may be executed. When these sections are
encountered, RTEMS disables external interrupts by setting the I
bit in the PSW to 0 before the execution of this section and
restores them to the previous level upon completion of the
section. RTEMS has been optimized to insure that interrupts are
disabled for less than XXX instructions when compiled with GNU
CC at optimization level 4. The exact execution time will vary
based on the based on the processor implementation, amount of
cache, the number of wait states for primary memory, and
processor speed present on the target board.
Non-maskable interrupts (NMI) such as high-priority
machine checks cannot be disabled, and ISRs which execute at
this level MUST NEVER issue RTEMS system calls. If a directive
is invoked, unpredictable results may occur due to the inability
of RTEMS to protect its critical sections. However, ISRs that
make no system calls may safely execute as non-maskable
interrupts.

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@@ -6,20 +6,8 @@
@c $Id$
@c
@ifinfo
@node Memory Model, Memory Model Introduction, Calling Conventions User-Provided Routines, Top
@end ifinfo
@chapter Memory Model
@ifinfo
@menu
* Memory Model Introduction::
* Memory Model Flat Memory Model::
@end menu
@end ifinfo
@ifinfo
@node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model
@end ifinfo
@section Introduction
A processor may support any combination of memory
@@ -31,9 +19,6 @@ memory of any kind. The appropriate memory model for RTEMS
provided by the targeted processor and related characteristics
of that model are described in this chapter.
@ifinfo
@node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model
@end ifinfo
@section Flat Memory Model
RTEMS supports applications in which the application

15
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@@ -6,20 +6,8 @@
@c $Id$
@c
@ifinfo
@node Memory Model, Memory Model Introduction, Calling Conventions User-Provided Routines, Top
@end ifinfo
@chapter Memory Model
@ifinfo
@menu
* Memory Model Introduction::
* Memory Model Flat Memory Model::
@end menu
@end ifinfo
@ifinfo
@node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model
@end ifinfo
@section Introduction
A processor may support any combination of memory
@@ -31,9 +19,6 @@ memory of any kind. The appropriate memory model for RTEMS
provided by the targeted processor and related characteristics
of that model are described in this chapter.
@ifinfo
@node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model
@end ifinfo
@section Flat Memory Model
RTEMS supports applications in which the application