forked from Imagelibrary/rtems
2009-02-27 Joel Sherrill <joel.sherrill@OARcorp.com>
* Makefile.am: Remove unnecessary copy of cpu_asm.S * console/Modif_cpu_asm.S: Removed.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,8 @@
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2009-02-27 Joel Sherrill <joel.sherrill@OARcorp.com>
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* Makefile.am: Remove unnecessary copy of cpu_asm.S
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* console/Modif_cpu_asm.S: Removed.
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2008-12-08 Ralf Corsépius <ralf.corsepius@rtems.org>
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* bsp_specs: Backport from CVS-HEAD.
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@@ -37,8 +37,8 @@ startup_SOURCES = startup/bspclean.c ../../shared/bsplibc.c \
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../../shared/sbrk.c ../../m68k/shared/setvec.c \
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startup/dumpanic.c ../../shared/gnatinstallhandler.c
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clock_SOURCES = clock/ckinit.c
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console_SOURCES = console/Modif_cpu_asm.S console/console.c \
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console/m340uart.c ../../shared/dummy_printk_support.c
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console_SOURCES = console/console.c console/m340uart.c \
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../../shared/dummy_printk_support.c
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timer_SOURCES = timer/timer.c
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noinst_LIBRARIES = libbsp.a
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@@ -1,178 +0,0 @@
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/* cpu_asm.s
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*
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* This file contains all assembly code for the MC68020 implementation
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* of RTEMS.
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*
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* ATTENTION: Modified for benchmarks
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#include <rtems/asm.h>
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.text
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/*PAGE
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* void _Debug_ISR_Handler_Console()
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*
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* This routine provides the RTEMS interrupt management.
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*
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* NOTE:
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* Upon entry, the master stack will contain an interrupt stack frame
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* back to the interrupted thread and the interrupt stack will contain
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* a throwaway interrupt stack frame. If dispatching is enabled, this
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* is the outer most interrupt, and (a context switch is necessary or
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* the current thread has signals), then set up the master stack to
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* transfer control to the interrupt dispatcher.
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* NOTE:
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* USED TO MESURE THE TIME SPENT IN THE INTERRUPT SUBROUTINE
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* CS5 - CS8 are linked to an oscilloscope so that you can mesure
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* RTEMS overhead (BTW it's very short :) )
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*/
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/*
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* With this approach, lower priority interrupts may
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* execute twice if a higher priority interrupt is
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* acknowledged before _Thread_Dispatch_disable is
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* increamented and the higher priority interrupt
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* preforms a context switch after executing. The lower
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* priority intterrupt will execute (1) at the end of the
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* higher priority interrupt in the new context if
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* permitted by the new interrupt level mask, and (2) when
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* the original context regains the cpu.
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*/
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#if ( M68K_HAS_VBR == 1)
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.set SR_OFFSET, 0 | Status register offset
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.set PC_OFFSET, 2 | Program Counter offset
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.set FVO_OFFSET, 6 | Format/vector offset
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#else
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.set SR_OFFSET, 2 | Status register offset
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.set PC_OFFSET, 4 | Program Counter offset
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.set FVO_OFFSET, 0 | Format/vector offset placed in the stack
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#endif /* M68K_HAS_VBR */
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.set SAVED, 16 | space for saved registers
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.align 4
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.global SYM (_Debug_ISR_Handler_Console)
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SYM (_Debug_ISR_Handler_Console):
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tst.w 0x14000000 | ALLUME CS5
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addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
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moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1
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movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
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andl #0x0fff,d0 | d0 = vector offset in vbr
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#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
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movew sr,d1 | Save status register
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oriw #0x700,sr | Disable interrupts
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tstl SYM (_ISR_Nest_level) | Interrupting an interrupt handler?
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bne 1f | Yes, just skip over stack switch code
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movel SYM(_CPU_Interrupt_stack_high),a0 | End of interrupt stack
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movel a7,a0@- | Save task stack pointer
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movel a0,a7 | Switch to interrupt stack
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1:
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addql #1,SYM(_ISR_Nest_level) | one nest level deeper
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movew d1,sr | Restore status register
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#else
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addql #1,SYM (_ISR_Nest_level) | one nest level deeper
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#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
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#if ( M68K_HAS_PREINDEXING == 1 )
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movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
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#else
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movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table
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addal d0,a0 | a0 = address of vector
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movel (a0),a0 | a0 = address of user routine
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#endif
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lsrl #2,d0 | d0 = vector number
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movel d0,a7@- | push vector number
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tst.w 0x18000000 | ALLUME CS6
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jbsr a0@ | invoke the user ISR
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tst.w 0x18000000 | ALLUME CS6
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addql #4,a7 | remove vector number
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#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
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movew sr,d0 | Save status register
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oriw #0x700,sr | Disable interrupts
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subql #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count
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bne 1f | Skip if return to interrupt
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movel (a7),a7 | Restore task stack pointer
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1:
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movew d0,sr | Restore status register
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#else
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subql #1,SYM (_ISR_Nest_level) | one less nest level
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#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
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subql #1,SYM (_Thread_Dispatch_disable_level)
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| unnest multitasking
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bne Debug_exit | If dispatch disabled, Debug_exit
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#if ( M68K_HAS_SEPARATE_STACKS == 1 )
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movew #0xf000,d0 | isolate format nibble
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andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO
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cmpiw #0x1000,d0 | is it a throwaway isf?
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bne Debug_exit | NOT outer level, so branch
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#endif
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tstl SYM (_Context_Switch_necessary)
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| Is thread switch necessary?
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bne bframe | Yes, invoke dispatcher
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tstl SYM (_ISR_Signals_to_thread_executing)
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| signals sent to Run_thread
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| while in interrupt handler?
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beq Debug_exit | No, then Debug_exit
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bframe: clrl SYM (_ISR_Signals_to_thread_executing)
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| If sent, will be processed
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#if ( M68K_HAS_SEPARATE_STACKS == 1 )
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movec msp,a0 | a0 = master stack pointer
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movew #0,a0@- | push format word
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movel # SYM (_ISR_Dispatch),a0@- | push return addr
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| filter out the trace bit to stop single step debugging breaking
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movew a0@(6+SR_OFFSET),d0
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andw #0x7FFF,d0
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movew d0,a0@- | push thread sr
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movec a0,msp | set master stack pointer
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#else
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| filter out the trace bit to stop single step debugging breaking
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movew a7@(16+SR_OFFSET),d0
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andw #0x7FFF,d0
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movew d0,sr
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jsr SYM (_Thread_Dispatch)
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#endif
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Debug_exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1
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#if ( M68K_HAS_VBR == 0 )
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addql #2,a7 | pop format/id
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#endif /* M68K_HAS_VBR */
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tst.w 0x1C000000 | ALLUME CS7
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rte | return to thread
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| OR _Isr_dispatch
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