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2005-11-03 <strauman@slac.stanford.edu>

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* shared/console/reboot.c, shared/start/start.S: Fixed PR#845;
    !!enable MMU!! on mvme2100 - this is very important.
    Otherwise, all accesses are write-back cached [incl. memory-mapped devices].
    (Prerequisite were the changes to shared/startup/bspstart.c just
    below.) Implemented rtemsReboot() for mvme2100.
This commit is contained in:
Till Straumann
2005-11-04 03:20:29 +00:00
parent 8c9fffdd38
commit dc0f6585f5
2 changed files with 3 additions and 14 deletions
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3
c/src/lib/libbsp/powerpc/shared/console/reboot.c
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@@ -19,4 +19,7 @@ void rtemsReboot(void)
#if defined(BSP_KBD_IOBASE)
kbd_outb(0x4, 0xFE); /* use keyboard controler to do the job... */
#endif
#if defined(mvme2100)
*(unsigned char*)0xffe00000 |= 0x80;
#endif
} /* rtemsReboot */

14
c/src/lib/libbsp/powerpc/shared/start/start.S
View File

@@ -74,20 +74,10 @@ __rtems_entry_point:
ori r11,r11,0x1ffe
li r8,2 /* R/W access */
isync
#if defined(mvme2100)
/* BSP_vme_config() wants to use BAT0, this board will use the
* available BAT1 to map RAM.
*/
mtspr DBAT1L,r8 /* N.B. 6xx (not 601) have valid */
mtspr DBAT1U,r11 /* bit in upper BAT register */
mtspr IBAT1L,r8
mtspr IBAT1U,r11
#else
mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
mtspr DBAT0U,r11 /* bit in upper BAT register */
mtspr IBAT0L,r8
mtspr IBAT0U,r11
#endif
isync
/*
@@ -134,10 +124,6 @@ enter_C_code:
MMUon:
mfmsr r0
ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
#if defined(mvme2100)
/* Data addr translation is broken for the mvme2100, disable it here */
xori r0,r0, MSR_DR
#endif
#if (PPC_HAS_FPU == 0)
xori r0, r0, MSR_EE | MSR_IP | MSR_FP
#else