forked from Imagelibrary/rtems
bsps/arm: Add SMP support
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@@ -842,6 +842,63 @@ static inline void arm_cp15_wait_for_interrupt(void)
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);
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}
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static inline uint32_t arm_cp15_get_multiprocessor_affinity(void)
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{
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ARM_SWITCH_REGISTERS;
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uint32_t mpidr;
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__asm__ volatile (
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ARM_SWITCH_TO_ARM
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"mrc p15, 0, %[mpidr], c0, c0, 5\n"
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ARM_SWITCH_BACK
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: [mpidr] "=&r" (mpidr) ARM_SWITCH_ADDITIONAL_OUTPUT
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);
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return mpidr & 0xff;
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}
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static inline uint32_t arm_cortex_a9_get_multiprocessor_cpu_id(void)
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{
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return arm_cp15_get_multiprocessor_affinity() & 0xff;
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}
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#define ARM_CORTEX_A9_ACTL_FW (1U << 0)
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#define ARM_CORTEX_A9_ACTL_L2_PREFETCH_HINT_ENABLE (1U << 1)
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#define ARM_CORTEX_A9_ACTL_L1_PREFETCH_ENABLE (1U << 2)
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#define ARM_CORTEX_A9_ACTL_WRITE_FULL_LINE_OF_ZEROS_MODE (1U << 3)
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#define ARM_CORTEX_A9_ACTL_SMP (1U << 6)
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#define ARM_CORTEX_A9_ACTL_EXCL (1U << 7)
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#define ARM_CORTEX_A9_ACTL_ALLOC_IN_ONE_WAY (1U << 8)
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#define ARM_CORTEX_A9_ACTL_PARITY_ON (1U << 9)
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static inline uint32_t arm_cp15_get_auxiliary_control(void)
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{
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ARM_SWITCH_REGISTERS;
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uint32_t val;
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__asm__ volatile (
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ARM_SWITCH_TO_ARM
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"mrc p15, 0, %[val], c1, c0, 1\n"
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ARM_SWITCH_BACK
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: [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
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);
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return val;
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}
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static inline void arm_cp15_set_auxiliary_control(uint32_t val)
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{
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ARM_SWITCH_REGISTERS;
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__asm__ volatile (
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ARM_SWITCH_TO_ARM
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"mcr p15, 0, %[val], c1, c0, 1\n"
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ARM_SWITCH_BACK
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: ARM_SWITCH_OUTPUT
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: [val] "r" (val)
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);
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}
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/**
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* @brief Sets the @a section_flags for the address range [@a begin, @a end).
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*
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