RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

bsp/arm: Cleanup L2 cache handling

Browse Source
This commit is contained in:
Ralf Kirchner
2014-04-17 11:27:23 +02:00
committed by Sebastian Huber
parent 127634c358
commit d98eea06dc
1 changed files with 7 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
View File

@@ -513,8 +513,6 @@ static bool l2c_310_cache_errata_is_applicable_753970(
return is_applicable;
}
static bool l2c_310_cache_errata_is_applicable_727913(
void
)
@@ -973,31 +971,6 @@ static void l2c_310_cache_check_errata( void )
* corruption */
assert( ! l2c_310_cache_errata_is_applicable_752271() );
/* This erratum gets handled with a workaround: 753970 The Cache Sync
* operation prevents further bufferable writes from merging in the store.
Search for 753970 in cache_.h for detailed information */
/* Conditions
This problem occurs when the following conditions are met:
1. PL310 receives a Cache Sync operation.
Workaround
The proposed workaround to avoid this erratum is to replace the normal
offset of Cache Sync operation (0x730) by another offset targeting an
unmapped PL310 register: 0x740.
More specifically, find below a pseudo code sequence illustrating the
workaround:
Replace
// PL310 Cache Sync operation
LDR r1,=PL310_BASE
STR r2,[r1,#0x730]
by
// Workaround for PL310 Cache Sync operation
LDR r1,=PL310_BASE
STR r2,[r1,#0x740] ; write to an unmapped register
This write has the same effect as the Cache Sync operation: store buffer
drained and waiting for all buffers empty.*/
/* assert( ! l2c_310_cache_errata_is_applicable_753970() ); */
/* This erratum can not be worked around: 754670 A continuous write flow can
* stall a read targeting the same memory area
* But this erratum does not lead to any data corruption */
@@ -1112,10 +1085,7 @@ cache_l2c_310_flush_entire( void )
rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;
while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {
}
;
while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {};
/* Wait for the flush to complete */
cache_l2c_310_sync();
@@ -1131,7 +1101,6 @@ cache_l2c_310_invalidate_1_line( const void *d_addr )
l2cc->inv_pa = (uint32_t) d_addr;
cache_l2c_310_sync();
}