forked from Imagelibrary/rtems
powerpc: Add support for VRSAVE
The VRSAVE feature of the Altivec unit can be used to reduce the amount of Altivec registers which need to be saved/restored during interrupt processing and context switches. In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is required, see GCC configuration. The -mvrsave option must be added to the ABI_FLAGS of the BSP. Currently only the -mcpu=e6500 based QorIQ BSP support this optimization. Update #4712.
This commit is contained in:
Sebastian Huber
@@ -23,7 +23,7 @@
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* COPYRIGHT (c) 1989-1997.
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* On-Line Applications Research Corporation (OAR).
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*
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* Copyright (c) 2011, 2017 embedded brains GmbH
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* Copyright (c) 2011, 2020 embedded brains GmbH
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*
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* The license and distribution terms for this file may in
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* the file LICENSE in this distribution or at
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@@ -267,6 +267,10 @@ PROC (_CPU_Context_switch_no_return):
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isync
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#endif
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#if defined(PPC_MULTILIB_ALTIVEC) && defined(__PPC_VRSAVE__)
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mfvrsave r9
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#endif
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/* Align to a cache line */
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CLEAR_RIGHT_IMMEDIATE r3, r3, PPC_DEFAULT_CACHE_LINE_POWER
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CLEAR_RIGHT_IMMEDIATE r5, r4, PPC_DEFAULT_CACHE_LINE_POWER
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@@ -284,6 +288,14 @@ PROC (_CPU_Context_switch_no_return):
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mfmsr r6
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#endif /* END PPC_DISABLE_MSR_ACCESS */
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mfcr r7
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#ifdef PPC_MULTILIB_ALTIVEC
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#ifdef __PPC_VRSAVE__
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/* Mark v0 as used since we need it to get the VSCR */
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oris r8, r9, 0x8000
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mtvrsave r8
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#endif
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mfvscr v0
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#endif
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mflr r8
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lwz r11, PER_CPU_ISR_DISPATCH_DISABLE(r12)
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@@ -356,6 +368,16 @@ PROC (_CPU_Context_switch_no_return):
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stw r11, PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r3)
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#ifdef PPC_MULTILIB_ALTIVEC
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li r10, PPC_CONTEXT_OFFSET_VSCR
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stvewx v0, r3, r10
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#ifdef __PPC_VRSAVE__
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stw r9, PPC_CONTEXT_OFFSET_VRSAVE(r3)
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andi. r9, r9, 0xfff
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bne .Laltivec_save
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.Laltivec_save_continue:
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#else /* __PPC_VRSAVE__ */
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li r9, PPC_CONTEXT_OFFSET_V20
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stvx v20, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V21
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@@ -397,7 +419,8 @@ PROC (_CPU_Context_switch_no_return):
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stvx v31, r3, r9
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mfvrsave r9
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stw r9, PPC_CONTEXT_OFFSET_VRSAVE(r3)
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#endif
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#endif /* __PPC_VRSAVE__ */
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#endif /* PPC_MULTILIB_ALTIVEC */
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#ifdef PPC_MULTILIB_FPU
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stfd f14, PPC_CONTEXT_OFFSET_F14(r3)
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@@ -461,6 +484,14 @@ restore_context:
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PPC_REG_LOAD r1, PPC_CONTEXT_OFFSET_GPR1(r5)
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PPC_REG_LOAD r8, PPC_CONTEXT_OFFSET_LR(r5)
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#ifdef PPC_MULTILIB_ALTIVEC
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li r10, PPC_CONTEXT_OFFSET_VSCR
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lvewx v0, r5, r10
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#ifdef __PPC_VRSAVE__
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lwz r9, PPC_CONTEXT_OFFSET_VRSAVE(r5)
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#endif
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#endif
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PPC_GPR_LOAD r14, PPC_CONTEXT_OFFSET_GPR14(r5)
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PPC_GPR_LOAD r15, PPC_CONTEXT_OFFSET_GPR15(r5)
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@@ -494,6 +525,15 @@ restore_context:
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lwz r11, PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r5)
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#ifdef PPC_MULTILIB_ALTIVEC
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mtvscr v0
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#ifdef __PPC_VRSAVE__
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mtvrsave r9
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andi. r9, r9, 0xfff
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bne .Laltivec_restore
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.Laltivec_restore_continue:
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#else /* __PPC_VRSAVE__ */
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li r9, PPC_CONTEXT_OFFSET_V20
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lvx v20, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V21
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@@ -520,7 +560,8 @@ restore_context:
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lvx v31, r5, r9
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lwz r9, PPC_CONTEXT_OFFSET_VRSAVE(r5)
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mtvrsave r9
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#endif
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#endif /* __PPC_VRSAVE__ */
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#endif /* PPC_MULTILIB_ALTIVEC */
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#ifdef PPC_MULTILIB_FPU
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lfd f14, PPC_CONTEXT_OFFSET_F14(r5)
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@@ -567,6 +608,13 @@ PROC (_CPU_Context_restore):
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li r3, 0
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#endif
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#if defined(PPC_MULTILIB_ALTIVEC) && defined(__PPC_VRSAVE__)
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/* Mark v0 as used since we need it to get the VSCR */
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mfvrsave r9
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oris r8, r9, 0x8000
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mtvrsave r8
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#endif
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b restore_context
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#ifdef RTEMS_SMP
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@@ -595,3 +643,105 @@ PROC (_CPU_Context_restore):
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b .Lcheck_is_executing
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#endif
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#if defined(PPC_MULTILIB_ALTIVEC) && defined(__PPC_VRSAVE__)
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.Laltivec_save:
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/*
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* Let X be VRSAVE, calculate:
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*
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* Z = X & 0x777
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* Z = Z + 0x777
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* X = X | Z
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*
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* Afterwards, we have in X for each group of four non-volatile VR
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* registers:
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*
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* 0111b, if VRSAVE group of four registers == 0
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* 1XXXb, if VRSAVE group of four registers != 0
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*/
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andi. r10, r9, 0x777
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addi r10, r10, 0x777
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or r9, r9, r10
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mtcr r9
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bf 20, .Laltivec_save_v24
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li r9, PPC_CONTEXT_OFFSET_V20
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stvx v20, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V21
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stvx v21, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V22
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stvx v22, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V23
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stvx v23, r3, r9
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.Laltivec_save_v24:
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bf 24, .Laltivec_save_v28
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li r9, PPC_CONTEXT_OFFSET_V24
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stvx v24, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V25
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stvx v25, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V26
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stvx v26, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V27
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stvx v27, r3, r9
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.Laltivec_save_v28:
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bf 28, .Laltivec_save_continue
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li r9, PPC_CONTEXT_OFFSET_V28
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stvx v28, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V29
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stvx v29, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V30
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stvx v30, r3, r9
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li r9, PPC_CONTEXT_OFFSET_V31
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stvx v31, r3, r9
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b .Laltivec_save_continue
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.Laltivec_restore:
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/* See comment at .Laltivec_save */
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andi. r10, r9, 0x777
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addi r10, r10, 0x777
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or r9, r9, r10
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mtcr r9
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bf 20, .Laltivec_restore_v24
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li r9, PPC_CONTEXT_OFFSET_V20
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lvx v20, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V21
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lvx v21, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V22
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lvx v22, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V23
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lvx v23, r5, r9
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.Laltivec_restore_v24:
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bf 24, .Laltivec_restore_v28
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li r9, PPC_CONTEXT_OFFSET_V24
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lvx v24, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V25
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lvx v25, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V26
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lvx v26, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V27
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lvx v27, r5, r9
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.Laltivec_restore_v28:
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bf 28, .Laltivec_restore_continue
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li r9, PPC_CONTEXT_OFFSET_V28
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lvx v28, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V29
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lvx v29, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V30
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lvx v30, r5, r9
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li r9, PPC_CONTEXT_OFFSET_V31
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lvx v31, r5, r9
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b .Laltivec_restore_continue
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#endif /* PPC_MULTILIB_ALTIVEC && __PPC_VRSAVE__ */
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