forked from Imagelibrary/rtems
This commit was manufactured by cvs2svn to create branch 'rtems-4-6-branch'.
Sprout from master 2003-02-11 23:44:41 UTC Joel Sherrill <joel.sherrill@OARcorp.com> '2003-02-11 Joel Sherrill <joel@OARcorp.com>' Cherrypick from rtemsdoc-4-5-branch 1997-05-27 12:40:10 UTC Joel Sherrill <joel.sherrill@OARcorp.com> 'base RTEMS documentation': doc/common/treedef.tex Delete: bootstrap c/src/ada/.cvsignore c/src/ada/ChangeLog c/src/ada/Makefile.am c/src/ada/rtems-multiprocessing.adb c/src/ada/rtems-multiprocessing.ads c/src/ada/rtems.adb c/src/ada/rtems.ads c/src/lib/libcpu/powerpc/new-exceptions/ChangeLog c/src/lib/libcpu/powerpc/new-exceptions/cpu.c c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S c/src/lib/libcpu/powerpc/old-exceptions/ChangeLog c/src/lib/libcpu/powerpc/old-exceptions/README c/src/lib/libcpu/powerpc/old-exceptions/TODO c/src/lib/libcpu/powerpc/old-exceptions/cpu.c c/src/lib/libcpu/powerpc/old-exceptions/cpu_asm.S c/src/lib/libcpu/powerpc/old-exceptions/irq_stub.S c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c c/src/lib/libcpu/powerpc/old-exceptions/rtems/score/ppc_offs.h c/src/libchip/shmdr/.cvsignore c/src/libchip/shmdr/README c/src/libchip/shmdr/addlq.c c/src/libchip/shmdr/cnvpkt.c c/src/libchip/shmdr/dump.c c/src/libchip/shmdr/fatal.c c/src/libchip/shmdr/getlq.c c/src/libchip/shmdr/getpkt.c c/src/libchip/shmdr/init.c c/src/libchip/shmdr/initlq.c c/src/libchip/shmdr/intr.c c/src/libchip/shmdr/mpci.h c/src/libchip/shmdr/mpisr.c c/src/libchip/shmdr/poll.c c/src/libchip/shmdr/receive.c c/src/libchip/shmdr/retpkt.c c/src/libchip/shmdr/send.c c/src/libchip/shmdr/setckvec.c c/src/libchip/shmdr/shm_driver.h cpukit/ftpd/Makefile.am cpukit/ftpd/ftpd.c cpukit/ftpd/ftpd.h cpukit/httpd/.cvsignore cpukit/httpd/Makefile.am cpukit/httpd/NOTES cpukit/httpd/asp.c cpukit/httpd/balloc.c cpukit/httpd/default.c cpukit/httpd/ej.h cpukit/httpd/ejIntrn.h cpukit/httpd/ejlex.c cpukit/httpd/ejparse.c cpukit/httpd/emfdb.c cpukit/httpd/emfdb.h cpukit/httpd/form.c cpukit/httpd/h.c cpukit/httpd/handler.c cpukit/httpd/license.txt cpukit/httpd/md5.h cpukit/httpd/md5c.c cpukit/httpd/mime.c cpukit/httpd/misc.c cpukit/httpd/ringq.c cpukit/httpd/rom.c cpukit/httpd/rtems_webserver.h cpukit/httpd/security.c cpukit/httpd/sock.c cpukit/httpd/socket.c cpukit/httpd/sym.c cpukit/httpd/uemf.c cpukit/httpd/uemf.h cpukit/httpd/um.c cpukit/httpd/um.h cpukit/httpd/url.c cpukit/httpd/value.c cpukit/httpd/wbase64.c cpukit/httpd/webcomp.c cpukit/httpd/webmain.c cpukit/httpd/webpage.c cpukit/httpd/webrom.c cpukit/httpd/webs.c cpukit/httpd/webs.h cpukit/httpd/websuemf.c cpukit/httpd/wsIntrn.h cpukit/libnetworking/netinet/in_cksum_arm.h cpukit/libnetworking/netinet/in_cksum_i386.h cpukit/libnetworking/netinet/in_cksum_m68k.h cpukit/libnetworking/netinet/in_cksum_powerpc.h cpukit/pppd/Makefile.am cpukit/pppd/README cpukit/pppd/STATUS cpukit/pppd/auth.c cpukit/pppd/cbcp.c cpukit/pppd/cbcp.h cpukit/pppd/ccp.c cpukit/pppd/ccp.h cpukit/pppd/chap.c cpukit/pppd/chap.h cpukit/pppd/chap_ms.c cpukit/pppd/chap_ms.h cpukit/pppd/chat.c cpukit/pppd/demand.c cpukit/pppd/example/Makefile-user cpukit/pppd/example/README cpukit/pppd/example/init.c cpukit/pppd/example/netconfig.h cpukit/pppd/example/ppp.conf cpukit/pppd/example/pppd.options cpukit/pppd/example/pppdapp.c cpukit/pppd/example/system.h cpukit/pppd/fsm.c cpukit/pppd/fsm.h cpukit/pppd/ipcp.c cpukit/pppd/ipcp.h cpukit/pppd/ipxcp.c cpukit/pppd/ipxcp.h cpukit/pppd/lcp.c cpukit/pppd/lcp.h cpukit/pppd/magic.c cpukit/pppd/magic.h cpukit/pppd/md4.c cpukit/pppd/md4.h cpukit/pppd/md5.c cpukit/pppd/md5.h cpukit/pppd/options.c cpukit/pppd/patchlevel.h cpukit/pppd/pathnames.h cpukit/pppd/pppd.8 cpukit/pppd/pppd.h cpukit/pppd/rtemsdialer.h cpukit/pppd/rtemsmain.c cpukit/pppd/rtemspppd.c cpukit/pppd/rtemspppd.h cpukit/pppd/sys-rtems.c cpukit/pppd/upap.c cpukit/pppd/upap.h cpukit/pppd/utils.c cpukit/rtems/src/clocktodtoseconds.c cpukit/rtems/src/clocktodvalidate.c cpukit/score/cpu/arm/rtems/asm.h cpukit/score/cpu/c4x/rtems/asm.h cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h cpukit/score/cpu/h8300/rtems/asm.h cpukit/score/cpu/i386/rtems/asm.h cpukit/score/cpu/m68k/rtems/asm.h cpukit/score/cpu/m68k/rtems/m68k/m68302.h cpukit/score/cpu/m68k/rtems/m68k/m68360.h cpukit/score/cpu/m68k/rtems/m68k/qsm.h cpukit/score/cpu/m68k/rtems/m68k/sim.h cpukit/score/cpu/mips/rtems/asm.h cpukit/score/cpu/mips/rtems/mips/idtcpu.h cpukit/score/cpu/mips/rtems/mips/iregdef.h cpukit/score/cpu/no_cpu/rtems/asm.h cpukit/score/cpu/or32/rtems/asm.h cpukit/score/cpu/powerpc/rtems/asm.h cpukit/score/cpu/sh/rtems/asm.h cpukit/score/cpu/sparc/rtems/asm.h cpukit/telnetd/Makefile.am cpukit/telnetd/README cpukit/telnetd/icmds.c cpukit/telnetd/pty.c cpukit/telnetd/pty.h cpukit/telnetd/telnetd.c cpukit/telnetd/telnetd.h cpukit/zlib/doc/rfc1950.txt cpukit/zlib/doc/rfc1951.txt cpukit/zlib/doc/rfc1952.txt testsuites/.cvsignore testsuites/ChangeLog testsuites/Makefile.am testsuites/PROBLEMS testsuites/README testsuites/configure.ac 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testsuites/sptests/sp14/asr.c testsuites/sptests/sp14/init.c testsuites/sptests/sp14/sp14.doc testsuites/sptests/sp14/sp14.scn testsuites/sptests/sp14/system.h testsuites/sptests/sp14/task1.c testsuites/sptests/sp14/task2.c testsuites/sptests/sp15/.cvsignore testsuites/sptests/sp15/Makefile.am testsuites/sptests/sp15/init.c testsuites/sptests/sp15/sp15.doc testsuites/sptests/sp15/sp15.scn testsuites/sptests/sp15/system.h testsuites/sptests/sp15/task1.c testsuites/sptests/sp16/.cvsignore testsuites/sptests/sp16/Makefile.am testsuites/sptests/sp16/init.c testsuites/sptests/sp16/sp16.doc testsuites/sptests/sp16/sp16.scn testsuites/sptests/sp16/system.h testsuites/sptests/sp16/task1.c testsuites/sptests/sp16/task2.c testsuites/sptests/sp16/task3.c testsuites/sptests/sp16/task4.c testsuites/sptests/sp16/task5.c testsuites/sptests/sp17/.cvsignore testsuites/sptests/sp17/Makefile.am testsuites/sptests/sp17/asr.c testsuites/sptests/sp17/init.c testsuites/sptests/sp17/sp17.doc testsuites/sptests/sp17/sp17.scn testsuites/sptests/sp17/system.h testsuites/sptests/sp17/task1.c testsuites/sptests/sp17/task2.c testsuites/sptests/sp19/.cvsignore testsuites/sptests/sp19/Makefile.am testsuites/sptests/sp19/first.c testsuites/sptests/sp19/fptask.c testsuites/sptests/sp19/fptest.h testsuites/sptests/sp19/init.c testsuites/sptests/sp19/inttest.h testsuites/sptests/sp19/sp19.doc testsuites/sptests/sp19/sp19.scn testsuites/sptests/sp19/system.h testsuites/sptests/sp19/task1.c testsuites/sptests/sp20/.cvsignore testsuites/sptests/sp20/Makefile.am testsuites/sptests/sp20/getall.c testsuites/sptests/sp20/init.c testsuites/sptests/sp20/sp20.doc testsuites/sptests/sp20/sp20.scn testsuites/sptests/sp20/system.h testsuites/sptests/sp20/task1.c testsuites/sptests/sp21/.cvsignore testsuites/sptests/sp21/Makefile.am testsuites/sptests/sp21/init.c testsuites/sptests/sp21/sp21.doc testsuites/sptests/sp21/sp21.scn testsuites/sptests/sp21/system.h testsuites/sptests/sp21/task1.c testsuites/sptests/sp22/.cvsignore testsuites/sptests/sp22/Makefile.am testsuites/sptests/sp22/delay.c testsuites/sptests/sp22/init.c testsuites/sptests/sp22/prtime.c testsuites/sptests/sp22/sp22.doc testsuites/sptests/sp22/sp22.scn testsuites/sptests/sp22/system.h testsuites/sptests/sp22/task1.c testsuites/sptests/sp23/.cvsignore testsuites/sptests/sp23/Makefile.am testsuites/sptests/sp23/init.c testsuites/sptests/sp23/sp23.doc testsuites/sptests/sp23/sp23.scn testsuites/sptests/sp23/system.h testsuites/sptests/sp23/task1.c testsuites/sptests/sp24/.cvsignore testsuites/sptests/sp24/Makefile.am testsuites/sptests/sp24/init.c testsuites/sptests/sp24/resume.c testsuites/sptests/sp24/sp24.doc testsuites/sptests/sp24/sp24.scn testsuites/sptests/sp24/system.h testsuites/sptests/sp24/task1.c testsuites/sptests/sp25/.cvsignore testsuites/sptests/sp25/Makefile.am testsuites/sptests/sp25/init.c testsuites/sptests/sp25/sp25.doc testsuites/sptests/sp25/sp25.scn testsuites/sptests/sp25/system.h testsuites/sptests/sp25/task1.c testsuites/sptests/sp26/.cvsignore testsuites/sptests/sp26/Makefile.am testsuites/sptests/sp26/init.c testsuites/sptests/sp26/sp26.doc testsuites/sptests/sp26/sp26.scn testsuites/sptests/sp26/system.h testsuites/sptests/sp26/task1.c testsuites/sptests/sp27/.cvsignore testsuites/sptests/sp27/Makefile.am testsuites/sptests/sp27/init.c testsuites/sptests/sp27/sp27.doc testsuites/sptests/sp27/sp27.scn testsuites/sptests/sp28/.cvsignore testsuites/sptests/sp28/Makefile.am testsuites/sptests/sp28/init.c testsuites/sptests/sp28/sp28.doc testsuites/sptests/sp28/sp28.scn testsuites/sptests/sp29/.cvsignore testsuites/sptests/sp29/Makefile.am testsuites/sptests/sp29/init.c testsuites/sptests/sp29/sp29.doc testsuites/sptests/sp29/sp29.scn testsuites/sptests/sp30/.cvsignore testsuites/sptests/sp30/Makefile.am testsuites/sptests/sp30/init.c testsuites/sptests/sp30/resume.c testsuites/sptests/sp30/sp30.doc testsuites/sptests/sp30/sp30.scn testsuites/sptests/sp30/system.h testsuites/sptests/sp30/task1.c testsuites/sptests/sp31/.cvsignore testsuites/sptests/sp31/Makefile.am testsuites/sptests/sp31/delay.c testsuites/sptests/sp31/init.c testsuites/sptests/sp31/prtime.c testsuites/sptests/sp31/sp31.doc testsuites/sptests/sp31/sp31.scn testsuites/sptests/sp31/system.h testsuites/sptests/sp31/task1.c testsuites/sptests/sp32/.cvsignore testsuites/sptests/sp32/Makefile.am testsuites/sptests/sp32/init.c testsuites/sptests/sp32/sp32.scn testsuites/sptests/spfatal/.cvsignore testsuites/sptests/spfatal/Makefile.am testsuites/sptests/spfatal/README testsuites/sptests/spfatal/fatal.c testsuites/sptests/spfatal/init.c testsuites/sptests/spfatal/puterr.c testsuites/sptests/spfatal/spfatal.doc testsuites/sptests/spfatal/spfatal.scn testsuites/sptests/spfatal/system.h testsuites/sptests/spfatal/task1.c testsuites/sptests/spsize/.cvsignore testsuites/sptests/spsize/Makefile.am testsuites/sptests/spsize/getint.c testsuites/sptests/spsize/init.c testsuites/sptests/spsize/size.c testsuites/sptests/spsize/size.scn testsuites/sptests/spsize/system.h testsuites/sptests/sptests.am testsuites/support/.cvsignore testsuites/support/ChangeLog testsuites/support/Makefile.am testsuites/support/configure.ac testsuites/support/include/.cvsignore testsuites/support/include/buffer_test_io.h testsuites/support/include/tmacros.h testsuites/tmitrontests/.cvsignore testsuites/tmitrontests/ChangeLog testsuites/tmitrontests/Makefile.am testsuites/tmitrontests/README testsuites/tmitrontests/configure.ac testsuites/tmitrontests/include/.cvsignore testsuites/tmitrontests/include/Makefile.am testsuites/tmitrontests/include/timesys.h testsuites/tmitrontests/tmitronsem01/.cvsignore testsuites/tmitrontests/tmitronsem01/Makefile.am testsuites/tmitrontests/tmitronsem01/init.c testsuites/tmitrontests/tmitronsem01/system.h testsuites/tmitrontests/tmitronsem01/tmitronsem01.doc testsuites/tmitrontests/tmitrontests.am testsuites/tmtests/.cvsignore testsuites/tmtests/ChangeLog testsuites/tmtests/Makefile.am testsuites/tmtests/README testsuites/tmtests/configure.ac testsuites/tmtests/include/.cvsignore testsuites/tmtests/include/Makefile.am testsuites/tmtests/include/timesys.h testsuites/tmtests/tm01/.cvsignore testsuites/tmtests/tm01/Makefile.am testsuites/tmtests/tm01/system.h testsuites/tmtests/tm01/task1.c testsuites/tmtests/tm01/tm01.doc testsuites/tmtests/tm02/.cvsignore testsuites/tmtests/tm02/Makefile.am testsuites/tmtests/tm02/system.h testsuites/tmtests/tm02/task1.c testsuites/tmtests/tm02/tm02.doc testsuites/tmtests/tm03/.cvsignore testsuites/tmtests/tm03/Makefile.am testsuites/tmtests/tm03/system.h testsuites/tmtests/tm03/task1.c testsuites/tmtests/tm03/tm03.doc testsuites/tmtests/tm04/.cvsignore testsuites/tmtests/tm04/Makefile.am testsuites/tmtests/tm04/system.h testsuites/tmtests/tm04/task1.c testsuites/tmtests/tm04/tm04.doc testsuites/tmtests/tm05/.cvsignore testsuites/tmtests/tm05/Makefile.am testsuites/tmtests/tm05/system.h testsuites/tmtests/tm05/task1.c testsuites/tmtests/tm05/tm05.doc testsuites/tmtests/tm06/.cvsignore testsuites/tmtests/tm06/Makefile.am testsuites/tmtests/tm06/system.h testsuites/tmtests/tm06/task1.c testsuites/tmtests/tm06/tm06.doc testsuites/tmtests/tm07/.cvsignore testsuites/tmtests/tm07/Makefile.am testsuites/tmtests/tm07/system.h testsuites/tmtests/tm07/task1.c testsuites/tmtests/tm07/tm07.doc testsuites/tmtests/tm08/.cvsignore testsuites/tmtests/tm08/Makefile.am testsuites/tmtests/tm08/system.h testsuites/tmtests/tm08/task1.c testsuites/tmtests/tm08/tm08.doc testsuites/tmtests/tm09/.cvsignore testsuites/tmtests/tm09/Makefile.am testsuites/tmtests/tm09/system.h testsuites/tmtests/tm09/task1.c testsuites/tmtests/tm09/tm09.doc testsuites/tmtests/tm10/.cvsignore testsuites/tmtests/tm10/Makefile.am testsuites/tmtests/tm10/system.h testsuites/tmtests/tm10/task1.c testsuites/tmtests/tm10/tm10.doc testsuites/tmtests/tm11/.cvsignore testsuites/tmtests/tm11/Makefile.am testsuites/tmtests/tm11/system.h testsuites/tmtests/tm11/task1.c testsuites/tmtests/tm11/tm11.doc testsuites/tmtests/tm12/.cvsignore testsuites/tmtests/tm12/Makefile.am testsuites/tmtests/tm12/system.h testsuites/tmtests/tm12/task1.c testsuites/tmtests/tm12/tm12.doc testsuites/tmtests/tm13/.cvsignore testsuites/tmtests/tm13/Makefile.am testsuites/tmtests/tm13/system.h testsuites/tmtests/tm13/task1.c testsuites/tmtests/tm13/tm13.doc testsuites/tmtests/tm14/.cvsignore testsuites/tmtests/tm14/Makefile.am testsuites/tmtests/tm14/system.h testsuites/tmtests/tm14/task1.c testsuites/tmtests/tm14/tm14.doc testsuites/tmtests/tm15/.cvsignore testsuites/tmtests/tm15/Makefile.am testsuites/tmtests/tm15/system.h testsuites/tmtests/tm15/task1.c testsuites/tmtests/tm15/tm15.doc testsuites/tmtests/tm16/.cvsignore testsuites/tmtests/tm16/Makefile.am testsuites/tmtests/tm16/system.h testsuites/tmtests/tm16/task1.c testsuites/tmtests/tm16/tm16.doc testsuites/tmtests/tm17/.cvsignore testsuites/tmtests/tm17/Makefile.am testsuites/tmtests/tm17/system.h testsuites/tmtests/tm17/task1.c testsuites/tmtests/tm17/tm17.doc testsuites/tmtests/tm18/.cvsignore testsuites/tmtests/tm18/Makefile.am testsuites/tmtests/tm18/system.h testsuites/tmtests/tm18/task1.c testsuites/tmtests/tm18/tm18.doc testsuites/tmtests/tm19/.cvsignore testsuites/tmtests/tm19/Makefile.am testsuites/tmtests/tm19/system.h testsuites/tmtests/tm19/task1.c testsuites/tmtests/tm19/tm19.doc testsuites/tmtests/tm20/.cvsignore testsuites/tmtests/tm20/Makefile.am testsuites/tmtests/tm20/system.h testsuites/tmtests/tm20/task1.c testsuites/tmtests/tm20/tm20.doc testsuites/tmtests/tm21/.cvsignore testsuites/tmtests/tm21/Makefile.am testsuites/tmtests/tm21/system.h testsuites/tmtests/tm21/task1.c testsuites/tmtests/tm21/tm21.doc testsuites/tmtests/tm22/.cvsignore testsuites/tmtests/tm22/Makefile.am testsuites/tmtests/tm22/system.h testsuites/tmtests/tm22/task1.c testsuites/tmtests/tm22/tm22.doc testsuites/tmtests/tm23/.cvsignore testsuites/tmtests/tm23/Makefile.am testsuites/tmtests/tm23/system.h testsuites/tmtests/tm23/task1.c testsuites/tmtests/tm23/tm23.doc testsuites/tmtests/tm24/.cvsignore testsuites/tmtests/tm24/Makefile.am testsuites/tmtests/tm24/system.h testsuites/tmtests/tm24/task1.c testsuites/tmtests/tm24/tm24.doc testsuites/tmtests/tm25/.cvsignore testsuites/tmtests/tm25/Makefile.am testsuites/tmtests/tm25/system.h testsuites/tmtests/tm25/task1.c testsuites/tmtests/tm25/tm25.doc testsuites/tmtests/tm26/.cvsignore testsuites/tmtests/tm26/Makefile.am testsuites/tmtests/tm26/fptest.h testsuites/tmtests/tm26/system.h testsuites/tmtests/tm26/task1.c testsuites/tmtests/tm26/tm26.doc testsuites/tmtests/tm27/.cvsignore testsuites/tmtests/tm27/Makefile.am testsuites/tmtests/tm27/system.h testsuites/tmtests/tm27/task1.c testsuites/tmtests/tm27/tm27.doc testsuites/tmtests/tm28/.cvsignore testsuites/tmtests/tm28/Makefile.am testsuites/tmtests/tm28/system.h testsuites/tmtests/tm28/task1.c testsuites/tmtests/tm28/tm28.doc testsuites/tmtests/tm29/.cvsignore testsuites/tmtests/tm29/Makefile.am testsuites/tmtests/tm29/system.h testsuites/tmtests/tm29/task1.c testsuites/tmtests/tm29/tm29.doc testsuites/tmtests/tmck/.cvsignore testsuites/tmtests/tmck/Makefile.am testsuites/tmtests/tmck/system.h testsuites/tmtests/tmck/task1.c testsuites/tmtests/tmck/tmck.doc testsuites/tmtests/tmoverhd/.cvsignore testsuites/tmtests/tmoverhd/Makefile.am testsuites/tmtests/tmoverhd/dumrtems.h testsuites/tmtests/tmoverhd/empty.c testsuites/tmtests/tmoverhd/system.h testsuites/tmtests/tmoverhd/testtask.c testsuites/tmtests/tmoverhd/tmoverhd.doc testsuites/tmtests/tmtests.am testsuites/tools/.cvsignore testsuites/tools/ChangeLog testsuites/tools/Makefile.am testsuites/tools/configure.ac testsuites/tools/generic/.cvsignore testsuites/tools/generic/ChangeLog testsuites/tools/generic/Makefile.am testsuites/tools/generic/configure.ac testsuites/tools/generic/difftest.in testsuites/tools/generic/sorttimes.in
This commit is contained in:
cvs2git
@@ -1,14 +0,0 @@
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aclocal.m4
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autom4te*.cache
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config.cache
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config.guess
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config.log
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config.status
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config.sub
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configure
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depcomp
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install-sh
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Makefile
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Makefile.in
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missing
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mkinstalldirs
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@@ -1,62 +0,0 @@
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2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* configure.ac: AM_INIT_AUTOMAKE([1.7.2]).
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2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* configure.ac: AC_PREREQ(2.57).
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2003-02-03 Joel Sherrill <joel@OARcorp.com>
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PR 338/filesystem
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* rtems.adb, rtems.ads: Side-effect of fixing reentrancy problem with
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rtems_io_lookup_name() (API change).
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2003-01-03 Joel Sherrill <joel@OARcorp.com>
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* rtems.ads: Corrected Configuration_Table record definition to
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match current RTEMS source. sp01 now runs.
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2002-11-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* configure.ac: Fix package name.
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2002-10-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* configure.ac: Remove AC_ENABLE_MULTILIB.
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* Makefile.am: Add CVS-Id.
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2002-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
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2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* .cvsignore: Reformat.
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Add autom4te*cache.
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Remove autom4te.cache.
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2002-08-30 Joel Sherrill <joel@OARcorp.com>
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* rtems.adb (IO_Initialize): Make this match the C prototype.
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2002-08-27 Joel Sherrill <joel@OARcorp.com>
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* rtems.ads: Corrected binding for Io_Initialize.
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2001-08-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* configure.ac: New.
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* Makefile.am: New.
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* .cvsignore: New.
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2001-02-01 Joel Sherrill <joel@OARcorp.com>
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* rtems.ads, rtems.adb: Formatting cleaned up. Task based timer
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directives added. This is Timer_Initiate_Server,
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Timer_Server_Fire_After, and Timer_Server_Fire_When.
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2001-02-01 Joel Sherrill <joel@OARcorp.com>
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* ChangeLog: New file.
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@@ -1,24 +0,0 @@
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#
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# $Id$
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#
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ACLOCAL_AMFLAGS = -I ../aclocal
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$(PROJECT_INCLUDE)/adainclude:
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$(mkinstalldirs) $@
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$(PROJECT_INCLUDE)/adainclude/%: %
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$(INSTALL_DATA) $< $@
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adaincludedir = $(includedir)/adainclude
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adainclude_HEADERS = rtems.adb rtems.ads
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adainclude_HEADERS += rtems-multiprocessing.adb rtems-multiprocessing.ads
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TMPINSTALL_FILES = \
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$(PROJECT_INCLUDE)/adainclude \
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$(adainclude_HEADERS:%=$(PROJECT_INCLUDE)/adainclude/%) \
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$(nodist_adalib_HEADERS:%=$(PROJECT_INCLUDE)/adainclude/%)
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all-local: $(TMPINSTALL_FILES)
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include $(top_srcdir)/../automake/local.am
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@@ -1,38 +0,0 @@
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--
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-- RTEMS Multiprocessing Manager/ Body
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--
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-- DESCRIPTION:
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--
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-- This package provides the interface to the Multiprocessing Manager
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-- of the RTEMS API.
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--
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-- DEPENDENCIES:
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--
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--
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-- COPYRIGHT (c) 1997.
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-- On-Line Applications Research Corporation (OAR).
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--
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-- The license and distribution terms for this file may in
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-- the file LICENSE in this distribution or at
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-- http://www.OARcorp.com/rtems/license.html.
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--
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-- $Id$
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--
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package body RTEMS.Multiprocessing is
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--
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-- Announce
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--
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procedure Announce is
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procedure Multiprocessing_Announce_Base;
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pragma Import (C, Multiprocessing_Announce_Base,
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"rtems_multiprocessing_announce");
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begin
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Multiprocessing_Announce_Base;
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end Announce;
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end RTEMS.Multiprocessing;
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@@ -1,30 +0,0 @@
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--
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-- RTEMS Multiprocessing Manager/ Specification
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--
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-- DESCRIPTION:
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--
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||||
-- This package provides the interface to the Multiprocessing Manager
|
||||
-- of the RTEMS API.
|
||||
--
|
||||
-- DEPENDENCIES:
|
||||
--
|
||||
--
|
||||
-- COPYRIGHT (c) 1997.
|
||||
-- On-Line Applications Research Corporation (OAR).
|
||||
--
|
||||
-- The license and distribution terms for this file may in
|
||||
-- the file LICENSE in this distribution or at
|
||||
-- http://www.OARcorp.com/rtems/license.html.
|
||||
--
|
||||
-- $Id$
|
||||
--
|
||||
|
||||
package RTEMS.Multiprocessing is
|
||||
|
||||
--
|
||||
-- Multiprocessing Manager
|
||||
--
|
||||
|
||||
procedure Announce;
|
||||
|
||||
end RTEMS.Multiprocessing;
|
||||
1947
c/src/ada/rtems.adb
1947
c/src/ada/rtems.adb
File diff suppressed because it is too large
Load Diff
1457
c/src/ada/rtems.ads
1457
c/src/ada/rtems.ads
File diff suppressed because it is too large
Load Diff
@@ -1,86 +0,0 @@
|
||||
2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: AM_INIT_AUTOMAKE([1.7.2]).
|
||||
|
||||
2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: AC_PREREQ(2.57).
|
||||
|
||||
2002-12-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Don't include @RTEMS_BSP@.cfg.
|
||||
* configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP.
|
||||
|
||||
2002-11-01 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* cpu.c: Currently only the mpc8260 BSP supports interrupt nesting.
|
||||
NOTE: These needs to be generalized as the patch is applied to other
|
||||
BSPs.
|
||||
|
||||
2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* .cvsignore: Reformat.
|
||||
Add autom4te*cache.
|
||||
Remove autom4te.cache.
|
||||
|
||||
2002-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Use .$(OBJEXT) instead of .o.
|
||||
|
||||
2001-05-14 Till Straumann <strauman@slac.stanford.edu>
|
||||
|
||||
* cpu.c: Per PR211 fix
|
||||
saving/restoring floating point context. The fpsave and fprestore
|
||||
routines are only used in a executing context which _is_ fp and hence
|
||||
has the FPU enabled. The current behavior required the FPU always to
|
||||
be on which is very dangerous if lazy context switching is used.
|
||||
[Joel Note: Some ports explicitly enabled the FPU in the FP save and
|
||||
restore routines to avoid this.]
|
||||
|
||||
The patch also makes sure (on powerpc only) that the FPU is disabled
|
||||
for integer tasks. Note that this is crucial if deferred fp context
|
||||
switching is used. Otherwise, fp context corruption may go undetected!
|
||||
Also note that even tasks which merely push/pop FP registers to/from
|
||||
the stack without modifying them still MUST be FP tasks - otherwise
|
||||
(if lazy FP context switching is used), FP register corruption (of
|
||||
other, FP, tasks may occur)!
|
||||
|
||||
Furthermore, (on PPC) by default, lazy FP context save/restore
|
||||
is _disabled_.
|
||||
|
||||
2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* rtems/score/cpu.h: Removed.
|
||||
* Makefile.am: Reflect changes above.
|
||||
|
||||
2001-04-03 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
|
||||
* rtems/score/cpu.h: Account for name change.
|
||||
|
||||
2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac:
|
||||
AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
|
||||
AM_INIT_AUTOMAKE([no-define foreign 1.6]).
|
||||
* Makefile.am: Remove AUTOMAKE_OPTIONS.
|
||||
|
||||
2001-11-28 Joel Sherrill <joel@OARcorp.com>,
|
||||
|
||||
This was tracked as PR91.
|
||||
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
|
||||
is used to specify if the port uses the standard macro for this (FALSE).
|
||||
A TRUE setting indicates the port provides its own implementation.
|
||||
* rtems/score/c_isr.inl: Deleted and contents merged into cpu.c.
|
||||
* cpu.c: Received contents of c_isr.inl.
|
||||
* Makefile.am: Deleted reference to c_isr.inl.
|
||||
|
||||
2001-11-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* .cvsignore: Add aclocal.m4, autom4te.*, config.*, configure.
|
||||
|
||||
2001-11-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Preinstall c_isr.inl (HACK).
|
||||
* ChangeLog: New file.
|
||||
|
||||
@@ -1,148 +0,0 @@
|
||||
/*
|
||||
* PowerPC CPU Dependent Source
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/cpu/no_cpu/cpu.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be found in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems/system.h>
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/context.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
|
||||
/* _CPU_Initialize
|
||||
*
|
||||
* This routine performs processor dependent initialization.
|
||||
*
|
||||
* INPUT PARAMETERS:
|
||||
* cpu_table - CPU table to initialize
|
||||
* thread_dispatch - address of disptaching routine
|
||||
*/
|
||||
|
||||
void _CPU_Initialize(
|
||||
rtems_cpu_table *cpu_table,
|
||||
void (*thread_dispatch) /* ignored on this CPU */
|
||||
)
|
||||
{
|
||||
_CPU_Table = *cpu_table;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Context_Initialize
|
||||
*/
|
||||
|
||||
void _CPU_Context_Initialize(
|
||||
Context_Control *the_context,
|
||||
unsigned32 *stack_base,
|
||||
unsigned32 size,
|
||||
unsigned32 new_level,
|
||||
void *entry_point,
|
||||
boolean is_fp
|
||||
)
|
||||
{
|
||||
unsigned32 msr_value;
|
||||
unsigned32 sp;
|
||||
|
||||
sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
|
||||
*((unsigned32 *)sp) = 0;
|
||||
the_context->gpr1 = sp;
|
||||
|
||||
_CPU_MSR_GET( msr_value );
|
||||
|
||||
if (!(new_level & CPU_MODES_INTERRUPT_MASK)) {
|
||||
msr_value |= MSR_EE;
|
||||
}
|
||||
else {
|
||||
msr_value &= ~MSR_EE;
|
||||
}
|
||||
|
||||
the_context->msr = msr_value;
|
||||
|
||||
/*
|
||||
* The FP bit of the MSR should only be enabled if this is a floating
|
||||
* point task. Unfortunately, the vfprintf_r routine in newlib
|
||||
* ends up pushing a floating point register regardless of whether or
|
||||
* not a floating point number is being printed. Serious restructuring
|
||||
* of vfprintf.c will be required to avoid this behavior. At this
|
||||
* time (7 July 1997), this restructuring is not being done.
|
||||
*/
|
||||
|
||||
/* Till Straumann: For deferred FPContext save/restore, make sure integer
|
||||
* tasks have no FPU access in order to catch violations.
|
||||
* Otherwise, the FP registers may be corrupted.
|
||||
* Since we set the_contex->msr using our current MSR,
|
||||
* we must make sure MSR_FP is off if (!is_fp)...
|
||||
*/
|
||||
#if defined(CPU_USE_DEFERRED_FP_SWITCH) && (CPU_USE_DEFERRED_FP_SWITCH==TRUE)
|
||||
if ( is_fp )
|
||||
#endif
|
||||
the_context->msr |= PPC_MSR_FP;
|
||||
#if defined(CPU_USE_DEFERRED_FP_SWITCH) && (CPU_USE_DEFERRED_FP_SWITCH==TRUE)
|
||||
else
|
||||
the_context->msr &= ~PPC_MSR_FP;
|
||||
#endif
|
||||
|
||||
the_context->pc = (unsigned32)entry_point;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Install_interrupt_stack
|
||||
*/
|
||||
|
||||
void _CPU_Install_interrupt_stack( void )
|
||||
{
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* This is the PowerPC specific implementation of the routine which
|
||||
* returns TRUE if an interrupt is in progress.
|
||||
*/
|
||||
|
||||
boolean _ISR_Is_in_progress( void )
|
||||
{
|
||||
/*
|
||||
* Until the patch on PR288 is in all new exception BSPs, this is
|
||||
* the safest thing to do.
|
||||
*/
|
||||
#ifdef mpc8260
|
||||
return (_ISR_Nest_level != 0);
|
||||
#else
|
||||
register unsigned int isr_nesting_level;
|
||||
/*
|
||||
* Move from special purpose register 0 (mfspr SPRG0, r3)
|
||||
*/
|
||||
asm volatile ("mfspr %0, 272" : "=r" (isr_nesting_level));
|
||||
return isr_nesting_level;
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -1,405 +0,0 @@
|
||||
|
||||
/* cpu_asm.s 1.1 - 95/12/04
|
||||
*
|
||||
* This file contains the assembly code for the PowerPC implementation
|
||||
* of RTEMS.
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <asm.h>
|
||||
|
||||
/*
|
||||
* Offsets for various Contexts
|
||||
*/
|
||||
.set GP_1, 0
|
||||
.set GP_2, (GP_1 + 4)
|
||||
.set GP_13, (GP_2 + 4)
|
||||
.set GP_14, (GP_13 + 4)
|
||||
|
||||
.set GP_15, (GP_14 + 4)
|
||||
.set GP_16, (GP_15 + 4)
|
||||
.set GP_17, (GP_16 + 4)
|
||||
.set GP_18, (GP_17 + 4)
|
||||
|
||||
.set GP_19, (GP_18 + 4)
|
||||
.set GP_20, (GP_19 + 4)
|
||||
.set GP_21, (GP_20 + 4)
|
||||
.set GP_22, (GP_21 + 4)
|
||||
|
||||
.set GP_23, (GP_22 + 4)
|
||||
.set GP_24, (GP_23 + 4)
|
||||
.set GP_25, (GP_24 + 4)
|
||||
.set GP_26, (GP_25 + 4)
|
||||
|
||||
.set GP_27, (GP_26 + 4)
|
||||
.set GP_28, (GP_27 + 4)
|
||||
.set GP_29, (GP_28 + 4)
|
||||
.set GP_30, (GP_29 + 4)
|
||||
|
||||
.set GP_31, (GP_30 + 4)
|
||||
.set GP_CR, (GP_31 + 4)
|
||||
.set GP_PC, (GP_CR + 4)
|
||||
.set GP_MSR, (GP_PC + 4)
|
||||
|
||||
#if (PPC_HAS_DOUBLE==1)
|
||||
.set FP_SIZE, 8
|
||||
#define LDF lfd
|
||||
#define STF stfd
|
||||
#else
|
||||
.set FP_SIZE, 4
|
||||
#define LDF lfs
|
||||
#define STF stfs
|
||||
#endif
|
||||
|
||||
.set FP_0, 0
|
||||
.set FP_1, (FP_0 + FP_SIZE)
|
||||
.set FP_2, (FP_1 + FP_SIZE)
|
||||
.set FP_3, (FP_2 + FP_SIZE)
|
||||
.set FP_4, (FP_3 + FP_SIZE)
|
||||
.set FP_5, (FP_4 + FP_SIZE)
|
||||
.set FP_6, (FP_5 + FP_SIZE)
|
||||
.set FP_7, (FP_6 + FP_SIZE)
|
||||
.set FP_8, (FP_7 + FP_SIZE)
|
||||
.set FP_9, (FP_8 + FP_SIZE)
|
||||
.set FP_10, (FP_9 + FP_SIZE)
|
||||
.set FP_11, (FP_10 + FP_SIZE)
|
||||
.set FP_12, (FP_11 + FP_SIZE)
|
||||
.set FP_13, (FP_12 + FP_SIZE)
|
||||
.set FP_14, (FP_13 + FP_SIZE)
|
||||
.set FP_15, (FP_14 + FP_SIZE)
|
||||
.set FP_16, (FP_15 + FP_SIZE)
|
||||
.set FP_17, (FP_16 + FP_SIZE)
|
||||
.set FP_18, (FP_17 + FP_SIZE)
|
||||
.set FP_19, (FP_18 + FP_SIZE)
|
||||
.set FP_20, (FP_19 + FP_SIZE)
|
||||
.set FP_21, (FP_20 + FP_SIZE)
|
||||
.set FP_22, (FP_21 + FP_SIZE)
|
||||
.set FP_23, (FP_22 + FP_SIZE)
|
||||
.set FP_24, (FP_23 + FP_SIZE)
|
||||
.set FP_25, (FP_24 + FP_SIZE)
|
||||
.set FP_26, (FP_25 + FP_SIZE)
|
||||
.set FP_27, (FP_26 + FP_SIZE)
|
||||
.set FP_28, (FP_27 + FP_SIZE)
|
||||
.set FP_29, (FP_28 + FP_SIZE)
|
||||
.set FP_30, (FP_29 + FP_SIZE)
|
||||
.set FP_31, (FP_30 + FP_SIZE)
|
||||
.set FP_FPSCR, (FP_31 + FP_SIZE)
|
||||
|
||||
.set IP_LINK, 0
|
||||
.set IP_0, (IP_LINK + 8)
|
||||
.set IP_2, (IP_0 + 4)
|
||||
|
||||
.set IP_3, (IP_2 + 4)
|
||||
.set IP_4, (IP_3 + 4)
|
||||
.set IP_5, (IP_4 + 4)
|
||||
.set IP_6, (IP_5 + 4)
|
||||
|
||||
.set IP_7, (IP_6 + 4)
|
||||
.set IP_8, (IP_7 + 4)
|
||||
.set IP_9, (IP_8 + 4)
|
||||
.set IP_10, (IP_9 + 4)
|
||||
|
||||
.set IP_11, (IP_10 + 4)
|
||||
.set IP_12, (IP_11 + 4)
|
||||
.set IP_13, (IP_12 + 4)
|
||||
.set IP_28, (IP_13 + 4)
|
||||
|
||||
.set IP_29, (IP_28 + 4)
|
||||
.set IP_30, (IP_29 + 4)
|
||||
.set IP_31, (IP_30 + 4)
|
||||
.set IP_CR, (IP_31 + 4)
|
||||
|
||||
.set IP_CTR, (IP_CR + 4)
|
||||
.set IP_XER, (IP_CTR + 4)
|
||||
.set IP_LR, (IP_XER + 4)
|
||||
.set IP_PC, (IP_LR + 4)
|
||||
|
||||
.set IP_MSR, (IP_PC + 4)
|
||||
.set IP_END, (IP_MSR + 16)
|
||||
|
||||
BEGIN_CODE
|
||||
/*
|
||||
* _CPU_Context_save_fp_context
|
||||
*
|
||||
* This routine is responsible for saving the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* Sometimes a macro implementation of this is in cpu.h which dereferences
|
||||
* the ** and a similarly named routine in this file is passed something
|
||||
* like a (Context_Control_fp *). The general rule on making this decision
|
||||
* is to avoid writing assembly language.
|
||||
*/
|
||||
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_save_fp)
|
||||
PROC (_CPU_Context_save_fp):
|
||||
#if (PPC_HAS_FPU == 1)
|
||||
lwz r3, 0(r3)
|
||||
STF f0, FP_0(r3)
|
||||
STF f1, FP_1(r3)
|
||||
STF f2, FP_2(r3)
|
||||
STF f3, FP_3(r3)
|
||||
STF f4, FP_4(r3)
|
||||
STF f5, FP_5(r3)
|
||||
STF f6, FP_6(r3)
|
||||
STF f7, FP_7(r3)
|
||||
STF f8, FP_8(r3)
|
||||
STF f9, FP_9(r3)
|
||||
STF f10, FP_10(r3)
|
||||
STF f11, FP_11(r3)
|
||||
STF f12, FP_12(r3)
|
||||
STF f13, FP_13(r3)
|
||||
STF f14, FP_14(r3)
|
||||
STF f15, FP_15(r3)
|
||||
STF f16, FP_16(r3)
|
||||
STF f17, FP_17(r3)
|
||||
STF f18, FP_18(r3)
|
||||
STF f19, FP_19(r3)
|
||||
STF f20, FP_20(r3)
|
||||
STF f21, FP_21(r3)
|
||||
STF f22, FP_22(r3)
|
||||
STF f23, FP_23(r3)
|
||||
STF f24, FP_24(r3)
|
||||
STF f25, FP_25(r3)
|
||||
STF f26, FP_26(r3)
|
||||
STF f27, FP_27(r3)
|
||||
STF f28, FP_28(r3)
|
||||
STF f29, FP_29(r3)
|
||||
STF f30, FP_30(r3)
|
||||
STF f31, FP_31(r3)
|
||||
mffs f2
|
||||
STF f2, FP_FPSCR(r3)
|
||||
#endif
|
||||
blr
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore_fp_context
|
||||
*
|
||||
* This routine is responsible for restoring the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* Sometimes a macro implementation of this is in cpu.h which dereferences
|
||||
* the ** and a similarly named routine in this file is passed something
|
||||
* like a (Context_Control_fp *). The general rule on making this decision
|
||||
* is to avoid writing assembly language.
|
||||
*/
|
||||
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_restore_fp)
|
||||
PROC (_CPU_Context_restore_fp):
|
||||
#if (PPC_HAS_FPU == 1)
|
||||
lwz r3, 0(r3)
|
||||
LDF f2, FP_FPSCR(r3)
|
||||
mtfsf 255, f2
|
||||
LDF f0, FP_0(r3)
|
||||
LDF f1, FP_1(r3)
|
||||
LDF f2, FP_2(r3)
|
||||
LDF f3, FP_3(r3)
|
||||
LDF f4, FP_4(r3)
|
||||
LDF f5, FP_5(r3)
|
||||
LDF f6, FP_6(r3)
|
||||
LDF f7, FP_7(r3)
|
||||
LDF f8, FP_8(r3)
|
||||
LDF f9, FP_9(r3)
|
||||
LDF f10, FP_10(r3)
|
||||
LDF f11, FP_11(r3)
|
||||
LDF f12, FP_12(r3)
|
||||
LDF f13, FP_13(r3)
|
||||
LDF f14, FP_14(r3)
|
||||
LDF f15, FP_15(r3)
|
||||
LDF f16, FP_16(r3)
|
||||
LDF f17, FP_17(r3)
|
||||
LDF f18, FP_18(r3)
|
||||
LDF f19, FP_19(r3)
|
||||
LDF f20, FP_20(r3)
|
||||
LDF f21, FP_21(r3)
|
||||
LDF f22, FP_22(r3)
|
||||
LDF f23, FP_23(r3)
|
||||
LDF f24, FP_24(r3)
|
||||
LDF f25, FP_25(r3)
|
||||
LDF f26, FP_26(r3)
|
||||
LDF f27, FP_27(r3)
|
||||
LDF f28, FP_28(r3)
|
||||
LDF f29, FP_29(r3)
|
||||
LDF f30, FP_30(r3)
|
||||
LDF f31, FP_31(r3)
|
||||
#endif
|
||||
blr
|
||||
|
||||
|
||||
/* _CPU_Context_switch
|
||||
*
|
||||
* This routine performs a normal non-FP context switch.
|
||||
*/
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_switch)
|
||||
PROC (_CPU_Context_switch):
|
||||
sync
|
||||
isync
|
||||
/* This assumes that all the registers are in the given order */
|
||||
li r5, 32
|
||||
addi r3,r3,-4
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r1, GP_1+4(r3)
|
||||
stw r2, GP_2+4(r3)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
addi r3, r3, GP_18+4
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stmw r13, GP_13-GP_18(r3)
|
||||
#else
|
||||
stw r13, GP_13+4(r3)
|
||||
stw r14, GP_14+4(r3)
|
||||
stw r15, GP_15+4(r3)
|
||||
stw r16, GP_16+4(r3)
|
||||
stw r17, GP_17+4(r3)
|
||||
stwu r18, GP_18+4(r3)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r19, GP_19-GP_18(r3)
|
||||
stw r20, GP_20-GP_18(r3)
|
||||
stw r21, GP_21-GP_18(r3)
|
||||
stw r22, GP_22-GP_18(r3)
|
||||
stw r23, GP_23-GP_18(r3)
|
||||
stw r24, GP_24-GP_18(r3)
|
||||
stw r25, GP_25-GP_18(r3)
|
||||
stw r26, GP_26-GP_18(r3)
|
||||
stw r27, GP_27-GP_18(r3)
|
||||
stw r28, GP_28-GP_18(r3)
|
||||
stw r29, GP_29-GP_18(r3)
|
||||
stw r30, GP_30-GP_18(r3)
|
||||
stw r31, GP_31-GP_18(r3)
|
||||
#endif
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r0, r4
|
||||
#endif
|
||||
mfcr r6
|
||||
stw r6, GP_CR-GP_18(r3)
|
||||
mflr r7
|
||||
stw r7, GP_PC-GP_18(r3)
|
||||
mfmsr r8
|
||||
stw r8, GP_MSR-GP_18(r3)
|
||||
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r1, GP_1(r4)
|
||||
lwz r2, GP_2(r4)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
addi r4, r4, GP_19
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lmw r13, GP_13-GP_19(r4)
|
||||
#else
|
||||
lwz r13, GP_13(r4)
|
||||
lwz r14, GP_14(r4)
|
||||
lwz r15, GP_15(r4)
|
||||
lwz r16, GP_16(r4)
|
||||
lwz r17, GP_17(r4)
|
||||
lwz r18, GP_18(r4)
|
||||
lwzu r19, GP_19(r4)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r20, GP_20-GP_19(r4)
|
||||
lwz r21, GP_21-GP_19(r4)
|
||||
lwz r22, GP_22-GP_19(r4)
|
||||
lwz r23, GP_23-GP_19(r4)
|
||||
lwz r24, GP_24-GP_19(r4)
|
||||
lwz r25, GP_25-GP_19(r4)
|
||||
lwz r26, GP_26-GP_19(r4)
|
||||
lwz r27, GP_27-GP_19(r4)
|
||||
lwz r28, GP_28-GP_19(r4)
|
||||
lwz r29, GP_29-GP_19(r4)
|
||||
lwz r30, GP_30-GP_19(r4)
|
||||
lwz r31, GP_31-GP_19(r4)
|
||||
#endif
|
||||
lwz r6, GP_CR-GP_19(r4)
|
||||
lwz r7, GP_PC-GP_19(r4)
|
||||
lwz r8, GP_MSR-GP_19(r4)
|
||||
mtcrf 255, r6
|
||||
mtlr r7
|
||||
mtmsr r8
|
||||
|
||||
blr
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore
|
||||
*
|
||||
* This routine is generallu used only to restart self in an
|
||||
* efficient manner. It may simply be a label in _CPU_Context_switch.
|
||||
*
|
||||
* NOTE: May be unnecessary to reload some registers.
|
||||
*/
|
||||
/*
|
||||
* ACB: Don't worry about cache optimisation here - this is not THAT critical.
|
||||
*/
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_restore)
|
||||
PROC (_CPU_Context_restore):
|
||||
lwz r5, GP_CR(r3)
|
||||
lwz r6, GP_PC(r3)
|
||||
lwz r7, GP_MSR(r3)
|
||||
mtcrf 255, r5
|
||||
mtlr r6
|
||||
mtmsr r7
|
||||
lwz r1, GP_1(r3)
|
||||
lwz r2, GP_2(r3)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
lmw r13, GP_13(r3)
|
||||
#else
|
||||
lwz r13, GP_13(r3)
|
||||
lwz r14, GP_14(r3)
|
||||
lwz r15, GP_15(r3)
|
||||
lwz r16, GP_16(r3)
|
||||
lwz r17, GP_17(r3)
|
||||
lwz r18, GP_18(r3)
|
||||
lwz r19, GP_19(r3)
|
||||
lwz r20, GP_20(r3)
|
||||
lwz r21, GP_21(r3)
|
||||
lwz r22, GP_22(r3)
|
||||
lwz r23, GP_23(r3)
|
||||
lwz r24, GP_24(r3)
|
||||
lwz r25, GP_25(r3)
|
||||
lwz r26, GP_26(r3)
|
||||
lwz r27, GP_27(r3)
|
||||
lwz r28, GP_28(r3)
|
||||
lwz r29, GP_29(r3)
|
||||
lwz r30, GP_30(r3)
|
||||
lwz r31, GP_31(r3)
|
||||
#endif
|
||||
|
||||
blr
|
||||
|
||||
@@ -1,78 +0,0 @@
|
||||
2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: AM_INIT_AUTOMAKE([1.7.2]).
|
||||
|
||||
2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: AC_PREREQ(2.57).
|
||||
|
||||
2002-12-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Don't include @RTEMS_BSP@.cfg.
|
||||
* configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP.
|
||||
|
||||
2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* .cvsignore: Reformat.
|
||||
Add autom4te*cache.
|
||||
Remove autom4te.cache.
|
||||
|
||||
2002-09-14 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* cpu.c: Include declaration of variable i in ifdef USE_SPRG to
|
||||
eliminate warning.
|
||||
|
||||
2002-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Use .$(OBJEXT) instead of .o.
|
||||
|
||||
2002-07-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Fix oversights in previous patch.
|
||||
|
||||
2002-07-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* rtems.S: Remove.
|
||||
* Makefile.am: Reflect having removed rtems.S. Use AM_CPPFLAGS
|
||||
instead of INCLUDES (Latest automake standard).
|
||||
|
||||
2002-04-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* cpu.c: Include <rtems/powerpc/cache.h>.
|
||||
|
||||
2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* rtems/score/cpu.h: Removed.
|
||||
* Makefile.am: Reflect changes above.
|
||||
|
||||
2001-04-03 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
|
||||
* rtems/score/cpu.h: Account for name change.
|
||||
|
||||
2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac:
|
||||
AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
|
||||
AM_INIT_AUTOMAKE([no-define foreign 1.6]).
|
||||
* Makefile.am: Remove AUTOMAKE_OPTIONS.
|
||||
|
||||
2001-11-28 Joel Sherrill <joel@OARcorp.com>,
|
||||
|
||||
This was tracked as PR91.
|
||||
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
|
||||
is used to specify if the port uses the standard macro for this (FALSE).
|
||||
A TRUE setting indicates the port provides its own implementation.
|
||||
* rtems/score/c_isr.inl: Deleted and contents merged into cpu.c.
|
||||
* cpu.c: Received contents of c_isr.inl.
|
||||
* Makefile.am: Deleted reference to c_isr.inl.
|
||||
|
||||
2001-11-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* .cvsignore: Add aclocal.m4, autom4te.*, config.*, configure.
|
||||
|
||||
2001-11-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Preinstall c_isr.inl (HACK).
|
||||
* ChangeLog: New file.
|
||||
|
||||
@@ -1,80 +0,0 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
There are various issues regarding this port:
|
||||
|
||||
|
||||
|
||||
1) Legal
|
||||
|
||||
This port is written by Andrew Bray <andy@i-cubed.co.uk>, and
|
||||
is copyright 1995 i-cubed ltd.
|
||||
|
||||
This port was later updated by Joel Sherrill <joel@OARcorp.com>
|
||||
to test the support for the PPC603, PPC603e, and MPC604. This
|
||||
was tested on the PowerPC simulator PSIM and a VMEbus single board
|
||||
computer.
|
||||
|
||||
2) CPU support.
|
||||
|
||||
This release fully supports the PPC403GA, PPC403GB, PPC603, PPC603e,
|
||||
MPC604, MPC750, and numerous MPC8xx processors. A good faith attempt
|
||||
has been made to include support other models based upon available
|
||||
documentation including the MPC5xx. There are two interrupt structures
|
||||
supported by the PowerPC port. The newer structure is supported by
|
||||
all the MPC750 and MPC604 BSPs. This structure is required to use
|
||||
the RDBG remote debugging support.
|
||||
|
||||
This port was originally written and tested on the PPC403GA (using
|
||||
software floating point). Current ports are tested primarily on
|
||||
60x CPUs using the PowerPC simulator PSIM.
|
||||
|
||||
Andrew Bray received assistance during the initial porting effort
|
||||
from IBM and Blue Micro and we would like to gratefully acknowledge
|
||||
that help.
|
||||
|
||||
The support for the PPC602 processor is incomplete as only sketchy
|
||||
data is currently available. Perhaps this model has been dropped.
|
||||
|
||||
3) Application Binary Interface
|
||||
|
||||
In the context of RTEMS, the ABI is of interest for the following
|
||||
aspects:
|
||||
|
||||
a) Register usage. Which registers are used to provide static variable
|
||||
linkage, stack pointer etc.
|
||||
|
||||
b) Function calling convention. How parameters are passed, how function
|
||||
variables should be invoked, how values are returned, etc.
|
||||
|
||||
c) Stack frame layout.
|
||||
|
||||
I am aware of a number of ABIs for the PowerPC:
|
||||
|
||||
a) The PowerOpen ABI. This is the original Power ABI used on the RS/6000.
|
||||
This is the only ABI supported by versions of GCC before 2.7.0.
|
||||
|
||||
b) The SVR4 ABI. This is the ABI defined by SunSoft for the Solaris port
|
||||
to the PowerPC.
|
||||
|
||||
c) The Embedded ABI. This is an embedded ABI for PowerPC use, which has no
|
||||
operating system interface defined. It is promoted by SunSoft, Motorola,
|
||||
and Cygnus Support. Cygnus are porting the GNU toolchain to this ABI.
|
||||
|
||||
d) GCC 2.7.0. This compiler is partway along the road to supporting the EABI,
|
||||
but is currently halfway in between.
|
||||
|
||||
This port was built and tested using the PowerOpen ABI, with the following
|
||||
caveat: we used an ELF assembler and linker. So some attention may be
|
||||
required on the assembler files to get them through a traditional (XCOFF)
|
||||
PowerOpen assembler.
|
||||
|
||||
This port contains support for the other ABIs, but this may prove to be
|
||||
incomplete as it is untested.
|
||||
|
||||
The RTEMS PowerPC port supports EABI as the primary ABI. The powerpc-rtems
|
||||
GNU toolset configuration is EABI.
|
||||
|
||||
Andrew Bray, 4 December 1995
|
||||
Joel Sherrill, 16 July 1997
|
||||
@@ -1,8 +0,0 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
Todo list:
|
||||
|
||||
Maybe decode external interrupts like the HPPA does.
|
||||
See c/src/lib/libcpu/powerpc/ppc403/ictrl/* for implementation on ppc403
|
||||
@@ -1,895 +0,0 @@
|
||||
/*
|
||||
* PowerPC CPU Dependent Source
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/cpu/no_cpu/cpu.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be found in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems/system.h>
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/context.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
#include <rtems/powerpc/cache.h>
|
||||
|
||||
/*
|
||||
* These are for testing purposes.
|
||||
*/
|
||||
|
||||
/* _CPU_Initialize
|
||||
*
|
||||
* This routine performs processor dependent initialization.
|
||||
*
|
||||
* INPUT PARAMETERS:
|
||||
* cpu_table - CPU table to initialize
|
||||
* thread_dispatch - address of disptaching routine
|
||||
*/
|
||||
|
||||
static void ppc_spurious(int, CPU_Interrupt_frame *);
|
||||
|
||||
int _CPU_spurious_count = 0;
|
||||
int _CPU_last_spurious = 0;
|
||||
|
||||
void _CPU_Initialize(
|
||||
rtems_cpu_table *cpu_table,
|
||||
void (*thread_dispatch) /* ignored on this CPU */
|
||||
)
|
||||
{
|
||||
#if (PPC_USE_SPRG)
|
||||
int i;
|
||||
#endif
|
||||
#if (PPC_ABI != PPC_ABI_POWEROPEN)
|
||||
register unsigned32 r2 = 0;
|
||||
#if (PPC_ABI != PPC_ABI_GCC27)
|
||||
register unsigned32 r13 = 0;
|
||||
|
||||
asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
|
||||
_CPU_IRQ_info.Default_r13 = r13;
|
||||
#endif
|
||||
|
||||
asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
|
||||
_CPU_IRQ_info.Default_r2 = r2;
|
||||
#endif
|
||||
|
||||
_CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
|
||||
_CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
|
||||
/* fill in _CPU_IRQ_info.Vector_table later */
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
_CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1];
|
||||
#endif
|
||||
_CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
|
||||
_CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
|
||||
|
||||
#if (PPC_USE_SPRG)
|
||||
i = (int)&_CPU_IRQ_info;
|
||||
asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Store Msr Value in the IRQ info structure.
|
||||
*/
|
||||
_CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
|
||||
|
||||
#if (PPC_USE_SPRG)
|
||||
i = _CPU_IRQ_info.msr_initial;
|
||||
asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
|
||||
#endif
|
||||
|
||||
_CPU_Table = *cpu_table;
|
||||
}
|
||||
|
||||
/*
|
||||
* _CPU_Initialize_vectors()
|
||||
*
|
||||
* Support routine to initialize the RTEMS vector table after it is allocated.
|
||||
*
|
||||
* PowerPC Specific Information:
|
||||
*
|
||||
* Complete initialization since the table is now allocated.
|
||||
*/
|
||||
|
||||
void _CPU_Initialize_vectors(void)
|
||||
{
|
||||
int i;
|
||||
proc_ptr handler = (proc_ptr)ppc_spurious;
|
||||
|
||||
_CPU_IRQ_info.Vector_table = _ISR_Vector_table;
|
||||
|
||||
if ( _CPU_Table.spurious_handler )
|
||||
handler = (proc_ptr)_CPU_Table.spurious_handler;
|
||||
|
||||
for (i = 0; i < PPC_INTERRUPT_MAX; i++)
|
||||
_ISR_Vector_table[i] = handler;
|
||||
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_Calculate_level
|
||||
*
|
||||
* The PowerPC puts its interrupt enable status in the MSR register
|
||||
* which also contains things like endianness control. To be more
|
||||
* awkward, the layout varies from processor to processor. This
|
||||
* is why it was necessary to adopt a scheme which allowed the user
|
||||
* to specify specifically which interrupt sources were enabled.
|
||||
*/
|
||||
|
||||
unsigned32 _CPU_ISR_Calculate_level(
|
||||
unsigned32 new_level
|
||||
)
|
||||
{
|
||||
register unsigned32 new_msr = 0;
|
||||
|
||||
/*
|
||||
* Set the critical interrupt enable bit
|
||||
*/
|
||||
|
||||
#if (PPC_HAS_RFCI)
|
||||
if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
|
||||
new_msr |= PPC_MSR_CE;
|
||||
#endif
|
||||
|
||||
if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
|
||||
new_msr |= PPC_MSR_ME;
|
||||
|
||||
if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
|
||||
new_msr |= PPC_MSR_EE;
|
||||
|
||||
return new_msr;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_Set_level
|
||||
*
|
||||
* This routine sets the requested level in the MSR.
|
||||
*/
|
||||
|
||||
void _CPU_ISR_Set_level(
|
||||
unsigned32 new_level
|
||||
)
|
||||
{
|
||||
register unsigned32 tmp = 0;
|
||||
register unsigned32 new_msr;
|
||||
|
||||
new_msr = _CPU_ISR_Calculate_level( new_level );
|
||||
|
||||
asm volatile (
|
||||
"mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
|
||||
"=&r" ((tmp)) :
|
||||
"r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
|
||||
);
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_Get_level
|
||||
*
|
||||
* This routine gets the current interrupt level from the MSR and
|
||||
* converts it to an RTEMS interrupt level.
|
||||
*/
|
||||
|
||||
unsigned32 _CPU_ISR_Get_level( void )
|
||||
{
|
||||
unsigned32 level = 0;
|
||||
unsigned32 msr;
|
||||
|
||||
asm volatile("mfmsr %0" : "=r" ((msr)));
|
||||
|
||||
msr &= PPC_MSR_DISABLE_MASK;
|
||||
|
||||
/*
|
||||
* Set the critical interrupt enable bit
|
||||
*/
|
||||
|
||||
#if (PPC_HAS_RFCI)
|
||||
if ( !(msr & PPC_MSR_CE) )
|
||||
level |= PPC_INTERRUPT_LEVEL_CE;
|
||||
#endif
|
||||
|
||||
if ( !(msr & PPC_MSR_ME) )
|
||||
level |= PPC_INTERRUPT_LEVEL_ME;
|
||||
|
||||
if ( !(msr & PPC_MSR_EE) )
|
||||
level |= PPC_INTERRUPT_LEVEL_EE;
|
||||
|
||||
return level;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Context_Initialize
|
||||
*/
|
||||
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
#define CPU_MINIMUM_STACK_FRAME_SIZE 56
|
||||
#else /* PPC_ABI_SVR4 or PPC_ABI_EABI */
|
||||
#define CPU_MINIMUM_STACK_FRAME_SIZE 8
|
||||
#endif
|
||||
|
||||
void _CPU_Context_Initialize(
|
||||
Context_Control *the_context,
|
||||
unsigned32 *stack_base,
|
||||
unsigned32 size,
|
||||
unsigned32 new_level,
|
||||
void *entry_point,
|
||||
boolean is_fp
|
||||
)
|
||||
{
|
||||
unsigned32 msr_value;
|
||||
unsigned32 sp;
|
||||
|
||||
sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
|
||||
*((unsigned32 *)sp) = 0;
|
||||
the_context->gpr1 = sp;
|
||||
|
||||
the_context->msr = _CPU_ISR_Calculate_level( new_level );
|
||||
|
||||
/*
|
||||
* The FP bit of the MSR should only be enabled if this is a floating
|
||||
* point task. Unfortunately, the vfprintf_r routine in newlib
|
||||
* ends up pushing a floating point register regardless of whether or
|
||||
* not a floating point number is being printed. Serious restructuring
|
||||
* of vfprintf.c will be required to avoid this behavior. At this
|
||||
* time (7 July 1997), this restructuring is not being done.
|
||||
*/
|
||||
|
||||
/*if ( is_fp ) */
|
||||
the_context->msr |= PPC_MSR_FP;
|
||||
|
||||
/*
|
||||
* Calculate the task's MSR value:
|
||||
*
|
||||
* + Set the exception prefix bit to point to the exception table
|
||||
* + Force the RI bit
|
||||
* + Use the DR and IR bits
|
||||
*/
|
||||
_CPU_MSR_Value( msr_value );
|
||||
the_context->msr |= (msr_value & PPC_MSR_EP);
|
||||
the_context->msr |= PPC_MSR_RI;
|
||||
the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR);
|
||||
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
{ unsigned32 *desc = (unsigned32 *)entry_point;
|
||||
|
||||
the_context->pc = desc[0];
|
||||
the_context->gpr2 = desc[1];
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (PPC_ABI == PPC_ABI_SVR4)
|
||||
{ unsigned r13 = 0;
|
||||
asm volatile ("mr %0, 13" : "=r" ((r13)));
|
||||
|
||||
the_context->pc = (unsigned32)entry_point;
|
||||
the_context->gpr13 = r13;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (PPC_ABI == PPC_ABI_EABI)
|
||||
{ unsigned32 r2 = 0;
|
||||
unsigned r13 = 0;
|
||||
asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
|
||||
|
||||
the_context->pc = (unsigned32)entry_point;
|
||||
the_context->gpr2 = r2;
|
||||
the_context->gpr13 = r13;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* _CPU_ISR_install_vector
|
||||
*
|
||||
* This kernel routine installs the RTEMS handler for the
|
||||
* specified vector.
|
||||
*
|
||||
* Input parameters:
|
||||
* vector - interrupt vector number
|
||||
* old_handler - former ISR for this vector number
|
||||
* new_handler - replacement ISR for this vector number
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
*/
|
||||
|
||||
void _CPU_ISR_install_vector(
|
||||
unsigned32 vector,
|
||||
proc_ptr new_handler,
|
||||
proc_ptr *old_handler
|
||||
)
|
||||
{
|
||||
proc_ptr ignored;
|
||||
*old_handler = _ISR_Vector_table[ vector ];
|
||||
|
||||
/*
|
||||
* If the interrupt vector table is a table of pointer to isr entry
|
||||
* points, then we need to install the appropriate RTEMS interrupt
|
||||
* handler for this vector number.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Install the wrapper so this ISR can be invoked properly.
|
||||
*/
|
||||
if (_CPU_Table.exceptions_in_RAM)
|
||||
_CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
|
||||
|
||||
/*
|
||||
* We put the actual user ISR address in '_ISR_vector_table'. This will
|
||||
* be used by the _ISR_Handler so the user gets control.
|
||||
*/
|
||||
|
||||
_ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
|
||||
_CPU_Table.spurious_handler ?
|
||||
(ISR_Handler_entry)_CPU_Table.spurious_handler :
|
||||
(ISR_Handler_entry)ppc_spurious;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Install_interrupt_stack
|
||||
*/
|
||||
|
||||
void _CPU_Install_interrupt_stack( void )
|
||||
{
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
|
||||
_CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56;
|
||||
#else
|
||||
_CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Handle a spurious interrupt */
|
||||
static void ppc_spurious(int v, CPU_Interrupt_frame *i)
|
||||
{
|
||||
#if 0
|
||||
printf("Spurious interrupt on vector %d from %08.8x\n",
|
||||
v, i->pc);
|
||||
#endif
|
||||
#if defined(ppc403) || defined(ppc405)
|
||||
if (v == PPC_IRQ_EXTERNAL)
|
||||
{
|
||||
register int r = 0;
|
||||
|
||||
asm volatile("mtdcr 0x42, %0" :
|
||||
"=&r" ((r)) : "0" ((r))); /* EXIER */
|
||||
}
|
||||
else if (v == PPC_IRQ_PIT)
|
||||
{
|
||||
register int r = 0x08000000;
|
||||
|
||||
asm volatile("mtspr 0x3d8, %0" :
|
||||
"=&r" ((r)) : "0" ((r))); /* TSR */
|
||||
}
|
||||
else if (v == PPC_IRQ_FIT)
|
||||
{
|
||||
register int r = 0x04000000;
|
||||
|
||||
asm volatile("mtspr 0x3d8, %0" :
|
||||
"=&r" ((r)) : "0" ((r))); /* TSR */
|
||||
}
|
||||
#endif
|
||||
++_CPU_spurious_count;
|
||||
_CPU_last_spurious = v;
|
||||
}
|
||||
|
||||
void _CPU_Fatal_error(unsigned32 _error)
|
||||
{
|
||||
asm volatile ("mr 3, %0" : : "r" ((_error)));
|
||||
asm volatile ("tweq 5,5");
|
||||
asm volatile ("li 0,0; mtmsr 0");
|
||||
while (1) ;
|
||||
}
|
||||
|
||||
#define PPC_SYNCHRONOUS_TRAP_BIT_MASK 0x100
|
||||
#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
|
||||
#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
|
||||
#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
|
||||
|
||||
|
||||
const CPU_Trap_table_entry _CPU_Trap_slot_template = {
|
||||
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
|
||||
#error " Vector install not tested."
|
||||
#if (PPC_HAS_FPU)
|
||||
#error " Vector install not tested."
|
||||
0x9421feb0, /* stwu r1, -(20*4 + 18*8 + IP_END)(r1) */
|
||||
#else
|
||||
#error " Vector install not tested."
|
||||
0x9421ff40, /* stwu r1, -(20*4 + IP_END)(r1) */
|
||||
#endif
|
||||
#else
|
||||
0x9421ff90, /* stwu r1, -(IP_END)(r1) */
|
||||
#endif
|
||||
|
||||
0x90010008, /* stw %r0, IP_0(%r1) */
|
||||
0x38000000, /* li %r0, PPC_IRQ */
|
||||
0x48000002 /* ba PROC (_ISR_Handler) */
|
||||
};
|
||||
|
||||
#if defined(mpc860) || defined(mpc821)
|
||||
const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
|
||||
0x7c0803ac, /* mtlr %r0 */
|
||||
0x81210028, /* lwz %r9, IP_9(%r1) */
|
||||
0x38000000, /* li %r0, PPC_IRQ */
|
||||
0x48000002 /* b PROC (_ISR_Handler) */
|
||||
};
|
||||
#endif /* mpc860 */
|
||||
|
||||
unsigned32 ppc_exception_vector_addr(
|
||||
unsigned32 vector
|
||||
);
|
||||
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_install_raw_handler
|
||||
*
|
||||
* This routine installs the specified handler as a "raw" non-executive
|
||||
* supported trap handler (a.k.a. interrupt service routine).
|
||||
*
|
||||
* Input Parameters:
|
||||
* vector - trap table entry number plus synchronous
|
||||
* vs. asynchronous information
|
||||
* new_handler - address of the handler to be installed
|
||||
* old_handler - pointer to an address of the handler previously installed
|
||||
*
|
||||
* Output Parameters: NONE
|
||||
* *new_handler - address of the handler previously installed
|
||||
*
|
||||
* NOTE:
|
||||
*
|
||||
* This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
|
||||
* Install a software trap handler as an executive interrupt handler
|
||||
* (which is desirable since RTEMS takes care of window and register issues),
|
||||
* then the executive needs to know that the return address is to the trap
|
||||
* rather than the instruction following the trap.
|
||||
*
|
||||
*/
|
||||
|
||||
void _CPU_ISR_install_raw_handler(
|
||||
unsigned32 vector,
|
||||
proc_ptr new_handler,
|
||||
proc_ptr *old_handler
|
||||
)
|
||||
{
|
||||
unsigned32 real_vector;
|
||||
CPU_Trap_table_entry *slot;
|
||||
unsigned32 u32_handler=0;
|
||||
|
||||
/*
|
||||
* Get the "real" trap number for this vector ignoring the synchronous
|
||||
* versus asynchronous indicator included with our vector numbers.
|
||||
*/
|
||||
|
||||
real_vector = vector;
|
||||
|
||||
/*
|
||||
* Get the current base address of the trap table and calculate a pointer
|
||||
* to the slot we are interested in.
|
||||
*/
|
||||
slot = (CPU_Trap_table_entry *)ppc_exception_vector_addr( real_vector );
|
||||
|
||||
/*
|
||||
* Get the address of the old_handler from the trap table.
|
||||
*
|
||||
* NOTE: The old_handler returned will be bogus if it does not follow
|
||||
* the RTEMS model.
|
||||
*/
|
||||
|
||||
#define HIGH_BITS_MASK 0xFFFFFC00
|
||||
#define HIGH_BITS_SHIFT 10
|
||||
#define LOW_BITS_MASK 0x000003FF
|
||||
|
||||
if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
|
||||
/*
|
||||
* Set u32_handler = to target address
|
||||
*/
|
||||
u32_handler = slot->b_Handler & 0x03fffffc;
|
||||
|
||||
/* IMD FIX: sign extend address fragment... */
|
||||
if (u32_handler & 0x02000000) {
|
||||
u32_handler |= 0xfc000000;
|
||||
}
|
||||
|
||||
*old_handler = (proc_ptr) u32_handler;
|
||||
} else
|
||||
/* There are two kinds of handlers for the MPC860. One is the 'standard'
|
||||
* one like above. The other is for the cascaded interrupts from the SIU
|
||||
* and CPM. Therefore we must check for the alternate one if the standard
|
||||
* one is not present
|
||||
*/
|
||||
#if defined(mpc860) || defined(mpc821)
|
||||
if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
|
||||
/*
|
||||
* Set u32_handler = to target address
|
||||
*/
|
||||
u32_handler = slot->b_Handler & 0x03fffffc;
|
||||
*old_handler = (proc_ptr) u32_handler;
|
||||
} else
|
||||
#endif /* mpc860 */
|
||||
|
||||
*old_handler = 0;
|
||||
|
||||
/*
|
||||
* Copy the template to the slot and then fix it.
|
||||
*/
|
||||
#if defined(mpc860) || defined(mpc821)
|
||||
if (vector >= PPC_IRQ_IRQ0)
|
||||
*slot = _CPU_Trap_slot_template_m860;
|
||||
else
|
||||
#endif /* mpc860 */
|
||||
*slot = _CPU_Trap_slot_template;
|
||||
|
||||
u32_handler = (unsigned32) new_handler;
|
||||
|
||||
/*
|
||||
* IMD FIX: insert address fragment only (bits 6..29)
|
||||
* therefore check for proper address range
|
||||
* and remove unwanted bits
|
||||
*/
|
||||
if ((u32_handler & 0xfc000000) == 0xfc000000) {
|
||||
u32_handler &= ~0xfc000000;
|
||||
}
|
||||
else if ((u32_handler & 0xfc000000) != 0x00000000) {
|
||||
_Internal_error_Occurred(INTERNAL_ERROR_CORE,
|
||||
TRUE,
|
||||
u32_handler);
|
||||
}
|
||||
|
||||
slot->b_Handler |= u32_handler;
|
||||
|
||||
slot->li_r0_IRQ |= vector;
|
||||
|
||||
_CPU_Data_Cache_Block_Flush( slot );
|
||||
}
|
||||
|
||||
unsigned32 ppc_exception_vector_addr(
|
||||
unsigned32 vector
|
||||
)
|
||||
{
|
||||
#if (!PPC_HAS_EVPR)
|
||||
unsigned32 Msr;
|
||||
#endif
|
||||
unsigned32 Top = 0;
|
||||
unsigned32 Offset = 0x000;
|
||||
|
||||
#if (PPC_HAS_EXCEPTION_PREFIX)
|
||||
_CPU_MSR_Value ( Msr );
|
||||
if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
|
||||
Top = 0xfff00000;
|
||||
#elif (PPC_HAS_EVPR)
|
||||
asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
|
||||
Top = Top & 0xffff0000;
|
||||
#endif
|
||||
|
||||
switch ( vector ) {
|
||||
case PPC_IRQ_SYSTEM_RESET: /* on 40x aka PPC_IRQ_CRIT */
|
||||
Offset = 0x00100;
|
||||
break;
|
||||
case PPC_IRQ_MCHECK:
|
||||
Offset = 0x00200;
|
||||
break;
|
||||
case PPC_IRQ_PROTECT:
|
||||
Offset = 0x00300;
|
||||
break;
|
||||
case PPC_IRQ_ISI:
|
||||
Offset = 0x00400;
|
||||
break;
|
||||
case PPC_IRQ_EXTERNAL:
|
||||
Offset = 0x00500;
|
||||
break;
|
||||
case PPC_IRQ_ALIGNMENT:
|
||||
Offset = 0x00600;
|
||||
break;
|
||||
case PPC_IRQ_PROGRAM:
|
||||
Offset = 0x00700;
|
||||
break;
|
||||
case PPC_IRQ_NOFP:
|
||||
Offset = 0x00800;
|
||||
break;
|
||||
case PPC_IRQ_DECREMENTER:
|
||||
Offset = 0x00900;
|
||||
break;
|
||||
case PPC_IRQ_RESERVED_A:
|
||||
Offset = 0x00a00;
|
||||
break;
|
||||
case PPC_IRQ_RESERVED_B:
|
||||
Offset = 0x00b00;
|
||||
break;
|
||||
case PPC_IRQ_SCALL:
|
||||
Offset = 0x00c00;
|
||||
break;
|
||||
case PPC_IRQ_TRACE:
|
||||
Offset = 0x00d00;
|
||||
break;
|
||||
case PPC_IRQ_FP_ASST:
|
||||
Offset = 0x00e00;
|
||||
break;
|
||||
|
||||
#if defined(ppc403) || defined(ppc405)
|
||||
|
||||
/* PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
|
||||
case PPC_IRQ_CRIT:
|
||||
Offset = 0x00100;
|
||||
break;
|
||||
*/
|
||||
case PPC_IRQ_PIT:
|
||||
Offset = 0x01000;
|
||||
break;
|
||||
case PPC_IRQ_FIT:
|
||||
Offset = 0x01010;
|
||||
break;
|
||||
case PPC_IRQ_WATCHDOG:
|
||||
Offset = 0x01020;
|
||||
break;
|
||||
case PPC_IRQ_DEBUG:
|
||||
Offset = 0x02000;
|
||||
break;
|
||||
|
||||
#elif defined(ppc601)
|
||||
case PPC_IRQ_TRACE:
|
||||
Offset = 0x02000;
|
||||
break;
|
||||
|
||||
#elif defined(ppc603)
|
||||
case PPC_IRQ_TRANS_MISS:
|
||||
Offset = 0x1000;
|
||||
break;
|
||||
case PPC_IRQ_DATA_LOAD:
|
||||
Offset = 0x1100;
|
||||
break;
|
||||
case PPC_IRQ_DATA_STORE:
|
||||
Offset = 0x1200;
|
||||
break;
|
||||
case PPC_IRQ_ADDR_BRK:
|
||||
Offset = 0x1300;
|
||||
break;
|
||||
case PPC_IRQ_SYS_MGT:
|
||||
Offset = 0x1400;
|
||||
break;
|
||||
|
||||
#elif defined(ppc603e)
|
||||
case PPC_TLB_INST_MISS:
|
||||
Offset = 0x1000;
|
||||
break;
|
||||
case PPC_TLB_LOAD_MISS:
|
||||
Offset = 0x1100;
|
||||
break;
|
||||
case PPC_TLB_STORE_MISS:
|
||||
Offset = 0x1200;
|
||||
break;
|
||||
case PPC_IRQ_ADDRBRK:
|
||||
Offset = 0x1300;
|
||||
break;
|
||||
case PPC_IRQ_SYS_MGT:
|
||||
Offset = 0x1400;
|
||||
break;
|
||||
|
||||
#elif defined(mpc604)
|
||||
case PPC_IRQ_ADDR_BRK:
|
||||
Offset = 0x1300;
|
||||
break;
|
||||
case PPC_IRQ_SYS_MGT:
|
||||
Offset = 0x1400;
|
||||
break;
|
||||
|
||||
#elif defined(mpc860) || defined(mpc821)
|
||||
case PPC_IRQ_EMULATE:
|
||||
Offset = 0x1000;
|
||||
break;
|
||||
case PPC_IRQ_INST_MISS:
|
||||
Offset = 0x1100;
|
||||
break;
|
||||
case PPC_IRQ_DATA_MISS:
|
||||
Offset = 0x1200;
|
||||
break;
|
||||
case PPC_IRQ_INST_ERR:
|
||||
Offset = 0x1300;
|
||||
break;
|
||||
case PPC_IRQ_DATA_ERR:
|
||||
Offset = 0x1400;
|
||||
break;
|
||||
case PPC_IRQ_DATA_BPNT:
|
||||
Offset = 0x1c00;
|
||||
break;
|
||||
case PPC_IRQ_INST_BPNT:
|
||||
Offset = 0x1d00;
|
||||
break;
|
||||
case PPC_IRQ_IO_BPNT:
|
||||
Offset = 0x1e00;
|
||||
break;
|
||||
case PPC_IRQ_DEV_PORT:
|
||||
Offset = 0x1f00;
|
||||
break;
|
||||
case PPC_IRQ_IRQ0:
|
||||
Offset = 0x2000;
|
||||
break;
|
||||
case PPC_IRQ_LVL0:
|
||||
Offset = 0x2040;
|
||||
break;
|
||||
case PPC_IRQ_IRQ1:
|
||||
Offset = 0x2080;
|
||||
break;
|
||||
case PPC_IRQ_LVL1:
|
||||
Offset = 0x20c0;
|
||||
break;
|
||||
case PPC_IRQ_IRQ2:
|
||||
Offset = 0x2100;
|
||||
break;
|
||||
case PPC_IRQ_LVL2:
|
||||
Offset = 0x2140;
|
||||
break;
|
||||
case PPC_IRQ_IRQ3:
|
||||
Offset = 0x2180;
|
||||
break;
|
||||
case PPC_IRQ_LVL3:
|
||||
Offset = 0x21c0;
|
||||
break;
|
||||
case PPC_IRQ_IRQ4:
|
||||
Offset = 0x2200;
|
||||
break;
|
||||
case PPC_IRQ_LVL4:
|
||||
Offset = 0x2240;
|
||||
break;
|
||||
case PPC_IRQ_IRQ5:
|
||||
Offset = 0x2280;
|
||||
break;
|
||||
case PPC_IRQ_LVL5:
|
||||
Offset = 0x22c0;
|
||||
break;
|
||||
case PPC_IRQ_IRQ6:
|
||||
Offset = 0x2300;
|
||||
break;
|
||||
case PPC_IRQ_LVL6:
|
||||
Offset = 0x2340;
|
||||
break;
|
||||
case PPC_IRQ_IRQ7:
|
||||
Offset = 0x2380;
|
||||
break;
|
||||
case PPC_IRQ_LVL7:
|
||||
Offset = 0x23c0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_ERROR:
|
||||
Offset = 0x2400;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC4:
|
||||
Offset = 0x2410;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC5:
|
||||
Offset = 0x2420;
|
||||
break;
|
||||
case PPC_IRQ_CPM_SMC2:
|
||||
Offset = 0x2430;
|
||||
break;
|
||||
case PPC_IRQ_CPM_SMC1:
|
||||
Offset = 0x2440;
|
||||
break;
|
||||
case PPC_IRQ_CPM_SPI:
|
||||
Offset = 0x2450;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC6:
|
||||
Offset = 0x2460;
|
||||
break;
|
||||
case PPC_IRQ_CPM_TIMER4:
|
||||
Offset = 0x2470;
|
||||
break;
|
||||
case PPC_IRQ_CPM_RESERVED_8:
|
||||
Offset = 0x2480;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC7:
|
||||
Offset = 0x2490;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC8:
|
||||
Offset = 0x24a0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC9:
|
||||
Offset = 0x24b0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_TIMER3:
|
||||
Offset = 0x24c0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_RESERVED_D:
|
||||
Offset = 0x24d0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC10:
|
||||
Offset = 0x24e0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC11:
|
||||
Offset = 0x24f0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_I2C:
|
||||
Offset = 0x2500;
|
||||
break;
|
||||
case PPC_IRQ_CPM_RISC_TIMER:
|
||||
Offset = 0x2510;
|
||||
break;
|
||||
case PPC_IRQ_CPM_TIMER2:
|
||||
Offset = 0x2520;
|
||||
break;
|
||||
case PPC_IRQ_CPM_RESERVED_13:
|
||||
Offset = 0x2530;
|
||||
break;
|
||||
case PPC_IRQ_CPM_IDMA2:
|
||||
Offset = 0x2540;
|
||||
break;
|
||||
case PPC_IRQ_CPM_IDMA1:
|
||||
Offset = 0x2550;
|
||||
break;
|
||||
case PPC_IRQ_CPM_SDMA_ERROR:
|
||||
Offset = 0x2560;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC12:
|
||||
Offset = 0x2570;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC13:
|
||||
Offset = 0x2580;
|
||||
break;
|
||||
case PPC_IRQ_CPM_TIMER1:
|
||||
Offset = 0x2590;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC14:
|
||||
Offset = 0x25a0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_SCC4:
|
||||
Offset = 0x25b0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_SCC3:
|
||||
Offset = 0x25c0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_SCC2:
|
||||
Offset = 0x25d0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_SCC1:
|
||||
Offset = 0x25e0;
|
||||
break;
|
||||
case PPC_IRQ_CPM_PC15:
|
||||
Offset = 0x25f0;
|
||||
break;
|
||||
#endif
|
||||
|
||||
}
|
||||
Top += Offset;
|
||||
return Top;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* This is the PowerPC specific implementation of the routine which
|
||||
* returns TRUE if an interrupt is in progress.
|
||||
*
|
||||
* NOTE: This is the same as the generic version. But since the
|
||||
* PowerPC is still supporting old and new exception processing
|
||||
* models and the new exception processing model has a hardware
|
||||
* way of doing this, we have to provide this capability here
|
||||
* for symmetry.
|
||||
*/
|
||||
|
||||
boolean _ISR_Is_in_progress( void )
|
||||
{
|
||||
return (_ISR_Nest_level != 0);
|
||||
}
|
||||
@@ -1,653 +0,0 @@
|
||||
|
||||
/* cpu_asm.s 1.1 - 95/12/04
|
||||
*
|
||||
* This file contains the assembly code for the PowerPC implementation
|
||||
* of RTEMS.
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
/*
|
||||
* FIXME: This file is bsp-dependent.
|
||||
*/
|
||||
#include <bspopts.h>
|
||||
|
||||
#include <asm.h>
|
||||
#include <rtems/score/ppc_offs.h>
|
||||
|
||||
BEGIN_CODE
|
||||
/*
|
||||
* _CPU_Context_save_fp_context
|
||||
*
|
||||
* This routine is responsible for saving the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* Sometimes a macro implementation of this is in cpu.h which dereferences
|
||||
* the ** and a similarly named routine in this file is passed something
|
||||
* like a (Context_Control_fp *). The general rule on making this decision
|
||||
* is to avoid writing assembly language.
|
||||
*/
|
||||
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_save_fp)
|
||||
PROC (_CPU_Context_save_fp):
|
||||
#if (PPC_HAS_FPU == 1)
|
||||
lwz r3, 0(r3)
|
||||
#if (PPC_HAS_DOUBLE == 1)
|
||||
stfd f0, FP_0(r3)
|
||||
stfd f1, FP_1(r3)
|
||||
stfd f2, FP_2(r3)
|
||||
stfd f3, FP_3(r3)
|
||||
stfd f4, FP_4(r3)
|
||||
stfd f5, FP_5(r3)
|
||||
stfd f6, FP_6(r3)
|
||||
stfd f7, FP_7(r3)
|
||||
stfd f8, FP_8(r3)
|
||||
stfd f9, FP_9(r3)
|
||||
stfd f10, FP_10(r3)
|
||||
stfd f11, FP_11(r3)
|
||||
stfd f12, FP_12(r3)
|
||||
stfd f13, FP_13(r3)
|
||||
stfd f14, FP_14(r3)
|
||||
stfd f15, FP_15(r3)
|
||||
stfd f16, FP_16(r3)
|
||||
stfd f17, FP_17(r3)
|
||||
stfd f18, FP_18(r3)
|
||||
stfd f19, FP_19(r3)
|
||||
stfd f20, FP_20(r3)
|
||||
stfd f21, FP_21(r3)
|
||||
stfd f22, FP_22(r3)
|
||||
stfd f23, FP_23(r3)
|
||||
stfd f24, FP_24(r3)
|
||||
stfd f25, FP_25(r3)
|
||||
stfd f26, FP_26(r3)
|
||||
stfd f27, FP_27(r3)
|
||||
stfd f28, FP_28(r3)
|
||||
stfd f29, FP_29(r3)
|
||||
stfd f30, FP_30(r3)
|
||||
stfd f31, FP_31(r3)
|
||||
mffs f2
|
||||
stfd f2, FP_FPSCR(r3)
|
||||
#else
|
||||
stfs f0, FP_0(r3)
|
||||
stfs f1, FP_1(r3)
|
||||
stfs f2, FP_2(r3)
|
||||
stfs f3, FP_3(r3)
|
||||
stfs f4, FP_4(r3)
|
||||
stfs f5, FP_5(r3)
|
||||
stfs f6, FP_6(r3)
|
||||
stfs f7, FP_7(r3)
|
||||
stfs f8, FP_8(r3)
|
||||
stfs f9, FP_9(r3)
|
||||
stfs f10, FP_10(r3)
|
||||
stfs f11, FP_11(r3)
|
||||
stfs f12, FP_12(r3)
|
||||
stfs f13, FP_13(r3)
|
||||
stfs f14, FP_14(r3)
|
||||
stfs f15, FP_15(r3)
|
||||
stfs f16, FP_16(r3)
|
||||
stfs f17, FP_17(r3)
|
||||
stfs f18, FP_18(r3)
|
||||
stfs f19, FP_19(r3)
|
||||
stfs f20, FP_20(r3)
|
||||
stfs f21, FP_21(r3)
|
||||
stfs f22, FP_22(r3)
|
||||
stfs f23, FP_23(r3)
|
||||
stfs f24, FP_24(r3)
|
||||
stfs f25, FP_25(r3)
|
||||
stfs f26, FP_26(r3)
|
||||
stfs f27, FP_27(r3)
|
||||
stfs f28, FP_28(r3)
|
||||
stfs f29, FP_29(r3)
|
||||
stfs f30, FP_30(r3)
|
||||
stfs f31, FP_31(r3)
|
||||
mffs f2
|
||||
stfs f2, FP_FPSCR(r3)
|
||||
#endif
|
||||
#endif
|
||||
blr
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore_fp_context
|
||||
*
|
||||
* This routine is responsible for restoring the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* Sometimes a macro implementation of this is in cpu.h which dereferences
|
||||
* the ** and a similarly named routine in this file is passed something
|
||||
* like a (Context_Control_fp *). The general rule on making this decision
|
||||
* is to avoid writing assembly language.
|
||||
*/
|
||||
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_restore_fp)
|
||||
PROC (_CPU_Context_restore_fp):
|
||||
#if (PPC_HAS_FPU == 1)
|
||||
lwz r3, 0(r3)
|
||||
#if (PPC_HAS_DOUBLE == 1)
|
||||
lfd f2, FP_FPSCR(r3)
|
||||
mtfsf 255, f2
|
||||
lfd f0, FP_0(r3)
|
||||
lfd f1, FP_1(r3)
|
||||
lfd f2, FP_2(r3)
|
||||
lfd f3, FP_3(r3)
|
||||
lfd f4, FP_4(r3)
|
||||
lfd f5, FP_5(r3)
|
||||
lfd f6, FP_6(r3)
|
||||
lfd f7, FP_7(r3)
|
||||
lfd f8, FP_8(r3)
|
||||
lfd f9, FP_9(r3)
|
||||
lfd f10, FP_10(r3)
|
||||
lfd f11, FP_11(r3)
|
||||
lfd f12, FP_12(r3)
|
||||
lfd f13, FP_13(r3)
|
||||
lfd f14, FP_14(r3)
|
||||
lfd f15, FP_15(r3)
|
||||
lfd f16, FP_16(r3)
|
||||
lfd f17, FP_17(r3)
|
||||
lfd f18, FP_18(r3)
|
||||
lfd f19, FP_19(r3)
|
||||
lfd f20, FP_20(r3)
|
||||
lfd f21, FP_21(r3)
|
||||
lfd f22, FP_22(r3)
|
||||
lfd f23, FP_23(r3)
|
||||
lfd f24, FP_24(r3)
|
||||
lfd f25, FP_25(r3)
|
||||
lfd f26, FP_26(r3)
|
||||
lfd f27, FP_27(r3)
|
||||
lfd f28, FP_28(r3)
|
||||
lfd f29, FP_29(r3)
|
||||
lfd f30, FP_30(r3)
|
||||
lfd f31, FP_31(r3)
|
||||
#else
|
||||
lfs f2, FP_FPSCR(r3)
|
||||
mtfsf 255, f2
|
||||
lfs f0, FP_0(r3)
|
||||
lfs f1, FP_1(r3)
|
||||
lfs f2, FP_2(r3)
|
||||
lfs f3, FP_3(r3)
|
||||
lfs f4, FP_4(r3)
|
||||
lfs f5, FP_5(r3)
|
||||
lfs f6, FP_6(r3)
|
||||
lfs f7, FP_7(r3)
|
||||
lfs f8, FP_8(r3)
|
||||
lfs f9, FP_9(r3)
|
||||
lfs f10, FP_10(r3)
|
||||
lfs f11, FP_11(r3)
|
||||
lfs f12, FP_12(r3)
|
||||
lfs f13, FP_13(r3)
|
||||
lfs f14, FP_14(r3)
|
||||
lfs f15, FP_15(r3)
|
||||
lfs f16, FP_16(r3)
|
||||
lfs f17, FP_17(r3)
|
||||
lfs f18, FP_18(r3)
|
||||
lfs f19, FP_19(r3)
|
||||
lfs f20, FP_20(r3)
|
||||
lfs f21, FP_21(r3)
|
||||
lfs f22, FP_22(r3)
|
||||
lfs f23, FP_23(r3)
|
||||
lfs f24, FP_24(r3)
|
||||
lfs f25, FP_25(r3)
|
||||
lfs f26, FP_26(r3)
|
||||
lfs f27, FP_27(r3)
|
||||
lfs f28, FP_28(r3)
|
||||
lfs f29, FP_29(r3)
|
||||
lfs f30, FP_30(r3)
|
||||
lfs f31, FP_31(r3)
|
||||
#endif
|
||||
#endif
|
||||
blr
|
||||
|
||||
|
||||
/* _CPU_Context_switch
|
||||
*
|
||||
* This routine performs a normal non-FP context switch.
|
||||
*/
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_switch)
|
||||
PROC (_CPU_Context_switch):
|
||||
sync
|
||||
isync
|
||||
#if (PPC_CACHE_ALIGNMENT == 4) /* No cache */
|
||||
stw r1, GP_1(r3)
|
||||
lwz r1, GP_1(r4)
|
||||
stw r2, GP_2(r3)
|
||||
lwz r2, GP_2(r4)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
stmw r13, GP_13(r3)
|
||||
lmw r13, GP_13(r4)
|
||||
#else
|
||||
stw r13, GP_13(r3)
|
||||
lwz r13, GP_13(r4)
|
||||
stw r14, GP_14(r3)
|
||||
lwz r14, GP_14(r4)
|
||||
stw r15, GP_15(r3)
|
||||
lwz r15, GP_15(r4)
|
||||
stw r16, GP_16(r3)
|
||||
lwz r16, GP_16(r4)
|
||||
stw r17, GP_17(r3)
|
||||
lwz r17, GP_17(r4)
|
||||
stw r18, GP_18(r3)
|
||||
lwz r18, GP_18(r4)
|
||||
stw r19, GP_19(r3)
|
||||
lwz r19, GP_19(r4)
|
||||
stw r20, GP_20(r3)
|
||||
lwz r20, GP_20(r4)
|
||||
stw r21, GP_21(r3)
|
||||
lwz r21, GP_21(r4)
|
||||
stw r22, GP_22(r3)
|
||||
lwz r22, GP_22(r4)
|
||||
stw r23, GP_23(r3)
|
||||
lwz r23, GP_23(r4)
|
||||
stw r24, GP_24(r3)
|
||||
lwz r24, GP_24(r4)
|
||||
stw r25, GP_25(r3)
|
||||
lwz r25, GP_25(r4)
|
||||
stw r26, GP_26(r3)
|
||||
lwz r26, GP_26(r4)
|
||||
stw r27, GP_27(r3)
|
||||
lwz r27, GP_27(r4)
|
||||
stw r28, GP_28(r3)
|
||||
lwz r28, GP_28(r4)
|
||||
stw r29, GP_29(r3)
|
||||
lwz r29, GP_29(r4)
|
||||
stw r30, GP_30(r3)
|
||||
lwz r30, GP_30(r4)
|
||||
stw r31, GP_31(r3)
|
||||
lwz r31, GP_31(r4)
|
||||
#endif
|
||||
mfcr r5
|
||||
stw r5, GP_CR(r3)
|
||||
lwz r5, GP_CR(r4)
|
||||
mflr r6
|
||||
mtcrf 255, r5
|
||||
stw r6, GP_PC(r3)
|
||||
lwz r6, GP_PC(r4)
|
||||
mfmsr r7
|
||||
mtlr r6
|
||||
stw r7, GP_MSR(r3)
|
||||
lwz r7, GP_MSR(r4)
|
||||
mtmsr r7
|
||||
#endif
|
||||
#if (PPC_CACHE_ALIGNMENT == 16)
|
||||
/* This assumes that all the registers are in the given order */
|
||||
li r5, 16
|
||||
addi r3,r3,-4
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r1, GP_1+4(r3)
|
||||
stw r2, GP_2+4(r3)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
addi r3, r3, GP_14+4
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
|
||||
addi r3, r3, GP_18-GP_14
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
addi r3, r3, GP_22-GP_18
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
addi r3, r3, GP_26-GP_22
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stmw r13, GP_13-GP_26(r3)
|
||||
#else
|
||||
stw r13, GP_13+4(r3)
|
||||
stwu r14, GP_14+4(r3)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r15, GP_15-GP_14(r3)
|
||||
stw r16, GP_16-GP_14(r3)
|
||||
stw r17, GP_17-GP_14(r3)
|
||||
stwu r18, GP_18-GP_14(r3)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r19, GP_19-GP_18(r3)
|
||||
stw r20, GP_20-GP_18(r3)
|
||||
stw r21, GP_21-GP_18(r3)
|
||||
stwu r22, GP_22-GP_18(r3)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r23, GP_23-GP_22(r3)
|
||||
stw r24, GP_24-GP_22(r3)
|
||||
stw r25, GP_25-GP_22(r3)
|
||||
stwu r26, GP_26-GP_22(r3)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r27, GP_27-GP_26(r3)
|
||||
stw r28, GP_28-GP_26(r3)
|
||||
stw r29, GP_29-GP_26(r3)
|
||||
stw r30, GP_30-GP_26(r3)
|
||||
stw r31, GP_31-GP_26(r3)
|
||||
#endif
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r0, r4
|
||||
#endif
|
||||
mfcr r6
|
||||
stw r6, GP_CR-GP_26(r3)
|
||||
mflr r7
|
||||
stw r7, GP_PC-GP_26(r3)
|
||||
mfmsr r8
|
||||
stw r8, GP_MSR-GP_26(r3)
|
||||
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r1, GP_1(r4)
|
||||
lwz r2, GP_2(r4)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
addi r4, r4, GP_15
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
addi r4, r4, GP_19-GP_15
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
addi r4, r4, GP_23-GP_19
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
addi r4, r4, GP_27-GP_23
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lmw r13, GP_13-GP_27(r4)
|
||||
#else
|
||||
lwz r13, GP_13(r4)
|
||||
lwz r14, GP_14(r4)
|
||||
lwzu r15, GP_15(r4)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r16, GP_16-GP_15(r4)
|
||||
lwz r17, GP_17-GP_15(r4)
|
||||
lwz r18, GP_18-GP_15(r4)
|
||||
lwzu r19, GP_19-GP_15(r4)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r20, GP_20-GP_19(r4)
|
||||
lwz r21, GP_21-GP_19(r4)
|
||||
lwz r22, GP_22-GP_19(r4)
|
||||
lwzu r23, GP_23-GP_19(r4)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r24, GP_24-GP_23(r4)
|
||||
lwz r25, GP_25-GP_23(r4)
|
||||
lwz r26, GP_26-GP_23(r4)
|
||||
lwzu r27, GP_27-GP_23(r4)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r28, GP_28-GP_27(r4)
|
||||
lwz r29, GP_29-GP_27(r4)
|
||||
lwz r30, GP_30-GP_27(r4)
|
||||
lwz r31, GP_31-GP_27(r4)
|
||||
#endif
|
||||
lwz r6, GP_CR-GP_27(r4)
|
||||
lwz r7, GP_PC-GP_27(r4)
|
||||
lwz r8, GP_MSR-GP_27(r4)
|
||||
mtcrf 255, r6
|
||||
mtlr r7
|
||||
mtmsr r8
|
||||
#endif
|
||||
#if (PPC_CACHE_ALIGNMENT == 32)
|
||||
/* This assumes that all the registers are in the given order */
|
||||
li r5, 32
|
||||
addi r3,r3,-4
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r1, GP_1+4(r3)
|
||||
stw r2, GP_2+4(r3)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
addi r3, r3, GP_18+4
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stmw r13, GP_13-GP_18(r3)
|
||||
#else
|
||||
stw r13, GP_13+4(r3)
|
||||
stw r14, GP_14+4(r3)
|
||||
stw r15, GP_15+4(r3)
|
||||
stw r16, GP_16+4(r3)
|
||||
stw r17, GP_17+4(r3)
|
||||
stwu r18, GP_18+4(r3)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r19, GP_19-GP_18(r3)
|
||||
stw r20, GP_20-GP_18(r3)
|
||||
stw r21, GP_21-GP_18(r3)
|
||||
stw r22, GP_22-GP_18(r3)
|
||||
stw r23, GP_23-GP_18(r3)
|
||||
stw r24, GP_24-GP_18(r3)
|
||||
stw r25, GP_25-GP_18(r3)
|
||||
stw r26, GP_26-GP_18(r3)
|
||||
stw r27, GP_27-GP_18(r3)
|
||||
stw r28, GP_28-GP_18(r3)
|
||||
stw r29, GP_29-GP_18(r3)
|
||||
stw r30, GP_30-GP_18(r3)
|
||||
stw r31, GP_31-GP_18(r3)
|
||||
#endif
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r0, r4
|
||||
#endif
|
||||
mfcr r6
|
||||
stw r6, GP_CR-GP_18(r3)
|
||||
mflr r7
|
||||
stw r7, GP_PC-GP_18(r3)
|
||||
mfmsr r8
|
||||
stw r8, GP_MSR-GP_18(r3)
|
||||
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r1, GP_1(r4)
|
||||
lwz r2, GP_2(r4)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
addi r4, r4, GP_19
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lmw r13, GP_13-GP_19(r4)
|
||||
#else
|
||||
lwz r13, GP_13(r4)
|
||||
lwz r14, GP_14(r4)
|
||||
lwz r15, GP_15(r4)
|
||||
lwz r16, GP_16(r4)
|
||||
lwz r17, GP_17(r4)
|
||||
lwz r18, GP_18(r4)
|
||||
lwzu r19, GP_19(r4)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r20, GP_20-GP_19(r4)
|
||||
lwz r21, GP_21-GP_19(r4)
|
||||
lwz r22, GP_22-GP_19(r4)
|
||||
lwz r23, GP_23-GP_19(r4)
|
||||
lwz r24, GP_24-GP_19(r4)
|
||||
lwz r25, GP_25-GP_19(r4)
|
||||
lwz r26, GP_26-GP_19(r4)
|
||||
lwz r27, GP_27-GP_19(r4)
|
||||
lwz r28, GP_28-GP_19(r4)
|
||||
lwz r29, GP_29-GP_19(r4)
|
||||
lwz r30, GP_30-GP_19(r4)
|
||||
lwz r31, GP_31-GP_19(r4)
|
||||
#endif
|
||||
lwz r6, GP_CR-GP_19(r4)
|
||||
lwz r7, GP_PC-GP_19(r4)
|
||||
lwz r8, GP_MSR-GP_19(r4)
|
||||
mtcrf 255, r6
|
||||
mtlr r7
|
||||
mtmsr r8
|
||||
#endif
|
||||
blr
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore
|
||||
*
|
||||
* This routine is generallu used only to restart self in an
|
||||
* efficient manner. It may simply be a label in _CPU_Context_switch.
|
||||
*
|
||||
* NOTE: May be unnecessary to reload some registers.
|
||||
*/
|
||||
/*
|
||||
* ACB: Don't worry about cache optimisation here - this is not THAT critical.
|
||||
*/
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_restore)
|
||||
PROC (_CPU_Context_restore):
|
||||
lwz r5, GP_CR(r3)
|
||||
lwz r6, GP_PC(r3)
|
||||
lwz r7, GP_MSR(r3)
|
||||
mtcrf 255, r5
|
||||
mtlr r6
|
||||
mtmsr r7
|
||||
lwz r1, GP_1(r3)
|
||||
lwz r2, GP_2(r3)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
lmw r13, GP_13(r3)
|
||||
#else
|
||||
lwz r13, GP_13(r3)
|
||||
lwz r14, GP_14(r3)
|
||||
lwz r15, GP_15(r3)
|
||||
lwz r16, GP_16(r3)
|
||||
lwz r17, GP_17(r3)
|
||||
lwz r18, GP_18(r3)
|
||||
lwz r19, GP_19(r3)
|
||||
lwz r20, GP_20(r3)
|
||||
lwz r21, GP_21(r3)
|
||||
lwz r22, GP_22(r3)
|
||||
lwz r23, GP_23(r3)
|
||||
lwz r24, GP_24(r3)
|
||||
lwz r25, GP_25(r3)
|
||||
lwz r26, GP_26(r3)
|
||||
lwz r27, GP_27(r3)
|
||||
lwz r28, GP_28(r3)
|
||||
lwz r29, GP_29(r3)
|
||||
lwz r30, GP_30(r3)
|
||||
lwz r31, GP_31(r3)
|
||||
#endif
|
||||
|
||||
blr
|
||||
|
||||
/* Individual interrupt prologues look like this:
|
||||
* #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
|
||||
* #if (PPC_HAS_FPU)
|
||||
* stwu r1, -(20*4 + 18*8 + IP_END)(r1)
|
||||
* #else
|
||||
* stwu r1, -(20*4 + IP_END)(r1)
|
||||
* #endif
|
||||
* #else
|
||||
* stwu r1, -(IP_END)(r1)
|
||||
* #endif
|
||||
* stw r0, IP_0(r1)
|
||||
*
|
||||
* li r0, vectornum
|
||||
* b PROC (_ISR_Handler{,C})
|
||||
*/
|
||||
|
||||
/* void __ISR_Handler()
|
||||
*
|
||||
* This routine provides the RTEMS interrupt management.
|
||||
* The vector number is in r0. R0 has already been stacked.
|
||||
*
|
||||
*/
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_ISR_Handler)
|
||||
PROC (_ISR_Handler):
|
||||
#define LABEL(x) x
|
||||
/* XXX ??
|
||||
#define MTSAVE(x) mtspr sprg0, x
|
||||
#define MFSAVE(x) mfspr x, sprg0
|
||||
*/
|
||||
#define MTPC(x) mtspr srr0, x
|
||||
#define MFPC(x) mfspr x, srr0
|
||||
#define MTMSR(x) mtspr srr1, x
|
||||
#define MFMSR(x) mfspr x, srr1
|
||||
|
||||
#include "irq_stub.S"
|
||||
rfi
|
||||
|
||||
#if (PPC_HAS_RFCI == 1)
|
||||
/* void __ISR_HandlerC()
|
||||
*
|
||||
* This routine provides the RTEMS interrupt management.
|
||||
* For critical interrupts
|
||||
*
|
||||
*/
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_ISR_HandlerC)
|
||||
PROC (_ISR_HandlerC):
|
||||
#undef LABEL
|
||||
#undef MTSAVE
|
||||
#undef MFSAVE
|
||||
#undef MTPC
|
||||
#undef MFPC
|
||||
#undef MTMSR
|
||||
#undef MFMSR
|
||||
#define LABEL(x) x##_C
|
||||
/* XXX??
|
||||
#define MTSAVE(x) mtspr sprg1, x
|
||||
#define MFSAVE(x) mfspr x, sprg1
|
||||
*/
|
||||
#define MTPC(x) mtspr srr2, x
|
||||
#define MFPC(x) mfspr x, srr2
|
||||
#define MTMSR(x) mtspr srr3, x
|
||||
#define MFMSR(x) mfspr x, srr3
|
||||
#include "irq_stub.S"
|
||||
rfci
|
||||
#endif
|
||||
|
||||
/* PowerOpen descriptors for indirect function calls.
|
||||
*/
|
||||
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
DESCRIPTOR (_CPU_Context_save_fp)
|
||||
DESCRIPTOR (_CPU_Context_restore_fp)
|
||||
DESCRIPTOR (_CPU_Context_switch)
|
||||
DESCRIPTOR (_CPU_Context_restore)
|
||||
DESCRIPTOR (_ISR_Handler)
|
||||
#if (PPC_HAS_RFCI == 1)
|
||||
DESCRIPTOR (_ISR_HandlerC)
|
||||
#endif
|
||||
#endif
|
||||
@@ -1,275 +0,0 @@
|
||||
/*
|
||||
* This file contains the interrupt handler assembly code for the PowerPC
|
||||
* implementation of RTEMS. It is #included from cpu_asm.s.
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
/*
|
||||
* FIXME: this file is bsp dependent.
|
||||
*/
|
||||
#include <bspopts.h>
|
||||
|
||||
/* void __ISR_Handler()
|
||||
*
|
||||
* This routine provides the RTEMS interrupt management.
|
||||
* The vector number is in r0. R0 has already been stacked.
|
||||
*
|
||||
*/
|
||||
PUBLIC_VAR (_CPU_IRQ_info )
|
||||
|
||||
/* Finish off the interrupt frame */
|
||||
stw r2, IP_2(r1)
|
||||
stw r3, IP_3(r1)
|
||||
stw r4, IP_4(r1)
|
||||
stw r5, IP_5(r1)
|
||||
stw r6, IP_6(r1)
|
||||
stw r7, IP_7(r1)
|
||||
stw r8, IP_8(r1)
|
||||
stw r9, IP_9(r1)
|
||||
stw r10, IP_10(r1)
|
||||
stw r11, IP_11(r1)
|
||||
stw r12, IP_12(r1)
|
||||
stw r13, IP_13(r1)
|
||||
stmw r28, IP_28(r1)
|
||||
mfcr r5
|
||||
mfctr r6
|
||||
mfxer r7
|
||||
mflr r8
|
||||
MFPC (r9)
|
||||
MFMSR (r10)
|
||||
/* Establish addressing */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfspr r11, sprg3
|
||||
#else
|
||||
lis r11,_CPU_IRQ_info@ha
|
||||
addi r11,r11,_CPU_IRQ_info@l
|
||||
#endif
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r0, r11
|
||||
#endif
|
||||
stw r5, IP_CR(r1)
|
||||
stw r6, IP_CTR(r1)
|
||||
stw r7, IP_XER(r1)
|
||||
stw r8, IP_LR(r1)
|
||||
stw r9, IP_PC(r1)
|
||||
stw r10, IP_MSR(r1)
|
||||
|
||||
lwz r30, Vector_table(r11)
|
||||
slwi r4,r0,2
|
||||
lwz r28, Nest_level(r11)
|
||||
add r4, r4, r30
|
||||
|
||||
lwz r30, 0(r28)
|
||||
mr r3, r0
|
||||
lwz r31, Stack(r11)
|
||||
/*
|
||||
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
|
||||
* if ( _ISR_Nest_level == 0 )
|
||||
* switch to software interrupt stack
|
||||
* #endif
|
||||
*/
|
||||
/* Switch stacks, here we must prevent ALL interrupts */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfmsr r5
|
||||
mfspr r6, sprg2
|
||||
#else
|
||||
lwz r6,msr_initial(r11)
|
||||
lis r5,~PPC_MSR_DISABLE_MASK@ha
|
||||
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
|
||||
and r6,r6,r5
|
||||
mfmsr r5
|
||||
#endif
|
||||
mtmsr r6
|
||||
cmpwi r30, 0
|
||||
lwz r29, Disable_level(r11)
|
||||
subf r31,r1,r31
|
||||
bne LABEL (nested)
|
||||
stwux r1,r1,r31
|
||||
LABEL (nested):
|
||||
/*
|
||||
* _ISR_Nest_level++;
|
||||
*/
|
||||
lwz r31, 0(r29)
|
||||
addi r30,r30,1
|
||||
stw r30,0(r28)
|
||||
/* From here on out, interrupts can be re-enabled. RTEMS
|
||||
* convention says not.
|
||||
*/
|
||||
lwz r4,0(r4)
|
||||
/*
|
||||
* _Thread_Dispatch_disable_level++;
|
||||
*/
|
||||
addi r31,r31,1
|
||||
stw r31, 0(r29)
|
||||
/* SCE 980217
|
||||
*
|
||||
* We need address translation ON when we call our ISR routine
|
||||
|
||||
mtmsr r5
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* (*_ISR_Vector_table[ vector ])( vector );
|
||||
*/
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
lwz r6,0(r4)
|
||||
lwz r2,4(r4)
|
||||
mtlr r6
|
||||
lwz r11,8(r4)
|
||||
#endif
|
||||
#if (PPC_ABI == PPC_ABI_GCC27)
|
||||
lwz r2, Default_r2(r11)
|
||||
mtlr r4
|
||||
#lwz r2, 0(r2)
|
||||
#endif
|
||||
#if (PPC_ABI == PPC_ABI_SVR4 || PPC_ABI == PPC_ABI_EABI)
|
||||
mtlr r4
|
||||
lwz r2, Default_r2(r11)
|
||||
lwz r13, Default_r13(r11)
|
||||
#lwz r2, 0(r2)
|
||||
#lwz r13, 0(r13)
|
||||
#endif
|
||||
mr r4,r1
|
||||
blrl
|
||||
/* NOP marker for debuggers */
|
||||
or r6,r6,r6
|
||||
|
||||
/* We must re-disable the interrupts */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfspr r11, sprg3
|
||||
mfspr r0, sprg2
|
||||
#else
|
||||
lis r11,_CPU_IRQ_info@ha
|
||||
addi r11,r11,_CPU_IRQ_info@l
|
||||
lwz r0,msr_initial(r11)
|
||||
lis r30,~PPC_MSR_DISABLE_MASK@ha
|
||||
ori r30,r30,~PPC_MSR_DISABLE_MASK@l
|
||||
and r0,r0,r30
|
||||
#endif
|
||||
mtmsr r0
|
||||
lwz r30, 0(r28)
|
||||
lwz r31, 0(r29)
|
||||
|
||||
/*
|
||||
* if (--Thread_Dispatch_disable,--_ISR_Nest_level)
|
||||
* goto easy_exit;
|
||||
*/
|
||||
addi r30, r30, -1
|
||||
cmpwi r30, 0
|
||||
addi r31, r31, -1
|
||||
stw r30, 0(r28)
|
||||
stw r31, 0(r29)
|
||||
bne LABEL (easy_exit)
|
||||
cmpwi r31, 0
|
||||
|
||||
lwz r30, Switch_necessary(r11)
|
||||
|
||||
/*
|
||||
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
|
||||
* restore stack
|
||||
* #endif
|
||||
*/
|
||||
lwz r1,0(r1)
|
||||
bne LABEL (easy_exit)
|
||||
lwz r30, 0(r30)
|
||||
lwz r31, Signal(r11)
|
||||
|
||||
/*
|
||||
* if ( _Context_Switch_necessary )
|
||||
* goto switch
|
||||
*/
|
||||
cmpwi r30, 0
|
||||
lwz r28, 0(r31)
|
||||
li r6,0
|
||||
bne LABEL (switch)
|
||||
/*
|
||||
* if ( !_ISR_Signals_to_thread_executing )
|
||||
* goto easy_exit
|
||||
* _ISR_Signals_to_thread_executing = 0;
|
||||
*/
|
||||
cmpwi r28, 0
|
||||
beq LABEL (easy_exit)
|
||||
|
||||
/*
|
||||
* switch:
|
||||
* call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
|
||||
*/
|
||||
LABEL (switch):
|
||||
stw r6, 0(r31)
|
||||
/* Re-enable interrupts */
|
||||
lwz r0, IP_MSR(r1)
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
lwz r2, Dispatch_r2(r11)
|
||||
#else
|
||||
/* R2 and R13 still hold their values from the last call */
|
||||
#endif
|
||||
mtmsr r0
|
||||
bl SYM (_Thread_Dispatch)
|
||||
/* NOP marker for debuggers */
|
||||
or r6,r6,r6
|
||||
/*
|
||||
* prepare to get out of interrupt
|
||||
*/
|
||||
/* Re-disable IRQs */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfspr r0, sprg2
|
||||
#else
|
||||
lis r11,_CPU_IRQ_info@ha
|
||||
addi r11,r11,_CPU_IRQ_info@l
|
||||
lwz r0,msr_initial(r11)
|
||||
lis r5,~PPC_MSR_DISABLE_MASK@ha
|
||||
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
|
||||
and r0,r0,r5
|
||||
#endif
|
||||
mtmsr r0
|
||||
|
||||
/*
|
||||
* easy_exit:
|
||||
* prepare to get out of interrupt
|
||||
* return from interrupt
|
||||
*/
|
||||
LABEL (easy_exit):
|
||||
lwz r5, IP_CR(r1)
|
||||
lwz r6, IP_CTR(r1)
|
||||
lwz r7, IP_XER(r1)
|
||||
lwz r8, IP_LR(r1)
|
||||
lwz r9, IP_PC(r1)
|
||||
lwz r10, IP_MSR(r1)
|
||||
mtcrf 255,r5
|
||||
mtctr r6
|
||||
mtxer r7
|
||||
mtlr r8
|
||||
MTPC (r9)
|
||||
MTMSR (r10)
|
||||
lwz r0, IP_0(r1)
|
||||
lwz r2, IP_2(r1)
|
||||
lwz r3, IP_3(r1)
|
||||
lwz r4, IP_4(r1)
|
||||
lwz r5, IP_5(r1)
|
||||
lwz r6, IP_6(r1)
|
||||
lwz r7, IP_7(r1)
|
||||
lwz r8, IP_8(r1)
|
||||
lwz r9, IP_9(r1)
|
||||
lwz r10, IP_10(r1)
|
||||
lwz r11, IP_11(r1)
|
||||
lwz r12, IP_12(r1)
|
||||
lwz r13, IP_13(r1)
|
||||
lmw r28, IP_28(r1)
|
||||
lwz r1, 0(r1)
|
||||
@@ -1,61 +0,0 @@
|
||||
/*
|
||||
* PowerPC Cache enable routines
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems/system.h>
|
||||
|
||||
#define PPC_Get_HID0( _value ) \
|
||||
do { \
|
||||
_value = 0; /* to avoid warnings */ \
|
||||
asm volatile( \
|
||||
"mfspr %0, 0x3f0;" /* get HID0 */ \
|
||||
"isync" \
|
||||
: "=r" (_value) \
|
||||
: "0" (_value) \
|
||||
); \
|
||||
} while (0)
|
||||
|
||||
#define PPC_Set_HID0( _value ) \
|
||||
do { \
|
||||
asm volatile( \
|
||||
"isync;" \
|
||||
"mtspr 0x3f0, %0;" /* load HID0 */ \
|
||||
"isync" \
|
||||
: "=r" (_value) \
|
||||
: "0" (_value) \
|
||||
); \
|
||||
} while (0)
|
||||
|
||||
|
||||
void powerpc_instruction_cache_enable ()
|
||||
{
|
||||
unsigned32 value;
|
||||
|
||||
/*
|
||||
* Enable the instruction cache
|
||||
*/
|
||||
|
||||
PPC_Get_HID0( value );
|
||||
|
||||
value |= 0x00008000; /* Set ICE bit */
|
||||
|
||||
PPC_Set_HID0( value );
|
||||
}
|
||||
|
||||
void powerpc_data_cache_enable ()
|
||||
{
|
||||
unsigned32 value;
|
||||
|
||||
/*
|
||||
* enable data cache
|
||||
*/
|
||||
|
||||
PPC_Get_HID0( value );
|
||||
|
||||
value |= 0x00004000; /* set DCE bit */
|
||||
|
||||
PPC_Set_HID0( value );
|
||||
}
|
||||
|
||||
@@ -1,166 +0,0 @@
|
||||
/* -*- asm -*- */
|
||||
#ifndef __PPC_OFFS_H
|
||||
#define __PPC_OFFS_H
|
||||
|
||||
/*
|
||||
* Offsets for various Contexts
|
||||
*/
|
||||
.set GP_1, 0
|
||||
.set GP_2, (GP_1 + 4)
|
||||
.set GP_13, (GP_2 + 4)
|
||||
.set GP_14, (GP_13 + 4)
|
||||
|
||||
.set GP_15, (GP_14 + 4)
|
||||
.set GP_16, (GP_15 + 4)
|
||||
.set GP_17, (GP_16 + 4)
|
||||
.set GP_18, (GP_17 + 4)
|
||||
|
||||
.set GP_19, (GP_18 + 4)
|
||||
.set GP_20, (GP_19 + 4)
|
||||
.set GP_21, (GP_20 + 4)
|
||||
.set GP_22, (GP_21 + 4)
|
||||
|
||||
.set GP_23, (GP_22 + 4)
|
||||
.set GP_24, (GP_23 + 4)
|
||||
.set GP_25, (GP_24 + 4)
|
||||
.set GP_26, (GP_25 + 4)
|
||||
|
||||
.set GP_27, (GP_26 + 4)
|
||||
.set GP_28, (GP_27 + 4)
|
||||
.set GP_29, (GP_28 + 4)
|
||||
.set GP_30, (GP_29 + 4)
|
||||
|
||||
.set GP_31, (GP_30 + 4)
|
||||
.set GP_CR, (GP_31 + 4)
|
||||
.set GP_PC, (GP_CR + 4)
|
||||
.set GP_MSR, (GP_PC + 4)
|
||||
|
||||
#if (PPC_HAS_DOUBLE == 1)
|
||||
.set FP_0, 0
|
||||
.set FP_1, (FP_0 + 8)
|
||||
.set FP_2, (FP_1 + 8)
|
||||
.set FP_3, (FP_2 + 8)
|
||||
.set FP_4, (FP_3 + 8)
|
||||
.set FP_5, (FP_4 + 8)
|
||||
.set FP_6, (FP_5 + 8)
|
||||
.set FP_7, (FP_6 + 8)
|
||||
.set FP_8, (FP_7 + 8)
|
||||
.set FP_9, (FP_8 + 8)
|
||||
.set FP_10, (FP_9 + 8)
|
||||
.set FP_11, (FP_10 + 8)
|
||||
.set FP_12, (FP_11 + 8)
|
||||
.set FP_13, (FP_12 + 8)
|
||||
.set FP_14, (FP_13 + 8)
|
||||
.set FP_15, (FP_14 + 8)
|
||||
.set FP_16, (FP_15 + 8)
|
||||
.set FP_17, (FP_16 + 8)
|
||||
.set FP_18, (FP_17 + 8)
|
||||
.set FP_19, (FP_18 + 8)
|
||||
.set FP_20, (FP_19 + 8)
|
||||
.set FP_21, (FP_20 + 8)
|
||||
.set FP_22, (FP_21 + 8)
|
||||
.set FP_23, (FP_22 + 8)
|
||||
.set FP_24, (FP_23 + 8)
|
||||
.set FP_25, (FP_24 + 8)
|
||||
.set FP_26, (FP_25 + 8)
|
||||
.set FP_27, (FP_26 + 8)
|
||||
.set FP_28, (FP_27 + 8)
|
||||
.set FP_29, (FP_28 + 8)
|
||||
.set FP_30, (FP_29 + 8)
|
||||
.set FP_31, (FP_30 + 8)
|
||||
.set FP_FPSCR, (FP_31 + 8)
|
||||
#else
|
||||
.set FP_0, 0
|
||||
.set FP_1, (FP_0 + 4)
|
||||
.set FP_2, (FP_1 + 4)
|
||||
.set FP_3, (FP_2 + 4)
|
||||
.set FP_4, (FP_3 + 4)
|
||||
.set FP_5, (FP_4 + 4)
|
||||
.set FP_6, (FP_5 + 4)
|
||||
.set FP_7, (FP_6 + 4)
|
||||
.set FP_8, (FP_7 + 4)
|
||||
.set FP_9, (FP_8 + 4)
|
||||
.set FP_10, (FP_9 + 4)
|
||||
.set FP_11, (FP_10 + 4)
|
||||
.set FP_12, (FP_11 + 4)
|
||||
.set FP_13, (FP_12 + 4)
|
||||
.set FP_14, (FP_13 + 4)
|
||||
.set FP_15, (FP_14 + 4)
|
||||
.set FP_16, (FP_15 + 4)
|
||||
.set FP_17, (FP_16 + 4)
|
||||
.set FP_18, (FP_17 + 4)
|
||||
.set FP_19, (FP_18 + 4)
|
||||
.set FP_20, (FP_19 + 4)
|
||||
.set FP_21, (FP_20 + 4)
|
||||
.set FP_22, (FP_21 + 4)
|
||||
.set FP_23, (FP_22 + 4)
|
||||
.set FP_24, (FP_23 + 4)
|
||||
.set FP_25, (FP_24 + 4)
|
||||
.set FP_26, (FP_25 + 4)
|
||||
.set FP_27, (FP_26 + 4)
|
||||
.set FP_28, (FP_27 + 4)
|
||||
.set FP_29, (FP_28 + 4)
|
||||
.set FP_30, (FP_29 + 4)
|
||||
.set FP_31, (FP_30 + 4)
|
||||
.set FP_FPSCR, (FP_31 + 4)
|
||||
#endif
|
||||
|
||||
.set IP_LINK, 0
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
|
||||
.set IP_0, (IP_LINK + 56)
|
||||
#else
|
||||
.set IP_0, (IP_LINK + 8)
|
||||
#endif
|
||||
.set IP_2, (IP_0 + 4)
|
||||
|
||||
.set IP_3, (IP_2 + 4)
|
||||
.set IP_4, (IP_3 + 4)
|
||||
.set IP_5, (IP_4 + 4)
|
||||
.set IP_6, (IP_5 + 4)
|
||||
|
||||
.set IP_7, (IP_6 + 4)
|
||||
.set IP_8, (IP_7 + 4)
|
||||
.set IP_9, (IP_8 + 4)
|
||||
.set IP_10, (IP_9 + 4)
|
||||
|
||||
.set IP_11, (IP_10 + 4)
|
||||
.set IP_12, (IP_11 + 4)
|
||||
.set IP_13, (IP_12 + 4)
|
||||
.set IP_28, (IP_13 + 4)
|
||||
|
||||
.set IP_29, (IP_28 + 4)
|
||||
.set IP_30, (IP_29 + 4)
|
||||
.set IP_31, (IP_30 + 4)
|
||||
.set IP_CR, (IP_31 + 4)
|
||||
|
||||
.set IP_CTR, (IP_CR + 4)
|
||||
.set IP_XER, (IP_CTR + 4)
|
||||
.set IP_LR, (IP_XER + 4)
|
||||
.set IP_PC, (IP_LR + 4)
|
||||
|
||||
.set IP_MSR, (IP_PC + 4)
|
||||
.set IP_END, (IP_MSR + 16)
|
||||
|
||||
/* _CPU_IRQ_info offsets */
|
||||
|
||||
/* These must be in this order */
|
||||
.set Nest_level, 0
|
||||
.set Disable_level, 4
|
||||
.set Vector_table, 8
|
||||
.set Stack, 12
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
.set Dispatch_r2, 16
|
||||
.set Switch_necessary, 20
|
||||
#else
|
||||
.set Default_r2, 16
|
||||
#if (PPC_ABI != PPC_ABI_GCC27)
|
||||
.set Default_r13, 20
|
||||
.set Switch_necessary, 24
|
||||
#else
|
||||
.set Switch_necessary, 20
|
||||
#endif
|
||||
#endif
|
||||
.set Signal, Switch_necessary + 4
|
||||
.set msr_initial, Signal + 4
|
||||
|
||||
#endif /* __PPC_OFFS_H */
|
||||
@@ -1,2 +0,0 @@
|
||||
Makefile
|
||||
Makefile.in
|
||||
@@ -1,9 +0,0 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
The mpci.h file provided in here is too simple for an MPCI with
|
||||
multiple ways to get to a node.
|
||||
|
||||
This version of the shm driver needs to be reorganized to follow
|
||||
the better model of the Ada version.
|
||||
@@ -1,42 +0,0 @@
|
||||
/* void Shm_Locked_queue_Add( lq_cb, ecb )
|
||||
*
|
||||
* This routine adds an envelope control block to a shared memory queue.
|
||||
*
|
||||
* Input parameters:
|
||||
* lq_cb - pointer to a locked queue control block
|
||||
* ecb - pointer to an envelope control block
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
void Shm_Locked_queue_Add(
|
||||
Shm_Locked_queue_Control *lq_cb,
|
||||
Shm_Envelope_control *ecb
|
||||
)
|
||||
{
|
||||
rtems_unsigned32 index;
|
||||
|
||||
ecb->next = Shm_Locked_queue_End_of_list;
|
||||
ecb->queue = lq_cb->owner;
|
||||
index = ecb->index;
|
||||
|
||||
Shm_Lock( lq_cb );
|
||||
if ( Shm_Convert(lq_cb->front) != Shm_Locked_queue_End_of_list )
|
||||
Shm_Envelopes[ Shm_Convert(lq_cb->rear) ].next = index;
|
||||
else
|
||||
lq_cb->front = index;
|
||||
lq_cb->rear = index;
|
||||
Shm_Unlock( lq_cb );
|
||||
}
|
||||
@@ -1,41 +0,0 @@
|
||||
/* void Shm_Convert_packet( &packet )
|
||||
*
|
||||
* This routine is the shared memory locked queue MPCI driver routine
|
||||
* used to convert the RTEMS's information in a packet from non-native
|
||||
* format to processor native format.
|
||||
*
|
||||
* Input parameters:
|
||||
* packet - pointer to a packet
|
||||
*
|
||||
* Output parameters:
|
||||
* *packet - packet in native format
|
||||
*
|
||||
* NOTE: Message buffers are not manipulated.
|
||||
* Endian conversion is currently the only conversion.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
void Shm_Convert_packet(
|
||||
rtems_packet_prefix *packet
|
||||
)
|
||||
{
|
||||
rtems_unsigned32 *pkt, i;
|
||||
|
||||
pkt = (rtems_unsigned32 *) packet;
|
||||
for ( i=RTEMS_MINIMUN_HETERO_CONVERSION ; i ; i--, pkt++ )
|
||||
*pkt = CPU_swap_u32( *pkt );
|
||||
|
||||
for ( i=packet->to_convert ; i ; i--, pkt++ )
|
||||
*pkt = CPU_swap_u32( *pkt );
|
||||
}
|
||||
@@ -1,50 +0,0 @@
|
||||
/*
|
||||
* This routine is invoked following a reset to report the statistics
|
||||
* gathered during the previous execution.
|
||||
*
|
||||
* Input parameters: NONE
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "shm_driver.h"
|
||||
|
||||
void
|
||||
Shm_Print_statistics(void)
|
||||
{
|
||||
rtems_unsigned32 ticks;
|
||||
rtems_unsigned32 ticks_per_second;
|
||||
rtems_unsigned32 seconds;
|
||||
int packets_per_second;
|
||||
|
||||
(void) rtems_clock_get( RTEMS_CLOCK_GET_TICKS_SINCE_BOOT, &ticks );
|
||||
(void) rtems_clock_get( RTEMS_CLOCK_GET_TICKS_PER_SECOND, &ticks_per_second );
|
||||
|
||||
seconds = ticks / ticks_per_second;
|
||||
if ( seconds == 0 )
|
||||
seconds = 1;
|
||||
|
||||
packets_per_second = Shm_Receive_message_count / seconds;
|
||||
if ( (Shm_Receive_message_count % seconds) >= (seconds / 2) )
|
||||
packets_per_second++;
|
||||
|
||||
printf( "\n\nSHMDR STATISTICS (NODE %d)\n", Shm_Local_node );
|
||||
printf( "TICKS SINCE BOOT = %d\n", ticks );
|
||||
printf( "TICKS PER SECOND = %d\n", ticks_per_second );
|
||||
printf( "ISRs=%d\n", Shm_Interrupt_count );
|
||||
printf( "RECV=%d\n", Shm_Receive_message_count );
|
||||
printf( "NULL=%d\n", Shm_Null_message_count );
|
||||
printf( "PKTS/SEC=%d\n", packets_per_second );
|
||||
}
|
||||
@@ -1,38 +0,0 @@
|
||||
/* void MPCI_Fatal( error )
|
||||
*
|
||||
* This routine is the shared memory driver fatal error handler.
|
||||
*
|
||||
* Input parameters:
|
||||
* error - fatal error code
|
||||
*
|
||||
* Output parameters: NEVER RETURNS
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
void MPCI_Fatal(
|
||||
Internal_errors_Source source,
|
||||
boolean is_internal,
|
||||
rtems_unsigned32 error
|
||||
)
|
||||
{
|
||||
/* Eventually need to attempt to broadcast a K_FATAL message
|
||||
* without checking for all possible errors (do not want to
|
||||
* recurse).
|
||||
*
|
||||
* Also need to avoid using Shm_Node_statuses if the driver has not been
|
||||
* initialized.
|
||||
*/
|
||||
|
||||
Shm_Local_node_status->error = Shm_Convert(error);
|
||||
}
|
||||
@@ -1,47 +0,0 @@
|
||||
/* Shm_Envelope_control *Shm_Locked_queue_Get( lq_cb )
|
||||
*
|
||||
* This routine returns an envelope control block from a shared
|
||||
* memory queue.
|
||||
*
|
||||
* Input parameters:
|
||||
* lq_cb - pointer to a locked queue control block
|
||||
*
|
||||
* Output parameters:
|
||||
* returns - pointer to an envelope control block
|
||||
* - NULL if no envelopes on specified queue
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <shm_driver.h>
|
||||
|
||||
Shm_Envelope_control *Shm_Locked_queue_Get(
|
||||
Shm_Locked_queue_Control *lq_cb
|
||||
)
|
||||
{
|
||||
Shm_Envelope_control *tmp_ecb;
|
||||
rtems_unsigned32 tmpfront;
|
||||
|
||||
tmp_ecb = NULL;
|
||||
Shm_Lock( lq_cb );
|
||||
|
||||
tmpfront = Shm_Convert(lq_cb->front);
|
||||
if ( tmpfront != Shm_Locked_queue_End_of_list ) {
|
||||
tmp_ecb = &Shm_Envelopes[ tmpfront ];
|
||||
lq_cb->front = tmp_ecb->next;
|
||||
if ( tmp_ecb->next == Shm_Locked_queue_End_of_list )
|
||||
lq_cb->rear = Shm_Locked_queue_End_of_list;
|
||||
tmp_ecb->next = Shm_Locked_queue_Not_on_list;
|
||||
}
|
||||
|
||||
Shm_Unlock( lq_cb );
|
||||
return( tmp_ecb );
|
||||
}
|
||||
@@ -1,35 +0,0 @@
|
||||
/* Shm_Get_packet
|
||||
*
|
||||
* This routine is the shared memory locked queue MPCI driver
|
||||
* routine used to obtain an empty message packet.
|
||||
*
|
||||
* Input parameters:
|
||||
* packet - address of pointer to packet
|
||||
*
|
||||
* Output parameters:
|
||||
* *(cpb->get_packet) - address of allocated packet
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
rtems_mpci_entry Shm_Get_packet(
|
||||
rtems_packet_prefix **packet
|
||||
)
|
||||
{
|
||||
Shm_Envelope_control *ecb;
|
||||
|
||||
ecb = Shm_Allocate_envelope();
|
||||
if ( !ecb )
|
||||
rtems_fatal_error_occurred ( SHM_NO_FREE_PKTS );
|
||||
*packet = Shm_Envelope_control_to_packet_prefix_pointer( ecb );
|
||||
}
|
||||
@@ -1,253 +0,0 @@
|
||||
/* Shm_Initialization
|
||||
*
|
||||
* This routine is the shared memory communications initerface
|
||||
* driver initialization routine.
|
||||
*
|
||||
* Input parameters: NONE
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#define _SHM_INIT
|
||||
|
||||
#include <rtems.h>
|
||||
#include <shm_driver.h>
|
||||
|
||||
#include <string.h> /* memset() */
|
||||
#include <stdlib.h> /* malloc() */
|
||||
#include <assert.h>
|
||||
|
||||
/*
|
||||
* User extension to install MPCI_Fatal as a fatal error
|
||||
* handler extension
|
||||
*/
|
||||
|
||||
rtems_extensions_table MPCI_Shm_extensions;
|
||||
|
||||
rtems_mpci_entry Shm_Initialization( void )
|
||||
|
||||
{
|
||||
rtems_unsigned32 i, all_initialized;
|
||||
rtems_unsigned32 interrupt_cause, interrupt_value;
|
||||
void *interrupt_address;
|
||||
Shm_Node_status_control *nscb;
|
||||
rtems_unsigned32 extension_id; /* for installation of MPCI_Fatal */
|
||||
rtems_unsigned32 remaining_memory;
|
||||
/* XXX these should use "public" methods to set their values.... */
|
||||
rtems_configuration_table *configuration = _Configuration_Table;
|
||||
rtems_multiprocessing_table *mp_configuration = _Configuration_MP_table;
|
||||
|
||||
Shm_RTEMS_Configuration = configuration;
|
||||
Shm_RTEMS_MP_Configuration = mp_configuration;
|
||||
|
||||
Shm_Local_node = Shm_RTEMS_MP_Configuration->node;
|
||||
Shm_Maximum_nodes = Shm_RTEMS_MP_Configuration->maximum_nodes;
|
||||
|
||||
Shm_Get_configuration( Shm_Local_node, &Shm_Configuration );
|
||||
|
||||
Shm_Interrupt_table = (Shm_Interrupt_information *) malloc(
|
||||
sizeof(Shm_Interrupt_information) * (Shm_Maximum_nodes + 1)
|
||||
);
|
||||
|
||||
assert( Shm_Interrupt_table );
|
||||
|
||||
|
||||
Shm_Receive_message_count = 0;
|
||||
Shm_Null_message_count = 0;
|
||||
Shm_Interrupt_count = 0;
|
||||
|
||||
/*
|
||||
* Set the Node Status indicators
|
||||
*/
|
||||
|
||||
Shm_Pending_initialization =
|
||||
Shm_Convert(rtems_build_name( 'P', 'E', 'N', 'D' ));
|
||||
Shm_Initialization_complete =
|
||||
Shm_Convert(rtems_build_name( 'C', 'O', 'M', 'P' ));
|
||||
Shm_Active_node =
|
||||
Shm_Convert(rtems_build_name( 'A', 'C', 'T', 'V' ));
|
||||
|
||||
/*
|
||||
* Initialize the constants used by the Locked Queue code.
|
||||
*/
|
||||
|
||||
Shm_Locked_queue_End_of_list = Shm_Convert( 0xffffffff );
|
||||
Shm_Locked_queue_Not_on_list = Shm_Convert( 0xfffffffe );
|
||||
|
||||
/*
|
||||
* Set the base addresses for the:
|
||||
* + Node Status Table
|
||||
* + Free Pool and Receive Queues
|
||||
* + Envelopes
|
||||
*/
|
||||
|
||||
Shm_Node_statuses = (Shm_Node_status_control *) START_NS_CBS;
|
||||
Shm_Locked_queues = (Shm_Locked_queue_Control *) START_LQ_CBS;
|
||||
Shm_Envelopes = (Shm_Envelope_control *) START_ENVELOPES;
|
||||
|
||||
/*
|
||||
* Calculate the maximum number of envelopes which can be
|
||||
* placed the remaining shared memory.
|
||||
*/
|
||||
|
||||
remaining_memory =
|
||||
((void *)Shm_Configuration->base + Shm_Configuration->length) -
|
||||
((void *)Shm_Envelopes);
|
||||
|
||||
Shm_Maximum_envelopes = remaining_memory / sizeof( Shm_Envelope_control );
|
||||
Shm_Maximum_envelopes -= 1;
|
||||
|
||||
/*
|
||||
* Set the pointer to the receive queue for the local node.
|
||||
* When we receive a node, we will get it from here before
|
||||
* processing it.
|
||||
*/
|
||||
|
||||
Shm_Local_receive_queue = &Shm_Locked_queues[ Shm_Local_node ];
|
||||
Shm_Local_node_status = &Shm_Node_statuses[ Shm_Local_node ];
|
||||
|
||||
/*
|
||||
* Convert local interrupt cause information into the
|
||||
* neutral format so other nodes will be able to
|
||||
* understand it.
|
||||
*/
|
||||
|
||||
interrupt_address =
|
||||
(void *) Shm_Convert( (rtems_unsigned32)Shm_Configuration->Intr.address );
|
||||
interrupt_value = Shm_Convert( Shm_Configuration->Intr.value );
|
||||
interrupt_cause = Shm_Convert( Shm_Configuration->Intr.length );
|
||||
|
||||
if ( Shm_Configuration->poll_intr == POLLED_MODE ) Shm_setclockvec();
|
||||
else Shm_setvec();
|
||||
|
||||
if ( Shm_Is_master_node() ) {
|
||||
|
||||
/*
|
||||
* Zero out the shared memory area.
|
||||
*/
|
||||
|
||||
(void) memset(
|
||||
(void *) Shm_Configuration->base,
|
||||
0,
|
||||
Shm_Configuration->length
|
||||
);
|
||||
|
||||
/*
|
||||
* Initialize all of the locked queues (the free envelope
|
||||
* pool and a receive queue per node) and set all of the
|
||||
* node's status so they will be waiting to initialization
|
||||
* to complete.
|
||||
*/
|
||||
|
||||
Shm_Locked_queue_Initialize( FREE_ENV_CB, FREE_ENV_POOL );
|
||||
|
||||
for ( i=SHM_FIRST_NODE ; i<=Shm_Maximum_nodes ; i++ ) {
|
||||
Shm_Initialize_receive_queue( i );
|
||||
|
||||
Shm_Node_statuses[ i ].status = Shm_Pending_initialization;
|
||||
Shm_Node_statuses[ i ].error = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize all of the envelopes and place them in the
|
||||
* free pool.
|
||||
*/
|
||||
|
||||
for ( i=0 ; i<Shm_Maximum_envelopes ; i++ ) {
|
||||
Shm_Envelopes[ i ].index = Shm_Convert(i);
|
||||
Shm_Free_envelope( &Shm_Envelopes[ i ] );
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize this node's interrupt information in the
|
||||
* shared area so other nodes can interrupt us.
|
||||
*/
|
||||
|
||||
Shm_Local_node_status->int_address = (rtems_unsigned32) interrupt_address;
|
||||
Shm_Local_node_status->int_value = interrupt_value;
|
||||
Shm_Local_node_status->int_length = interrupt_cause;
|
||||
|
||||
Shm_Local_node_status->status = Shm_Initialization_complete;
|
||||
|
||||
/*
|
||||
* Loop until all nodes have completed initialization.
|
||||
*/
|
||||
|
||||
do {
|
||||
all_initialized = 1;
|
||||
|
||||
for ( i = SHM_FIRST_NODE ; i <= Shm_Maximum_nodes ; i++ )
|
||||
if ( Shm_Node_statuses[ i ].status != Shm_Initialization_complete )
|
||||
all_initialized = 0;
|
||||
|
||||
} while ( all_initialized == 0 );
|
||||
|
||||
/*
|
||||
* Tell the other nodes we think that the system is up.
|
||||
*/
|
||||
|
||||
for ( i = SHM_FIRST_NODE ; i <= Shm_Maximum_nodes ; i++ )
|
||||
Shm_Node_statuses[ i ].status = Shm_Active_node;
|
||||
|
||||
} else { /* is not MASTER node */
|
||||
|
||||
/*
|
||||
* Initialize the node status for the non-master nodes.
|
||||
* Because the master node zeroes out memory, it is
|
||||
* necessary for them to keep putting their values in
|
||||
* the node status area until the master says they
|
||||
* should become active.
|
||||
*/
|
||||
|
||||
Shm_Local_node_status->status = Shm_Pending_initialization;
|
||||
|
||||
do {
|
||||
|
||||
if ( Shm_Local_node_status->status == Shm_Pending_initialization ) {
|
||||
|
||||
/*
|
||||
* Initialize this node's interrupt information in the
|
||||
* shared area so other nodes can interrupt us.
|
||||
*/
|
||||
|
||||
Shm_Local_node_status->int_address =
|
||||
(rtems_unsigned32) interrupt_address;
|
||||
Shm_Local_node_status->int_value = interrupt_value;
|
||||
Shm_Local_node_status->int_length = interrupt_cause;
|
||||
|
||||
Shm_Local_node_status->status = Shm_Initialization_complete;
|
||||
}
|
||||
} while ( Shm_Local_node_status->status != Shm_Active_node ) ;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the Interrupt Information Table
|
||||
*/
|
||||
|
||||
for ( i = SHM_FIRST_NODE ; i <= Shm_Maximum_nodes ; i++ ) {
|
||||
nscb = &Shm_Node_statuses[ i ];
|
||||
|
||||
Shm_Interrupt_table[i].address = Shm_Convert_address(
|
||||
(void *)Shm_Convert(((vol_u32) nscb->int_address))
|
||||
);
|
||||
Shm_Interrupt_table[i].value = Shm_Convert( nscb->int_value );
|
||||
Shm_Interrupt_table[i].length = Shm_Convert( nscb->int_length );
|
||||
}
|
||||
|
||||
MPCI_Shm_extensions.fatal = MPCI_Fatal;
|
||||
|
||||
(void) rtems_extension_create(
|
||||
rtems_build_name( 'M', 'P', 'E', 'X' ),
|
||||
&MPCI_Shm_extensions,
|
||||
&extension_id
|
||||
);
|
||||
}
|
||||
@@ -1,34 +0,0 @@
|
||||
/* void Shm_Locked_queue_Initialize( lq_cb, owner )
|
||||
*
|
||||
* This routine initializes a shared memory locked queue.
|
||||
*
|
||||
* Input parameters:
|
||||
* lq_cb - pointer to the control block of the queue
|
||||
* to be initialized
|
||||
* owner - unique idenitifier of who owns this queue.
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
void Shm_Locked_queue_Initialize(
|
||||
Shm_Locked_queue_Control *lq_cb,
|
||||
rtems_unsigned32 owner
|
||||
)
|
||||
{
|
||||
Shm_Initialize_lock( lq_cb );
|
||||
lq_cb->front = Shm_Locked_queue_End_of_list;
|
||||
lq_cb->rear = Shm_Locked_queue_End_of_list;
|
||||
lq_cb->owner = Shm_Convert(owner);
|
||||
}
|
||||
@@ -1,57 +0,0 @@
|
||||
/* void Shm_Cause_interrupt( node )
|
||||
*
|
||||
* This routine is the shared memory driver routine which
|
||||
* generates interrupts to other CPUs.
|
||||
*
|
||||
* It uses the information placed in the node status control
|
||||
* block by each node. For example, when used with the Motorola
|
||||
* MVME136 board, the MPCSR is used.
|
||||
*
|
||||
* Input parameters:
|
||||
* node - destination of this packet (0 = broadcast)
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
void Shm_Cause_interrupt(
|
||||
rtems_unsigned32 node
|
||||
)
|
||||
{
|
||||
Shm_Interrupt_information *intr;
|
||||
rtems_unsigned8 *u8;
|
||||
rtems_unsigned16 *u16;
|
||||
rtems_unsigned32 *u32;
|
||||
rtems_unsigned32 value;
|
||||
|
||||
intr = &Shm_Interrupt_table[node];
|
||||
value = intr->value;
|
||||
|
||||
switch ( intr->length ) {
|
||||
case NO_INTERRUPT:
|
||||
break;
|
||||
case BYTE:
|
||||
u8 = (rtems_unsigned8 *)intr->address;
|
||||
*u8 = (rtems_unsigned8) value;
|
||||
break;
|
||||
case WORD:
|
||||
u16 = (rtems_unsigned16 *)intr->address;
|
||||
*u16 = (rtems_unsigned16) value;
|
||||
break;
|
||||
case LONG:
|
||||
u32 = (rtems_unsigned32 *)intr->address;
|
||||
*u32 = (rtems_unsigned32) value;
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -1,58 +0,0 @@
|
||||
/* mpci.h
|
||||
*
|
||||
* This include file contains all the renaming necessary to
|
||||
* have an application use the Shared Memory Driver as its
|
||||
* sole mechanism for MPCI.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef __SHM_MPCI_h
|
||||
#define __SHM_MPCI_h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <shm_driver.h>
|
||||
|
||||
#define MPCI_Initialization( _configuration ) \
|
||||
Shm_Initialization( _configuration )
|
||||
|
||||
#define MPCI_Get_packet( _the_packet ) \
|
||||
Shm_Get_packet( _the_packet )
|
||||
|
||||
#define MPCI_Return_packet( _the_packet ) \
|
||||
Shm_Return_packet( _the_packet )
|
||||
|
||||
#define MPCI_Receive_packet( _the_packet ) \
|
||||
Shm_Receive_packet( _the_packet )
|
||||
|
||||
#define MPCI_Send_packet( _destination, _the_packet ) \
|
||||
Shm_Send_packet( _destination, _the_packet )
|
||||
|
||||
/* Unnecessary... mapped in shm_driver.h
|
||||
#define MPCI_Fatal( _the_error ) \
|
||||
Shm_Fatal( _the_error )
|
||||
*/
|
||||
|
||||
#define MPCI_Enable_statistics()
|
||||
|
||||
#define MPCI_Print_statistics() \
|
||||
Shm_Print_statistics()
|
||||
|
||||
/* no need to rename the MPCI_Table either */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
@@ -1,22 +0,0 @@
|
||||
/* _Shm_isr()
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
rtems_isr Shm_isr(
|
||||
rtems_vector_number vector
|
||||
)
|
||||
{
|
||||
Shm_Interrupt_count += 1;
|
||||
rtems_multiprocessing_announce();
|
||||
}
|
||||
@@ -1,52 +0,0 @@
|
||||
/* void Shm_Poll()
|
||||
*
|
||||
* This routine polls to see if a packet has arrived. If one
|
||||
* has it informs the executive. It is typically called from
|
||||
* the clock tick interrupt service routine.
|
||||
*
|
||||
* Input parameters: NONE
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/score/sysstate.h>
|
||||
#include <rtems/libio.h>
|
||||
|
||||
#include "shm_driver.h"
|
||||
|
||||
void Shm_Poll()
|
||||
{
|
||||
rtems_unsigned32 tmpfront;
|
||||
rtems_libio_ioctl_args_t args;
|
||||
|
||||
/* invoke clock isr */
|
||||
args.iop = 0;
|
||||
args.command = rtems_build_name('I', 'S', 'R', ' ');
|
||||
(void) rtems_io_control(rtems_clock_major, rtems_clock_minor, &args);
|
||||
|
||||
/*
|
||||
* Check for msgs only if we are "up"
|
||||
* This avoids a race condition where we may get a clock
|
||||
* interrupt before MPCI has completed its init
|
||||
*/
|
||||
|
||||
if (_System_state_Is_up(_System_state_Get()))
|
||||
{
|
||||
tmpfront = Shm_Local_receive_queue->front;
|
||||
if ( Shm_Convert(tmpfront) != Shm_Locked_queue_End_of_list )
|
||||
{
|
||||
rtems_multiprocessing_announce();
|
||||
Shm_Interrupt_count++;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,43 +0,0 @@
|
||||
/* Shm_Receive_packet
|
||||
*
|
||||
* This routine is the shared memory locked queue MPCI driver routine
|
||||
* used to obtain a packet containing a message from this node's
|
||||
* receive queue.
|
||||
*
|
||||
* Input parameters:
|
||||
* packet - address of a pointer to a packet
|
||||
*
|
||||
* Output parameters:
|
||||
* *(rpb->packet) - pointer to packet
|
||||
* NULL if no packet currently available
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
rtems_mpci_entry Shm_Receive_packet(
|
||||
rtems_packet_prefix **packet
|
||||
)
|
||||
{
|
||||
Shm_Envelope_control *ecb;
|
||||
|
||||
ecb = Shm_Locked_queue_Get( Shm_Local_receive_queue );
|
||||
if ( ecb ) {
|
||||
*(packet) = Shm_Envelope_control_to_packet_prefix_pointer( ecb );
|
||||
if ( ecb->Preamble.endian != Shm_Configuration->format )
|
||||
Shm_Convert_packet( *packet );
|
||||
Shm_Receive_message_count++;
|
||||
} else {
|
||||
*(packet) = NULL;
|
||||
Shm_Null_message_count++;
|
||||
}
|
||||
}
|
||||
@@ -1,31 +0,0 @@
|
||||
/* Shm_Return_packet
|
||||
*
|
||||
* This routine is the shared memory locked queue MPCI driver
|
||||
* routine used to return a message packet to a free envelope
|
||||
* pool accessible by this node.
|
||||
*
|
||||
* Input parameters:
|
||||
* packet - address of pointer to packet
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
rtems_mpci_entry Shm_Return_packet(
|
||||
rtems_packet_prefix *packet
|
||||
)
|
||||
{
|
||||
Shm_Free_envelope( Shm_Packet_prefix_to_envelope_control_pointer(packet) );
|
||||
}
|
||||
|
||||
@@ -1,60 +0,0 @@
|
||||
/* Shm_Send_packet
|
||||
*
|
||||
* This routine is the shared memory driver locked queue write
|
||||
* MPCI driver routine. This routine sends the specified packet
|
||||
* to the destination specified by "node". A "node" value of
|
||||
* zero designates that this packet is to be broadcasted.
|
||||
*
|
||||
* Input parameters:
|
||||
* node - destination of this packet (0 = broadcast)
|
||||
* packet - address of packet
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include "shm_driver.h"
|
||||
|
||||
struct pkt_cpy {
|
||||
rtems_unsigned32 packet[MAX_PACKET_SIZE/4];
|
||||
};
|
||||
|
||||
rtems_mpci_entry Shm_Send_packet(
|
||||
rtems_unsigned32 node,
|
||||
rtems_packet_prefix *packet
|
||||
)
|
||||
{
|
||||
Shm_Envelope_control *ecb, *tmp_ecb;
|
||||
rtems_unsigned32 nnum;
|
||||
|
||||
ecb = Shm_Packet_prefix_to_envelope_control_pointer( packet );
|
||||
if ( node ) {
|
||||
Shm_Build_preamble( ecb, node );
|
||||
Shm_Build_postamble( ecb );
|
||||
Shm_Append_to_receive_queue( node, ecb );
|
||||
(*Shm_Configuration->cause_intr)( node );
|
||||
}
|
||||
else {
|
||||
for( nnum = SHM_FIRST_NODE ; nnum <= Shm_Maximum_nodes ; nnum++ )
|
||||
if ( Shm_Local_node != nnum ) {
|
||||
tmp_ecb = Shm_Allocate_envelope();
|
||||
if ( !tmp_ecb )
|
||||
rtems_fatal_error_occurred( SHM_NO_FREE_PKTS );
|
||||
Shm_Build_preamble( tmp_ecb, nnum );
|
||||
*((struct pkt_cpy *)tmp_ecb->packet) = *((struct pkt_cpy *)packet);
|
||||
Shm_Build_postamble( tmp_ecb );
|
||||
Shm_Append_to_receive_queue( nnum, tmp_ecb );
|
||||
(*Shm_Configuration->cause_intr)( nnum );
|
||||
}
|
||||
Shm_Free_envelope( ecb );
|
||||
}
|
||||
}
|
||||
@@ -1,33 +0,0 @@
|
||||
/* Shm_setclockvec
|
||||
*
|
||||
* This routines installs the shared memory clock interrupt handler
|
||||
* used when the driver is used in polling mode.
|
||||
*
|
||||
* INPUT PARAMETERS: NONE
|
||||
*
|
||||
* OUTPUT PARAMETERS: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/libio.h>
|
||||
|
||||
#include "shm_driver.h"
|
||||
|
||||
rtems_isr Shm_setclockvec()
|
||||
{
|
||||
rtems_libio_ioctl_args_t args;
|
||||
args.iop = 0;
|
||||
args.command = rtems_build_name('N', 'E', 'W', ' ');
|
||||
args.buffer = (void *) Shm_Poll;
|
||||
|
||||
(void) rtems_io_control(rtems_clock_major, rtems_clock_minor, &args);
|
||||
}
|
||||
@@ -1,544 +0,0 @@
|
||||
/* shm_driver.h
|
||||
*
|
||||
* This include file contains all the constants, structures,
|
||||
* and global variables for this RTEMS based shared memory
|
||||
* communications interface driver.
|
||||
*
|
||||
* Processor board dependencies are in other files.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef __SHM_h
|
||||
#define __SHM_h
|
||||
|
||||
#include <clockdrv.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* The information contained in the Node Status, Locked Queue, and
|
||||
* Envelope Control Blocks must be maintained in a NEUTRAL format.
|
||||
* Currently the neutral format may be selected as big or little
|
||||
* endian by simply defining either NEUTRAL_BIG or NEUTRAL_LITTLE.
|
||||
*
|
||||
* It is CRITICAL to note that the neutral format can ONLY be
|
||||
* changed by modifying this file and recompiling the ENTIRE
|
||||
* SHM driver including ALL target specific support files.
|
||||
*
|
||||
* The following table details the memory contents for the endian
|
||||
* field of the Node Status Control Block in the various
|
||||
* data format configurations (data is in hexadecimal):
|
||||
*
|
||||
* NEUTRAL NATIVE BYTE 0 BYTE 1 BYTE 2 BYTE 3
|
||||
* ======= ====== ====== ====== ====== ======
|
||||
* BIG BIG 00 00 00 01
|
||||
* BIG LITTLE 10 00 00 00
|
||||
* LITTLE BIG 01 00 00 00
|
||||
* LITTLE LITTLE 00 00 00 10
|
||||
*
|
||||
*
|
||||
* NOTE: XXX
|
||||
* PORTABILITY OF LOCKING INSTRUCTIONS
|
||||
* ===================================
|
||||
* The locking mechanism described below is not
|
||||
* general enough. Where the hardware supports
|
||||
* it we should use "atomic swap" instructions
|
||||
* so the values in the lock can be tailored to
|
||||
* support a CPU with only weak atomic memory
|
||||
* instructions. There are combinations of
|
||||
* CPUs with inflexible atomic memory instructions
|
||||
* which appear to be incompatible. For example,
|
||||
* the SPARClite instruction uses a byte which is
|
||||
* 0xFF when locked. The PA-RISC uses 1 to indicate
|
||||
* locked and 0 when unlocked. These CPUs appear to
|
||||
* have incompatible lock instructions. But
|
||||
* they could be used in a heterogenous system
|
||||
* with does not mix SPARCs and PA-RISCs. For
|
||||
* example, the i386 and SPARC or i386 and SPARC
|
||||
* could work together. The bottom line is that
|
||||
* not every CPU will work together using this
|
||||
* locking scheme. There are supposed to be
|
||||
* algorithms to do this without hardware assist
|
||||
* and one of these should be incorporated into
|
||||
* the shared memory driver.
|
||||
*
|
||||
* The most flexible scheme using the instructions
|
||||
* of the various CPUs for efficiency would be to use
|
||||
* "atomic swaps" wherever possible. Make the lock
|
||||
* and unlock configurable much like BIG vs LITTLE
|
||||
* endian use of shared memory is now. The values
|
||||
* of the lock could then reflect the "worst"
|
||||
* CPU in a system. This still results in mixes
|
||||
* of CPUs which are incompatible.
|
||||
*
|
||||
* The current locking mechanism is based upon the MC68020
|
||||
* "tas" instruction which is atomic. All ports to other CPUs
|
||||
* comply with the restrictive placement of lock bit by this
|
||||
* instruction. The lock bit is the most significant bit in a
|
||||
* big-endian rtems_unsigned32. On other processors, the lock is
|
||||
* typically implemented via an atomic swap or atomic modify
|
||||
* bits type instruction.
|
||||
*/
|
||||
|
||||
#define NEUTRAL_BIG
|
||||
|
||||
#ifdef NEUTRAL_BIG
|
||||
#define SHM_BIG 0x00000001
|
||||
#define SHM_LITTLE 0x10000000
|
||||
#endif
|
||||
|
||||
#ifdef NEUTRAL_LITTLE
|
||||
#define SHM_BIG 0x01000000
|
||||
#define SHM_LITTLE 0x00000010
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following are the values used to fill in the lock field. Some CPUs
|
||||
* are able to write only a single value into field. By making the
|
||||
* lock and unlock values configurable, CPUs which support "atomic swap"
|
||||
* instructions can generally be made to work in any heterogeneous
|
||||
* configuration. However, it is possible for two CPUs to be incompatible
|
||||
* in regards to the lock field values. This occurs when two CPUs
|
||||
* which write only a single value to the field are used in a system
|
||||
* but the two CPUs write different incompatible values.
|
||||
*
|
||||
* NOTE: The following is a first attempt at defining values which
|
||||
* have a chance at working together. The m68k should use
|
||||
* chk2 instead of tas to be less restrictive. Target endian
|
||||
* problems (like the Force CPU386 which has (broken) big endian
|
||||
* view of the VMEbus address space) are not addressed yet.
|
||||
*/
|
||||
|
||||
#if defined(__i960__)
|
||||
#define SHM_LOCK_VALUE 0x00000080
|
||||
#define SHM_UNLOCK_VALUE 0
|
||||
#elif defined(__mc68000__)
|
||||
#define SHM_LOCK_VALUE 0x80000000
|
||||
#define SHM_UNLOCK_VALUE 0
|
||||
#define SHM_LOCK_VALUE 0x80000000
|
||||
#define SHM_UNLOCK_VALUE 0
|
||||
#elif defined(__i386__)
|
||||
#define SHM_LOCK_VALUE 0x80000000
|
||||
#define SHM_UNLOCK_VALUE 0
|
||||
#elif defined(__mips__)
|
||||
#define SHM_LOCK_VALUE 0x80000000
|
||||
#define SHM_UNLOCK_VALUE 0
|
||||
#elif defined(__hppa__)
|
||||
#define SHM_LOCK_VALUE 0
|
||||
#define SHM_UNLOCK_VALUE 1
|
||||
#elif defined(__PPC__)
|
||||
#define SHM_LOCK_VALUE 1
|
||||
#define SHM_UNLOCK_VALUE 0
|
||||
#elif defined(__unix__)
|
||||
#define SHM_LOCK_VALUE 0
|
||||
#define SHM_UNLOCK_VALUE 1
|
||||
#elif defined(_AM29K)
|
||||
#define SHM_LOCK_VALUE 0
|
||||
#define SHM_UNLOCK_VALUE 1
|
||||
#elif defined(no_cpu) /* for this values are irrelevant */
|
||||
#define SHM_LOCK_VALUE 1
|
||||
#define SHM_UNLOCK_VALUE 0
|
||||
#else
|
||||
#error "shm_driver.h - no SHM_LOCK_VALUE defined for this CPU architecture"
|
||||
#endif
|
||||
|
||||
#define Shm_Convert( value ) \
|
||||
((Shm_Configuration->convert) ? \
|
||||
(*Shm_Configuration->convert)(value) : (value))
|
||||
|
||||
/* constants */
|
||||
|
||||
#define SHM_MASTER 1 /* master initialization node */
|
||||
#define SHM_FIRST_NODE 1
|
||||
|
||||
/* size constants */
|
||||
|
||||
#define KILOBYTE (1024)
|
||||
#define MEGABYTE (1024*1024)
|
||||
|
||||
/* inter-node interrupt values */
|
||||
|
||||
#define NO_INTERRUPT 0 /* used for polled nodes */
|
||||
#define BYTE 1
|
||||
#define WORD 2
|
||||
#define LONG 4
|
||||
|
||||
/* operational mode constants -- used in SHM Configuration Table */
|
||||
#define POLLED_MODE 0
|
||||
#define INTR_MODE 1
|
||||
|
||||
/* error codes */
|
||||
|
||||
#define NO_ERROR 0
|
||||
#define SHM_NO_FREE_PKTS 0xf0000
|
||||
|
||||
/* null pointers of different types */
|
||||
|
||||
#define NULL_ENV_CB ((Shm_Envelope_control *) 0)
|
||||
#define NULL_CONVERT 0
|
||||
|
||||
/*
|
||||
* size of stuff before preamble in envelope.
|
||||
* It must be a constant since we will use it to generate MAX_PACKET_SIZE
|
||||
*/
|
||||
|
||||
#define SHM_ENVELOPE_PREFIX_OVERHEAD (4 * sizeof(vol_u32))
|
||||
|
||||
/*
|
||||
* The following is adjusted so envelopes are MAX_ENVELOPE_SIZE bytes long.
|
||||
* It must be >= RTEMS_MINIMUM_PACKET_SIZE in mppkt.h.
|
||||
*/
|
||||
|
||||
#ifndef MAX_ENVELOPE_SIZE
|
||||
#define MAX_ENVELOPE_SIZE 0x180
|
||||
#endif
|
||||
|
||||
#define MAX_PACKET_SIZE (MAX_ENVELOPE_SIZE - \
|
||||
SHM_ENVELOPE_PREFIX_OVERHEAD + \
|
||||
sizeof(Shm_Envelope_preamble) + \
|
||||
sizeof(Shm_Envelope_postamble))
|
||||
|
||||
|
||||
/* constants pertinent to Locked Queue routines */
|
||||
|
||||
#define LQ_UNLOCKED SHM_UNLOCK_VALUE
|
||||
#define LQ_LOCKED SHM_LOCK_VALUE
|
||||
|
||||
/* constants related to the Free Envelope Pool */
|
||||
|
||||
#define FREE_ENV_POOL 0
|
||||
#define FREE_ENV_CB (&Shm_Locked_queues[ FREE_ENV_POOL ])
|
||||
|
||||
/* The following are important when dealing with
|
||||
* the shared memory communications interface area.
|
||||
*
|
||||
* NOTE: The starting address and length of the shared memory
|
||||
* is defined in a system dependent file.
|
||||
*/
|
||||
|
||||
#define START_NS_CBS ((void *)Shm_Configuration->base)
|
||||
#define START_LQ_CBS ((START_NS_CBS) + \
|
||||
( (sizeof (Shm_Node_status_control)) * (Shm_Maximum_nodes + 1) ) )
|
||||
#define START_ENVELOPES ( ((void *) START_LQ_CBS) + \
|
||||
( (sizeof (Shm_Locked_queue_Control)) * (Shm_Maximum_nodes + 1) ) )
|
||||
#define END_SHMCI_AREA ( (void *) START_ENVELOPES + \
|
||||
( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) )
|
||||
#define END_SHARED_MEM (START_NS_CBS+Shm_Configuration->length)
|
||||
|
||||
/* macros */
|
||||
|
||||
#define Shm_Is_master_node() \
|
||||
( SHM_MASTER == Shm_Local_node )
|
||||
|
||||
#define Shm_Free_envelope( ecb ) \
|
||||
Shm_Locked_queue_Add( FREE_ENV_CB, (ecb) )
|
||||
#define Shm_Allocate_envelope() \
|
||||
Shm_Locked_queue_Get(FREE_ENV_CB)
|
||||
|
||||
#define Shm_Initialize_receive_queue(node) \
|
||||
Shm_Locked_queue_Initialize( &Shm_Locked_queues[node], node )
|
||||
|
||||
#define Shm_Append_to_receive_queue(node, ecb) \
|
||||
Shm_Locked_queue_Add( &Shm_Locked_queues[node], (ecb) )
|
||||
|
||||
#define Shm_Envelope_control_to_packet_prefix_pointer(ecb) \
|
||||
((void *)(ecb)->packet)
|
||||
|
||||
#define Shm_Packet_prefix_to_envelope_control_pointer( pkt ) \
|
||||
((Shm_Envelope_control *)((rtems_unsigned8 *)(pkt) - \
|
||||
(sizeof(Shm_Envelope_preamble) + SHM_ENVELOPE_PREFIX_OVERHEAD)))
|
||||
|
||||
#define Shm_Build_preamble(ecb, node) \
|
||||
(ecb)->Preamble.endian = Shm_Configuration->format
|
||||
|
||||
#define Shm_Build_postamble( ecb )
|
||||
|
||||
/* volatile types */
|
||||
|
||||
typedef volatile rtems_unsigned8 vol_u8;
|
||||
typedef volatile rtems_unsigned32 vol_u32;
|
||||
|
||||
/* shm control information */
|
||||
|
||||
struct shm_info {
|
||||
vol_u32 not_currently_used_0;
|
||||
vol_u32 not_currently_used_1;
|
||||
vol_u32 not_currently_used_2;
|
||||
vol_u32 not_currently_used_3;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
/*byte start_of_text;*/
|
||||
vol_u32 endian;
|
||||
vol_u32 not_currently_used_0;
|
||||
vol_u32 not_currently_used_1;
|
||||
vol_u32 not_currently_used_2;
|
||||
} Shm_Envelope_preamble;
|
||||
|
||||
typedef struct {
|
||||
} Shm_Envelope_postamble;
|
||||
|
||||
/* WARNING! If you change this structure, don't forget to change
|
||||
* SHM_ENVELOPE_PREFIX_OVERHEAD and
|
||||
* Shm_Packet_prefix_to_envelope_control_pointer() above.
|
||||
*/
|
||||
|
||||
/* This comment block describes the contents of each field
|
||||
* of the Envelope Control Block:
|
||||
*
|
||||
* next - The index of the next envelope on this queue.
|
||||
* queue - The index of the queue this envelope is on.
|
||||
* index - The index of this envelope.
|
||||
* Preamble - Generic packet preamble. One day this structure
|
||||
* could be enhanced to contain routing information.
|
||||
* packet - RTEMS MPCI packet. Untouched by SHM Driver
|
||||
* other than copying and format conversion as
|
||||
* documented in the RTEMS User's Guide.
|
||||
* Postamble - Generic packet postamble. One day this structure
|
||||
* could be enhanced to contain checksum information.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
vol_u32 next; /* next envelope on queue */
|
||||
vol_u32 queue; /* queue on which this resides */
|
||||
vol_u32 index; /* index into array of envelopes*/
|
||||
vol_u32 pad0; /* insure the next one is aligned */
|
||||
Shm_Envelope_preamble Preamble; /* header information */
|
||||
vol_u8 packet[MAX_PACKET_SIZE]; /* RTEMS INFO */
|
||||
Shm_Envelope_postamble Postamble;/* trailer information */
|
||||
} Shm_Envelope_control;
|
||||
|
||||
/* This comment block describes the contents of each field
|
||||
* of the Locked Queue Control Block:
|
||||
*
|
||||
* lock - Lock used to insure mutually exclusive access.
|
||||
* front - Index of first envelope on queue. This field
|
||||
* is used to remove head of queue (receive).
|
||||
* rear - Index of last envelope on queue. This field
|
||||
* is used to add evelope to queue (send).
|
||||
* owner - The node number of the recipient (owning) node.
|
||||
* RTEMS does not use the node number zero (0).
|
||||
* The zero node is used by the SHM Driver for the
|
||||
* Free Envelope Queue shared by all nodes.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
vol_u32 lock; /* lock field for this queue */
|
||||
vol_u32 front; /* first envelope on queue */
|
||||
vol_u32 rear; /* last envelope on queue */
|
||||
vol_u32 owner; /* receiving (i.e. owning) node */
|
||||
} Shm_Locked_queue_Control;
|
||||
|
||||
/* This comment block describes the contents of each field
|
||||
* of the Node Status Control Block:
|
||||
*
|
||||
* status - Node status. Current values are Pending Initialization,
|
||||
* Initialization Complete, and Active Node. Other values
|
||||
* could be added to enhance fault tolerance.
|
||||
* error - Zero if the node has not failed. Otherwise,
|
||||
* this field contains a status indicating the
|
||||
* failure reason.
|
||||
* int_address, int_value, and int_length
|
||||
* - These field are the Interrupt Information table
|
||||
* for this node in neutral format. This is how
|
||||
* each node knows how to generate interrupts.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
vol_u32 status; /* node status information */
|
||||
vol_u32 error; /* fatal error code */
|
||||
vol_u32 int_address; /* write here for interrupt */
|
||||
vol_u32 int_value; /* this value causes interrupt */
|
||||
vol_u32 int_length; /* for this length (0,1,2,4) */
|
||||
vol_u32 not_currently_used_0;
|
||||
vol_u32 not_currently_used_1;
|
||||
vol_u32 not_currently_used_2;
|
||||
} Shm_Node_status_control;
|
||||
|
||||
/* This comment block describes the contents of each field
|
||||
* of the Interrupt Information Table. This table describes
|
||||
* how another node can generate an interrupt to this node.
|
||||
* This information is target board dependent. If the
|
||||
* SHM Driver is in POLLED_MODE, then all fields should
|
||||
* be initialized to NO_INTERRUPT.
|
||||
*
|
||||
* address - The address to which another node should
|
||||
* write to cause an interrupt.
|
||||
* value - The value which must be written
|
||||
* length - The size of the value to write. Valid
|
||||
* values are BYTE, WORD, and LONG.
|
||||
*
|
||||
* NOTE: The Node Status Control Block contains this
|
||||
* information in neutral format and not in a
|
||||
* structure to avoid potential alignment problems.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
vol_u32 *address; /* write here for interrupt */
|
||||
vol_u32 value; /* this value causes interrupt */
|
||||
vol_u32 length; /* for this length (0,1,2,4) */
|
||||
} Shm_Interrupt_information;
|
||||
|
||||
/* SHM Configuration Table
|
||||
*
|
||||
* This comment block describes the contents of each field
|
||||
* of the SHM Configuration Table.
|
||||
*
|
||||
* base - The base address of the shared memory. This
|
||||
* address may be specific to this node.
|
||||
* length - The length of the shared memory in bytes.
|
||||
* format - The natural format for rtems_unsigned32's in the
|
||||
* shared memory. Valid values are currently
|
||||
* only SHM_LITTLE and SHM_BIG.
|
||||
* convert - The address of the routine which converts
|
||||
* between neutral and local format.
|
||||
* poll_intr - The operational mode of the driver. Some
|
||||
* target boards may not provide hardware for
|
||||
* an interprocessor interrupt. If POLLED_MODE
|
||||
* is selected, the SHM driver will install a
|
||||
* wrapper around the Clock_isr() to poll for
|
||||
* incoming packets. Throughput is dependent
|
||||
* on the time between clock interrupts.
|
||||
* Valid values are POLLED_MODE and INTR_MODE.
|
||||
* cause_intr - This is the address of the routine used to
|
||||
* write to a particular address and cause an
|
||||
* interrupt on another node. This routine
|
||||
* may need to be target dependent if something
|
||||
* other than a normal write from C does not work.
|
||||
* Intr - This structure describes the operation required
|
||||
* to cause an interrupt to this node. The actual
|
||||
* contents of this structure are described above.
|
||||
*/
|
||||
|
||||
struct shm_config_info {
|
||||
vol_u32 *base; /* base address of SHM */
|
||||
vol_u32 length; /* length (in bytes) of SHM */
|
||||
vol_u32 format; /* SHM is big or little endian */
|
||||
vol_u32 (*convert)();/* neutral conversion routine */
|
||||
vol_u32 poll_intr;/* POLLED or INTR driven mode */
|
||||
void (*cause_intr)( rtems_unsigned32 );
|
||||
Shm_Interrupt_information Intr; /* cause intr information */
|
||||
};
|
||||
|
||||
typedef struct shm_config_info shm_config_table;
|
||||
|
||||
/* global variables */
|
||||
|
||||
#ifdef _SHM_INIT
|
||||
#define SHM_EXTERN
|
||||
#else
|
||||
#define SHM_EXTERN extern
|
||||
#endif
|
||||
|
||||
SHM_EXTERN shm_config_table *Shm_Configuration;
|
||||
SHM_EXTERN Shm_Interrupt_information *Shm_Interrupt_table;
|
||||
SHM_EXTERN Shm_Node_status_control *Shm_Node_statuses;
|
||||
SHM_EXTERN Shm_Locked_queue_Control *Shm_Locked_queues;
|
||||
SHM_EXTERN Shm_Envelope_control *Shm_Envelopes;
|
||||
SHM_EXTERN rtems_configuration_table *Shm_RTEMS_Configuration;
|
||||
SHM_EXTERN rtems_multiprocessing_table *Shm_RTEMS_MP_Configuration;
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Receive_message_count;
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Null_message_count;
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Interrupt_count;
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Local_node;
|
||||
SHM_EXTERN Shm_Locked_queue_Control *Shm_Local_receive_queue;
|
||||
SHM_EXTERN Shm_Node_status_control *Shm_Local_node_status;
|
||||
SHM_EXTERN rtems_unsigned32 Shm_isrstat;
|
||||
/* reported by shmdr */
|
||||
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Pending_initialization;
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Initialization_complete;
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Active_node;
|
||||
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Maximum_nodes;
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Maximum_envelopes;
|
||||
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_End_of_list;
|
||||
SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_Not_on_list;
|
||||
|
||||
/* functions */
|
||||
|
||||
/* locked queue routines */
|
||||
void Shm_Locked_queue_Add(
|
||||
Shm_Locked_queue_Control *, Shm_Envelope_control * );
|
||||
Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * );
|
||||
void Shm_Locked_queue_Initialize(
|
||||
Shm_Locked_queue_Control *, rtems_unsigned32 );
|
||||
/* Shm_Initialize_lock is CPU dependent */
|
||||
/* Shm_Lock is CPU dependent */
|
||||
/* Shm_Unlock is CPU dependent */
|
||||
|
||||
/* portable routines */
|
||||
void Init_env_pool();
|
||||
void Shm_Print_statistics( void );
|
||||
void MPCI_Fatal( Internal_errors_Source, boolean, rtems_unsigned32 );
|
||||
rtems_task Shm_Cause_interrupt( rtems_unsigned32 );
|
||||
void Shm_Poll();
|
||||
void Shm_setclockvec();
|
||||
void Shm_Convert_packet( rtems_packet_prefix * );
|
||||
|
||||
/* CPU specific routines are inlined in shmcpu.h */
|
||||
|
||||
/* target specific routines */
|
||||
void *Shm_Convert_address( void * );
|
||||
void Shm_Get_configuration( rtems_unsigned32, shm_config_table ** );
|
||||
void Shm_isr();
|
||||
void Shm_setvec( void );
|
||||
|
||||
void Shm_Initialize_lock( Shm_Locked_queue_Control * );
|
||||
void Shm_Lock( Shm_Locked_queue_Control * );
|
||||
void Shm_Unlock( Shm_Locked_queue_Control * );
|
||||
|
||||
/* MPCI entry points */
|
||||
rtems_mpci_entry Shm_Get_packet(
|
||||
rtems_packet_prefix **
|
||||
);
|
||||
|
||||
rtems_mpci_entry Shm_Initialization( void );
|
||||
|
||||
rtems_mpci_entry Shm_Receive_packet(
|
||||
rtems_packet_prefix **
|
||||
);
|
||||
|
||||
rtems_mpci_entry Shm_Return_packet(
|
||||
rtems_packet_prefix *
|
||||
);
|
||||
|
||||
rtems_mpci_entry Shm_Send_packet(
|
||||
rtems_unsigned32,
|
||||
rtems_packet_prefix *
|
||||
);
|
||||
|
||||
extern rtems_mpci_table MPCI_table;
|
||||
|
||||
#ifdef _SHM_INIT
|
||||
|
||||
/* multiprocessor communications interface (MPCI) table */
|
||||
|
||||
rtems_mpci_table MPCI_table = {
|
||||
100000, /* default timeout value in ticks */
|
||||
MAX_PACKET_SIZE, /* maximum packet size */
|
||||
Shm_Initialization, /* initialization procedure */
|
||||
Shm_Get_packet, /* get packet procedure */
|
||||
Shm_Return_packet, /* return packet procedure */
|
||||
Shm_Send_packet, /* packet send procedure */
|
||||
Shm_Receive_packet /* packet receive procedure */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
Reference in New Issue
Block a user