RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

doc: Update ARM documentation

Browse Source
This commit is contained in:
Sebastian Huber
2015-06-26 21:28:06 +02:00
parent 32005a7284
commit d84408a9aa
1 changed files with 15 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
doc/cpu_supplement/arm.t
View File

@@ -9,10 +9,10 @@
This chapter discusses the This chapter discusses the
@uref{http://en.wikipedia.org/wiki/ARM_architecture,ARM architecture} @uref{http://en.wikipedia.org/wiki/ARM_architecture,ARM architecture}
dependencies in this port of RTEMS. The ARM family has a wide variety of dependencies in this port of RTEMS. The ARMv4T (and compatible), ARMv7-A,
implementations by a wide range of vendors. Consequently, there are many, many ARMv7-R and ARMv7-M architecture versions are supported by RTEMS. Processors
CPU models within it. Currently the ARMv5 (and compatible) architecture with a MMU use a static configuration which is set up during system start. SMP
version as defined in the @code{ARMv5 Architecture Reference Manual} is supported by RTEMS. is supported.
@subheading Architecture Documents @subheading Architecture Documents
@@ -121,7 +121,7 @@ care about the MMU if necessary.
@section Interrupt Processing @section Interrupt Processing
The ARMv5 (and compatible) architecture has seven exception types: The ARMv4T (and compatible) architecture has seven exception types:
@itemize @bullet @itemize @bullet
@@ -140,6 +140,16 @@ intentional that the FIQ is not supported by the operating system. Without
operating system support for the FIQ it is not necessary to disable them during operating system support for the FIQ it is not necessary to disable them during
critical sections of the system. critical sections of the system.
The ARMv7-M architecture has a completely different exception model. Here
interrupts are disabled with a write of 0x80 to the @code{basepri_max}
register. This means that all exceptions and interrupts with a priority value
of greater than or equal to 0x80 are disabled. Thus exceptions and interrupts
with a priority value of less than 0x80 are non-maskable with respect to the
operating system and therefore must not use operating system services. Several
support libraries of chip vendors implicitly shift the priority value somehow
before the value is written to the NVIC IPR register. This can easily lead to
confusion.
@subsection Interrupt Levels @subsection Interrupt Levels
The RTEMS interrupt level mapping scheme for the ARM is not a numeric level as The RTEMS interrupt level mapping scheme for the ARM is not a numeric level as