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bsp/stm32h7: update stm32h7b3i-dk board system_stm32h7xx.c file

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Updated content comes from STM32CubeIDE 1.9.0 generated for STM32H7B3I-DK
board and have RTEMS related changes merged in.

Sponsored-By:	Precidata
This commit is contained in:
Karel Gardas
2022-05-15 22:10:40 +02:00
committed by Sebastian Huber
parent 63e327f9fb
commit d8017f203e
1 changed files with 25 additions and 115 deletions
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140
bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/system_stm32h7xx.c
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@@ -10,7 +10,7 @@
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock, it can be used
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
@@ -22,13 +22,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -51,11 +50,7 @@
#include <bsp/linker-symbols.h>
#endif /* __rtems__ */
#if !defined (HSE_VALUE)
#ifdef STM32H7B3xxQ
#define HSE_VALUE ((uint32_t)24000000) /*!< Value of the External oscillator in Hz */
#else
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
@@ -84,8 +79,8 @@
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
/* #define DATA_IN_D2_SRAM */
/*!< Uncomment the following line if you need to use initialized data in CD domain AHB SRAM */
/* #define DATA_IN_CD_AHB_SRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@@ -119,12 +114,12 @@
*/
#ifndef __rtems__
uint32_t SystemCoreClock = 64000000;
uint32_t SystemD2Clock = 64000000;
uint32_t SystemD2Clock = 64000000; /* AXI and AHBs Clock frequency */
#else /* __rtems__ */
RTEMS_SECTION(".rtemsstack") uint32_t SystemCoreClock;
RTEMS_SECTION(".rtemsstack") uint32_t SystemD2Clock;
#endif /* __rtems__ */
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /* CPU Domain Core Prescaler Table */
/**
* @}
@@ -151,9 +146,9 @@
*/
void SystemInit (void)
{
#if defined (DATA_IN_D2_SRAM) || defined (DATA_IN_CD_AHB_SRAM)
#ifdef DATA_IN_CD_AHB_SRAM
__IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM || DATA_IN_CD_AHB_SRAM */
#endif /* DATA_IN_CD_AHB_SRAM */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
@@ -169,16 +164,6 @@ void SystemInit (void)
/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
#if defined(D3_SRAM_BASE)
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
/* Reset D2CFGR register */
RCC->D2CFGR = 0x00000000;
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
#else
/* Reset CDCFGR1 register */
RCC->CDCFGR1 = 0x00000000;
@@ -187,8 +172,7 @@ void SystemInit (void)
/* Reset SRDCFGR register */
RCC->SRDCFGR = 0x00000000;
#endif
#ifdef STM32H7B3xxQ
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x02020200;
@@ -207,26 +191,7 @@ void SystemInit (void)
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x01010280;
#else
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x00000000;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00000000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x00000000;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x00000000;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x00000000;
#endif
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
@@ -236,67 +201,31 @@ void SystemInit (void)
/* Disable all interrupts */
RCC->CIER = 0x00000000;
#if (STM32H7_DEV_ID == 0x450UL)
/* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
#endif
#if defined (DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
#elif DATA_IN_CD_AHB_SRAM
#ifdef DATA_IN_CD_AHB_SRAM
/* in case of initialized data in CD AHB SRAM, enable the CD AHB SRAM clock */
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#else
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#endif /* RCC_AHB2ENR_D2SRAM3EN */
#endif /* DATA_IN_D2_SRAM */
#ifndef __rtems__
tmpreg = RCC->AHB2ENR;
(void) tmpreg;
#else /* __rtems__ */
RCC->AHB2ENR;
#endif /* __rtems__ */
#endif /* DATA_IN_CD_AHB_SRAM */
#ifdef STM32H7B3xxQ
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
#endif
#ifndef __rtems__
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif /* VECT_TAB_SRAM */
#else
/* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
#ifdef VECT_TAB_SRAM
#ifdef STM32H7B3xxQ
SCB->VTOR = CD_AXISRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal CD AXI-RAM */
#else
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
#endif
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
#endif /*DUAL_CORE && CORE_CM4*/
#else /* __rtems__ */
SCB->VTOR = (uint32_t) bsp_start_vector_table_begin;
#endif /* __rtems__ */
@@ -343,24 +272,22 @@ void SystemInit (void)
void SystemCoreClockUpdate (void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
uint32_t common_system_clock;
float_t fracn1, pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
common_system_clock = CSI_VALUE;
SystemCoreClock = CSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
common_system_clock = HSE_VALUE;
SystemCoreClock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
@@ -397,45 +324,29 @@ void SystemCoreClockUpdate (void)
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
common_system_clock = 0U;
SystemCoreClock = 0U;
}
break;
default:
common_system_clock = CSI_VALUE;
SystemCoreClock = CSI_VALUE;
break;
}
/* Compute SystemClock frequency --------------------------------------------------*/
#if defined (RCC_D1CFGR_D1CPRE)
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemCoreClock frequency : CM7 CPU frequency */
SystemCoreClock >>= tmp;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
}
@@ -450,4 +361,3 @@ void SystemCoreClockUpdate (void)
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/