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2008-08-21 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* startup/cpuinit.h: Uses now powerpc-utility.h.  Changed invalid usage
	of a boolean type to a proper integer type in calc_dbat_regvals().
	Througout code formatting.
This commit is contained in:
Joel Sherrill
2008-08-21 14:57:19 +00:00
parent 2a517327a6
commit d79a27be40
2 changed files with 182 additions and 130 deletions
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6
c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
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@@ -1,3 +1,9 @@
2008-08-21 Sebastian Huber <sebastian.huber@embedded-brains.de>
* startup/cpuinit.h: Uses now powerpc-utility.h. Changed invalid usage
of a boolean type to a proper integer type in calc_dbat_regvals().
Througout code formatting.
2008-08-20 Sebastian Huber <sebastian.huber@embedded-brains.de> 2008-08-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
* include/tm27.h: Uses now a decrementer exception handler. Replaces * include/tm27.h: Uses now a decrementer exception handler. Replaces

306
c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
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@@ -70,183 +70,229 @@
/* */ /* */
/***********************************************************************/ /***********************************************************************/
#include <bsp.h> #include <stdbool.h>
#include <rtems/powerpc/registers.h>
#include <mpc83xx/mpc83xx.h>
#include <libcpu/mmu.h>
#include <libcpu/spr.h>
#include <string.h> #include <string.h>
#define USE_IMMU #include <libcpu/powerpc-utility.h>
#include <libcpu/mmu.h>
/* Macros for HID0 access */ #include <mpc83xx/mpc83xx.h>
#define SET_HID0(r) __asm__ volatile ("mtspr 0x3F0,%0\n" ::"r"(r))
#define GET_HID0(r) __asm__ volatile ("mfspr %0,0x3F0\n" :"=r"(r))
#define DBAT_MTSPR(val,name) __MTSPR(val,name); #include <bsp.h>
#define SET_DBAT(n,uv,lv) {DBAT_MTSPR(lv,DBAT##n##L);DBAT_MTSPR(uv,DBAT##n##U);}
#if defined(USE_IMMU )
#define IBAT_MTSPR(val,name) __MTSPR(val,name);
#define SET_IBAT(n,uv,lv) {IBAT_MTSPR(lv,IBAT##n##L);IBAT_MTSPR(uv,IBAT##n##U);}
#endif
static void calc_dbat_regvals(BAT *bat_ptr, #define SET_DBAT( n, uv, lv) \
uint32_t base_addr, do { \
uint32_t size, PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \
boolean flg_w, PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \
boolean flg_i, } while (0)
boolean flg_m,
boolean flg_g, #define SET_IBAT( n, uv, lv) \
boolean flg_bpp) do { \
PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##L, lv); \
PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##U, uv); \
} while (0)
static void calc_dbat_regvals(
BAT *bat_ptr,
uint32_t base_addr,
uint32_t size,
bool flg_w,
bool flg_i,
bool flg_m,
bool flg_g,
uint32_t flg_bpp
)
{ {
uint32_t block_mask; uint32_t block_mask = 0xffffffff;
uint32_t end_addr; uint32_t end_addr = base_addr + size - 1;
/* /* Determine block mask, that overlaps the whole block */
* determine block mask, that overlaps the whole block
*/
end_addr = base_addr+size-1;
block_mask = 0xffffffff;
while ((end_addr & block_mask) != (base_addr & block_mask)) { while ((end_addr & block_mask) != (base_addr & block_mask)) {
block_mask <<= 1; block_mask <<= 1;
} }
bat_ptr->batu.bepi = base_addr >> (32-15); bat_ptr->batu.bepi = base_addr >> (32 - 15);
bat_ptr->batu.bl = ~(block_mask >> (28-11)); bat_ptr->batu.bl = ~(block_mask >> (28 - 11));
bat_ptr->batu.vs = 1; bat_ptr->batu.vs = 1;
bat_ptr->batu.vp = 1; bat_ptr->batu.vp = 1;
bat_ptr->batl.brpn = base_addr >> (32-15); bat_ptr->batl.brpn = base_addr >> (32 - 15);
bat_ptr->batl.w = flg_w; bat_ptr->batl.w = flg_w;
bat_ptr->batl.i = flg_i; bat_ptr->batl.i = flg_i;
bat_ptr->batl.m = flg_m; bat_ptr->batl.m = flg_m;
bat_ptr->batl.g = flg_g; bat_ptr->batl.g = flg_g;
bat_ptr->batl.pp = flg_bpp; bat_ptr->batl.pp = flg_bpp;
} }
static void clear_mmu_regs(void) static void clear_mmu_regs( void)
{ {
uint32_t i; uint32_t i;
/*
* clear segment registers /* Clear segment registers */
*/
for (i = 0;i < 16;i++) { for (i = 0;i < 16;i++) {
asm volatile(" mtsrin %0, %1\n"::"r" (i * 0x1000),"r"(i<<(31-3))); asm volatile( "mtsrin %0, %1\n" : : "r" (i * 0x1000), "r" (i << (31 - 3)));
} }
/*
* clear TLBs /* Clear TLBs */
*/
for (i = 0;i < 32;i++) { for (i = 0;i < 32;i++) {
asm volatile(" tlbie %0\n"::"r" (i << (31-19))); asm volatile( "tlbie %0\n" : : "r" (i << (31 - 19)));
} }
} }
void cpu_init(void) void cpu_init( void)
{ {
register unsigned long reg; BAT dbat, ibat;
BAT dbat,ibat; uint32_t msr;
/* /* Clear MMU and segment registers */
* clear MMU/Segment registers
*/
clear_mmu_regs(); clear_mmu_regs();
/*
* clear caches /* Clear caches */
*/ PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ILOCK | HID0_DLOCK);
GET_HID0(reg); PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);
reg = (reg & ~(HID0_ILOCK | HID0_DLOCK)) | HID0_ICFI | HID0_DCI; PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);
SET_HID0(reg);
reg &= ~(HID0_ICFI | HID0_DCI);
SET_HID0(reg);
/* /*
* set up IBAT registers in MMU * Set up IBAT registers in MMU
*/ */
memset(&ibat,0,sizeof(ibat));
SET_IBAT(2,ibat.batu,ibat.batl);
SET_IBAT(3,ibat.batu,ibat.batl);
SET_IBAT(4,ibat.batu,ibat.batl);
SET_IBAT(5,ibat.batu,ibat.batl);
SET_IBAT(6,ibat.batu,ibat.batl);
SET_IBAT(7,ibat.batu,ibat.batl);
#ifdef HAS_UBOOT
calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RX);
#else /* HAS_UBOOT */
calc_dbat_regvals(&ibat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RX);
#endif /* HAS_UBOOT */
SET_IBAT(0,ibat.batu,ibat.batl); memset(&ibat, 0, sizeof( ibat));
SET_IBAT( 2, ibat.batu, ibat.batl);
SET_IBAT( 3, ibat.batu, ibat.batl);
SET_IBAT( 4, ibat.batu, ibat.batl);
SET_IBAT( 5, ibat.batu, ibat.batl);
SET_IBAT( 6, ibat.batu, ibat.batl);
SET_IBAT( 7, ibat.batu, ibat.batl);
#ifdef HAS_UBOOT calc_dbat_regvals(
calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX); &ibat,
#else /* HAS_UBOOT */ #ifdef HAS_UBOOT
calc_dbat_regvals(&ibat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX); mpc83xx_uboot_board_info.bi_memstart,
#endif /* HAS_UBOOT */ mpc83xx_uboot_board_info.bi_memsize,
#else /* HAS_UBOOT */
(uint32_t) bsp_ram_start,
(uint32_t) bsp_ram_size,
#endif /* HAS_UBOOT */
false,
false,
false,
false,
BPP_RX
);
SET_IBAT( 0, ibat.batu, ibat.batl);
SET_IBAT(1,ibat.batu,ibat.batl); calc_dbat_regvals(
&ibat,
#ifdef HAS_UBOOT
mpc83xx_uboot_board_info.bi_flashstart,
mpc83xx_uboot_board_info.bi_flashsize,
#else /* HAS_UBOOT */
(uint32_t) bsp_rom_start,
(uint32_t) bsp_rom_size,
#endif /* HAS_UBOOT */
false,
false,
false,
false,
BPP_RX
);
SET_IBAT( 1, ibat.batu, ibat.batl);
/* /*
* set up DBAT registers in MMU * Set up DBAT registers in MMU
*/ */
memset(&dbat,0,sizeof(dbat));
SET_DBAT(3,dbat.batu,dbat.batl);
SET_DBAT(4,dbat.batu,dbat.batl);
SET_DBAT(5,dbat.batu,dbat.batl);
SET_DBAT(6,dbat.batu,dbat.batl);
SET_DBAT(7,dbat.batu,dbat.batl);
#ifdef HAS_UBOOT memset(&dbat, 0, sizeof( dbat));
calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RW); SET_DBAT( 3, dbat.batu, dbat.batl);
#else /* HAS_UBOOT */ SET_DBAT( 4, dbat.batu, dbat.batl);
calc_dbat_regvals(&dbat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RW); SET_DBAT( 5, dbat.batu, dbat.batl);
#endif /* HAS_UBOOT */ SET_DBAT( 6, dbat.batu, dbat.batl);
SET_DBAT( 7, dbat.batu, dbat.batl);
SET_DBAT(0,dbat.batu,dbat.batl); calc_dbat_regvals(
&dbat,
#ifdef HAS_UBOOT
mpc83xx_uboot_board_info.bi_memstart,
mpc83xx_uboot_board_info.bi_memsize,
#else /* HAS_UBOOT */
(uint32_t) bsp_ram_start,
(uint32_t) bsp_ram_size,
#endif /* HAS_UBOOT */
false,
false,
false,
false,
BPP_RW
);
SET_DBAT( 0, dbat.batu, dbat.batl);
#ifdef HAS_UBOOT calc_dbat_regvals(
calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX); &dbat,
#else /* HAS_UBOOT */ #ifdef HAS_UBOOT
calc_dbat_regvals(&dbat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX); mpc83xx_uboot_board_info.bi_flashstart,
#endif /* HAS_UBOOT */ mpc83xx_uboot_board_info.bi_flashsize,
#else /* HAS_UBOOT */
(uint32_t) bsp_rom_start,
(uint32_t) bsp_rom_size,
#endif /* HAS_UBOOT */
false,
false,
false,
false,
BPP_RX
);
SET_DBAT( 1, dbat.batu, dbat.batl);
SET_DBAT(1,dbat.batu,dbat.batl); calc_dbat_regvals(
&dbat,
#ifdef HAS_UBOOT #ifdef HAS_UBOOT
calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_immrbar,1024*1024,0,1,0,1,BPP_RW); mpc83xx_uboot_board_info.bi_immrbar,
#else /* HAS_UBOOT */ #else /* HAS_UBOOT */
calc_dbat_regvals(&dbat,(uint32_t) IMMRBAR,1024*1024,0,1,0,1,BPP_RW); (uint32_t) IMMRBAR,
#endif /* HAS_UBOOT */ #endif /* HAS_UBOOT */
1024 * 1024,
SET_DBAT(2,dbat.batu,dbat.batl); false,
true,
false,
true,
BPP_RW
);
SET_DBAT( 2, dbat.batu, dbat.batl);
#ifdef MPC8313ERDB #ifdef MPC8313ERDB
/* Enhanced Local Bus Controller (eLBC) */ /* Enhanced Local Bus Controller (eLBC) */
calc_dbat_regvals( &dbat, 0xfa000000, 128 * 1024, 0, 1, 0, 1, BPP_RW); calc_dbat_regvals(
&dbat,
0xfa000000,
128 * 1024,
false,
true,
false,
true,
BPP_RW
);
SET_DBAT( 3, dbat.batu, dbat.batl); SET_DBAT( 3, dbat.batu, dbat.batl);
#endif /* MPC8313ERDB */ #endif /* MPC8313ERDB */
/* /* Read MSR */
* enable data/instruction MMU in MSR msr = ppc_machine_state_register();
*/
_write_MSR(_read_MSR() | MSR_DR | MSR_IR); /* Enable data and instruction MMU in MSR */
msr |= MSR_DR | MSR_IR;
/* Enable FPU in MSR */
msr |= MSR_FP;
/* Update MSR */
ppc_set_machine_state_register( msr);
/* /*
* enable FPU in MSR * In HID0:
* - Enable dynamic power management
* - Enable machine check interrupts
*/ */
_write_MSR(_read_MSR() | MSR_FP); PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_EMCP | HID0_DPM);
/* /* Enable timebase clock */
* in HID0:
* - enable dynamic power management
* - enable machine check interrupts
*/
GET_HID0(reg);
reg |= (HID0_EMCP | HID0_DPM) ;
SET_HID0(reg);
/*
* enable timebase clock
*/
mpc83xx.syscon.spcr |= M83xx_SYSCON_SPCR_TBEN; mpc83xx.syscon.spcr |= M83xx_SYSCON_SPCR_TBEN;
} }