RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

bsp/mpc5200: Fix cache handling

Browse Source
This commit is contained in:
Sebastian Huber
2013-04-17 16:03:03 +02:00
parent 47fb2fed19
commit d5587f9f3b
2 changed files with 6 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c
View File

@@ -165,16 +165,6 @@ void bsp_start(void)
bsp_time_base_frequency = XLB_CLOCK / 4; bsp_time_base_frequency = XLB_CLOCK / 4;
bsp_clicks_per_usec = (XLB_CLOCK/4000000); bsp_clicks_per_usec = (XLB_CLOCK/4000000);
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
#if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
/* Initialize exception handler */ /* Initialize exception handler */
ppc_exc_cache_wb_check = 0; ppc_exc_cache_wb_check = 0;
ppc_exc_initialize( ppc_exc_initialize(

14
c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
View File

@@ -290,8 +290,9 @@ void cpu_init(void)
{ {
uint32_t msr; uint32_t msr;
/* Enable instruction cache */ #if BSP_INSTRUCTION_CACHE_ENABLED
PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICE); rtems_cache_enable_instruction();
#endif
/* Set up DBAT registers in MMU */ /* Set up DBAT registers in MMU */
cpu_init_bsp(); cpu_init_bsp();
@@ -311,10 +312,7 @@ void cpu_init(void)
/* Update MSR */ /* Update MSR */
ppc_set_machine_state_register( msr); ppc_set_machine_state_register( msr);
/* #if BSP_DATA_CACHE_ENABLED
* Enable data cache. rtems_cache_enable_data();
* #endif
* NOTE: TRACE32 now supports data cache for MGT5x00.
*/
PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_DCE);
} }