bsp/mpc5200: Fix cache handling

c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c

@@ -165,16 +165,6 @@ void bsp_start(void)
   bsp_time_base_frequency = XLB_CLOCK / 4;
   bsp_clicks_per_usec    = (XLB_CLOCK/4000000);
 
-  /*
-   * Enable instruction and data caches. Do not force writethrough mode.
-   */
-  #if BSP_INSTRUCTION_CACHE_ENABLED
-    rtems_cache_enable_instruction();
-  #endif
-  #if BSP_DATA_CACHE_ENABLED
-    rtems_cache_enable_data();
-  #endif
-
   /* Initialize exception handler */
   ppc_exc_cache_wb_check = 0;
   ppc_exc_initialize(

c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c

@@ -290,8 +290,9 @@ void cpu_init(void)
 {
   uint32_t msr;
 
-  /* Enable instruction cache */
-  PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICE);
+  #if BSP_INSTRUCTION_CACHE_ENABLED
+    rtems_cache_enable_instruction();
+  #endif
 
   /* Set up DBAT registers in MMU */
   cpu_init_bsp();
@@ -311,10 +312,7 @@ void cpu_init(void)
   /* Update MSR */
   ppc_set_machine_state_register( msr);
 
-  /*
-   * Enable data cache.
-   *
-   * NOTE: TRACE32 now supports data cache for MGT5x00.
-   */
-  PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_DCE);
+  #if BSP_DATA_CACHE_ENABLED
+    rtems_cache_enable_data();
+  #endif
 }