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Patch from John M. Mills <jmills@tga.com> to do some cleanup and use

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-O4 at both debug and optimized levels.  There is still a speed setting
problem but the sample tests run.
This commit is contained in:
Joel Sherrill
2000-04-28 19:51:00 +00:00
parent a06c5f5b22
commit d554ca0bf9
6 changed files with 107 additions and 92 deletions
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15
c/src/lib/libbsp/sh/gensh2/README
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@@ -49,9 +49,12 @@ NOTES
(1) Only stub console driver available at the moment.
Driver for the on-chip serial devices (sci) will be available soon.
(2) The present 'hw_init.c' file is incomplete and does not set all
registers required for serial I/O. The effect is that the sci devices
are 'muted' and do not successfully transmit characters to the respective
I/O lines on the SH7045F. If these ports have been properly initialized,
they are not disabled by the current code. A two-part initialization will
be available soon.
(2) The present 'hw_init.c' file provides 'early_hw_init'(void) which
is normally called from 'start.S' to provide such minimal HW setup
as is conveniently written in 'C' and can make use of global
symbols for 7045F processor elements. It also provides
'void bsp_hw_init (void)' normally called from 'bspstart.c', shortly
before RTEMS itself is started.
These are both minimal functions intended to support the RTEMS test
suites.

14
c/src/lib/libbsp/sh/gensh2/start/start.S
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@@ -44,7 +44,7 @@ SYM (start):
! Initialize minimal hardware
mov.l hw_init_k, r0
jsr @r0
nop !debug dead-slot target
nop !dead slot
#endif /* START_HW_INIT */
! zero out bss
@@ -56,7 +56,6 @@ SYM (start):
add #4,r0
cmp/ge r0,r1
bt 0b
nop !debug dead-slot target
! copy the vector table from rom to ram
mov.l vects_k,r0 ! vectab
@@ -70,8 +69,8 @@ SYM (start):
add #1,r2
cmp/hi r3,r2
bf 1b
nop !debug dead-slot target
#ifndef STANDALONE_EVB
! overlay monitor vectors onto RTEMS table template
! code adapted from Hitachi EDK7045F User Manual: "Copyvect.s"
mova vects_k,r0
@@ -135,20 +134,19 @@ SYM (start):
mov.l r3, @r0
mov.l vects_k,r0 ! point vbr to vectab
ldc r0,vbr
#endif ! STANDALONE_EVB
! call the mainline
mov #0,r4 ! argc
mov #0,r5 ! argv - can place in dead slot
mov.l main_k,r0
jsr @r0
nop !debug dead-slot target
mov #0,r5 ! argv - can place in dead slot
! call exit
mov r0,r4
mov.l exit_k,r0
or r0,r0
jsr @r0
nop !debug dead-slot target
or r0,r0
mov.l vbrtemp_k,r0 ! restore original vbr
mov.l @r0,r3
@@ -171,7 +169,7 @@ exit_k:
.long SYM(exit)
#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */
hw_init_k:
.long SYM(hw_initialize)
.long SYM(early_hw_init)
#endif /* START_HW_INIT */
vbrtemp_k:
.long SYM(vbrtemp)

4
c/src/lib/libbsp/sh/gensh2/startup/bspstart.c
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@@ -37,7 +37,7 @@
* some changes.
*/
extern void hw_initialize(void);
extern void bsp_hw_init(void);
extern rtems_configuration_table Configuration;
@@ -94,7 +94,7 @@ void bsp_start(void)
#ifndef START_HW_INIT
/* board hardware setup here, or from 'start.S' */
hw_initialize();
bsp_hw_init();
#endif
/*

124
c/src/lib/libbsp/sh/gensh2/startup/hw_init.c
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@@ -3,8 +3,14 @@
* Pin and memory assignments assume
* target is Hitachi SH7045F EVB ("lcevb")
*
* Provides two initialization routines:
* A. 'void early_hw_init(void)' for 'start.S'
* sets up hw needed for early RTEMS boot, and
* B. 'void bsp_hw_init(void)' for 'bspstart.c'
* sets up hardware used by this BSP.
*
* Author: John M. Mills (jmills@tga.com)
* COPYRIGHT(c) 1999, TGA Technologies, Inc
* COPYRIGHT(c) 2000, TGA Technologies, Inc
* Norcross, GA 30071 U.S.A
*
* This program is distributed in the hope that it will be useful,
@@ -40,74 +46,72 @@
#include <rtems/score/sh_io.h>
#include <rtems/score/iosh7045.h>
/* exported entry */
extern void hw_initialize (void);
/* exported entries */
extern void bsp_hw_init (void);
extern void early_hw_init (void);
/* STANDALONE_EVB sets up bus, DRAM, PFC, and SCI0 */
/* no STANDALONE_EVB accepts defaults, adds RESET, SCI1, WDT */
/***************************************************/
/* Inline function to access CPU features */
/* from C. This makes use of GNU extensions. */
/***************************************************/
__inline__ void set_interrupt_mask(unsigned char mask)
/* called from 'start.S' on "#ifdef START_HW_INIT" */
void early_hw_init (void)
{
asm("mov.l r0,@-r15");
asm("mov %0,r0"::"r"(mask));
asm("and #0xF,r0");
asm("rotl r0");
asm("rotl r0");
asm("rotl r0");
asm("rotl r0");
asm("ldc r0,sr");
asm("mov.l @r15+,r0");
}
void hw_initialize (void)
{
int a;
unsigned8 temp8;
unsigned16 temp16;
#ifdef STANDALONE_EVB
/* FIXME: replace 'magic numbers' */
/* STANDALONE_EVB minimally sets up bus and DRAM here */
/* no STANDALONE_EVB accepts defaults from debug monitor */
write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */
write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/
write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */
write16(0x000F, BSC_WCR2); /* Waits for DRAM/DMA access - default */
write16(0x0000, BSC_DCR); /* DRAM control - default */
write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */
write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/
write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */
write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */
write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */
write16(0x0000, PFC_PBCR1); /* Pin function controller - default */
write16(0x2005, PFC_PBCR2); /* Pin function controller - A18,A17,A16 */
write16(0xFFFF, PFC_PCCR); /* Pin function controller - A15-A0 */
write16(0x5555, PFC_PDCRH1; /* Pin function controller - D31-D24 */
write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */
write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0 */
write16(0x0000, PFC_IFCR); /* Pin function controller - default */
write16(0x0005, PFC_PACRL2); /* Pin function controller - Tx0, Rx0 */
/* FIXME: replace 'magic numbers' with logical names */
write16(0x00, PFC_PACRL2); /* default disconnects all I/O */
/* pins; connected by DEVICE_open() */
write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */
write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/
write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */
write16(0x000F, BSC_WCR2); /* Waits for DRAM/DMA access - default */
write16(0x0000, BSC_DCR); /* DRAM control - default */
write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */
write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/
write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */
#endif
/* default hardware setup for SH7045F EVB */
/* add early-init functions here */
/* PFC: General I/O except pin 13 (reset): */
temp16 = read16(PFC_PECR1) | 0x0800;
write16(temp16, PFC_PECR1);
};
/* All I/O lines bits 7-0: */
write16(0x00, PFC_PECR2);
/* to be called from 'bspstart.c' */
void bsp_hw_init (void)
{
int a;
unsigned8 temp8;
unsigned16 temp16;
/* P5 (LED) out, all other pins in: */
temp16 = read16(PFC_PEIOR) | 0x0020;
write16(temp16, PFC_PEIOR);
#ifdef STANDALONE_EVB
/* STANDALONE_EVB: sets up PFC */
/* no STANDALONE_EVB: accepts defaults, adds RESET */
/* FIXME: replace 'magic numbers' */
write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */
write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */
write16(0x0000, PFC_PBCR1); /* Pin function controller - default */
write16(0x2005, PFC_PBCR2); /* Pin fcn. controller - A18,A17,A16 */
write16(0xFFFF, PFC_PCCR); /* Pin function controller - A15-A0 */
write16(0x5555, PFC_PDCRH1); /* Pin function controller - D31-D24 */
write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */
write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0 */
write16(0x0000, PFC_IFCR); /* Pin function controller - default */
write16(0x0000, PFC_PACRL2); /* default disconnects all I/O pins;*/
/* [re-connected by DEVICE_open()] */
#endif
/* default hardware setup for SH7045F EVB */
/* PFC: General I/O except pin 13 (reset): */
temp16 = read16(PFC_PECR1);
temp16 |= 0x0800;
write16(temp16, PFC_PECR1);
/* All I/O lines bits 7-0: */
write16(0x00, PFC_PECR2);
/* P5 (LED) out, all other pins in: */
temp16 = read16(PFC_PEIOR);
temp16 |= 0x0020;
write16(temp16, PFC_PEIOR);
}

27
c/src/lib/libcpu/sh/sh7045/sci/sci.c
View File

@@ -51,7 +51,7 @@
#include <rtems/score/iosh7045.h>
#include <sh/sh7_sci.h>
#include <sh/sh7_pfc.h>
/* #include <sh/io_types.h> */
#include <sh/sci.h>
#ifndef STANDALONE_EVB
@@ -330,18 +330,18 @@ rtems_device_driver sh_sci_open(
return RTEMS_SUCCESSFUL ;
}
/* enable I/O pins */
/* set PFC registers to enable I/O pins */
if ((minor == 0) && (STANDALONE_EVB == 1)) {
temp16 = read16(PFC_PACRL2) & /* disable SCK0, Tx0, Rx0 */
~(PA2MD1 | PA2MD0 | PA1MD0 | PA0MD0);
temp16 |= (PA_TXD0 | PA_RXD0); /* assign pins for Tx0, Rx0 */
temp16 = read16(PFC_PACRL2); /* disable SCK0, DMA, IRQ */
temp16 &= ~(PA2MD1 | PA2MD0);
temp16 |= (PA_TXD0 | PA_RXD0); /* enable pins for Tx0, Rx0 */
write16(temp16, PFC_PACRL2);
} else if (minor == 1) {
temp16 = read16(PFC_PACRL2) & /* disable SCK1, Tx1, Rx1 */
~(PA5MD1 | PA5MD0 | PA4MD0 | PA3MD0);
temp16 |= (PA_TXD1 | PA_RXD1); /* assign pins for Tx1, Rx1 */
temp16 = read16(PFC_PACRL2); /* disable SCK1, DMA, IRQ */
temp16 &= ~(PA5MD1 | PA5MD0);
temp16 |= (PA_TXD1 | PA_RXD1); /* enable pins for Tx1, Rx1 */
write16(temp16, PFC_PACRL2);
} /* add other devices and pins as req'd. */
@@ -349,16 +349,23 @@ rtems_device_driver sh_sci_open(
/* set up SCI registers */
if ((minor != 0) || (STANDALONE_EVB == 1)) {
write8(0x00, sci_device[minor].addr + SCI_SCR); /* Clear SCR */
/* set SCR and BRR */
/* set SMR and BRR */
_sci_set_cflags( &sci_device[minor], sci_device[minor].cflags );
for(a=0; a < 10000L; a++) { /* One-bit delay */
for(a=0; a < 10000L; a++) { /* Delay */
asm volatile ("nop");
}
write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */
sci_device[minor].addr + SCI_SCR);
temp8 = read8(sci_device[minor].addr + SCI_RDR); /* flush input */
/* Clear RDRF flag */
temp8= read8(sci_device[minor].addr + SCI_SSR) & ~SCI_RDRF;
write8(temp8, sci_device[minor].addr + SCI_SSR);
write8(0x00, sci_device[minor].addr + SCI_TDR); /* force output */
/* Clear the TDRE bit */
temp8 = read8(sci_device[minor].addr + SCI_SSR) & ~SCI_TDRE;
write8(temp8, sci_device[minor].addr + SCI_SSR);
/* add interrupt setup if required */