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bsps/riscv: Fix PLIC enable register count

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This commit is contained in:
Sebastian Huber
2022-11-23 07:49:53 +01:00
parent 733d9b750c
commit d448aa4d05
1 changed files with 5 additions and 3 deletions
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8
bsps/riscv/riscv/irq/irq.c
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@@ -268,10 +268,12 @@ static void riscv_plic_init(const void *fdt)
uint32_t cpu_index; uint32_t cpu_index;
/* /*
* Interrupt enable registers with 32-bit alignment based on * Each interrupt enable register contains exactly 32 enable bits.
* number of interrupts. * Calculate the enable register count based on the number of interrupts
* supported by the PLIC. Take the reserved interrupt ID zero into
* account.
*/ */
enable_register_count = RTEMS_ALIGN_UP(ndev, 32) / 32; enable_register_count = RTEMS_ALIGN_UP(ndev + 1, 32) / 32;
hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4])); hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));