forked from Imagelibrary/rtems
Changed special purpose register inline functions to macros.
fixed some minors in mpc83xx support added file for mpc55xx watchdog support
This commit is contained in:
Thomas Doerfler
@@ -239,184 +239,176 @@ static inline void ppc_set_decrementer_register( uint32_t dec)
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PPC_Set_decrementer( dec);
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}
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#define PPC_STRINGOF(x) #x
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/* Do not use the following macros. Use the inline functions instead. */
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#define PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER( spr) \
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uint32_t val; \
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asm volatile ( \
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"mfspr %0, " #spr \
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: "=r" (val) \
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); \
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return val;
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#define PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( spr) \
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER( spr)
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#define PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER( spr, val) \
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asm volatile ( \
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"mtspr " #spr ", %0" \
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: \
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: "r" (val) \
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);
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#define PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( spr, val) \
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER( spr, val)
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/*
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* PPC4xx have Device Control Registers...
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/**
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* @brief Preprocessor magic for stringification of @a x.
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*/
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#define PPC_DEVICE_CONTROL_REGISTER(dcr) \
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({uint32_t val;asm volatile ("mfdcr %0," PPC_STRINGOF(dcr) \
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: "=r" (val)); val;})
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#define PPC_STRINGOF( x) #x
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#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr,val) \
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do { \
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asm volatile ("mtdcr " PPC_STRINGOF(dcr)",%0" \
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:: "r" (val)); \
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} while (0)
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/**
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* @brief Returns the value of the Special Purpose Register with number @a spr.
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*
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* @note This macro uses a GNU C extension.
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*/
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#define PPC_SPECIAL_PURPOSE_REGISTER( spr) \
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( { \
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uint32_t val; \
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asm volatile ( \
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"mfspr %0, " PPC_STRINGOF( spr) \
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: "=r" (val) \
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); \
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val;\
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} )
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/**
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* @brief Sets the Special Purpose Register with number @a spr to the value in
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* @a val.
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*/
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#define PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val) \
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do { \
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asm volatile ( \
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"mtspr " PPC_STRINGOF( spr) ", %0" \
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: \
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: "r" (val) \
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); \
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} while (0)
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static inline uint32_t ppc_special_purpose_register_0()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0);
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}
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/**
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* @brief Sets in the Special Purpose Register with number @a spr all bits
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* which are set in @a bits.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( spr, bits) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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rtems_interrupt_disable( level); \
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val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \
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val |= bits; \
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PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \
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rtems_interrupt_enable( level); \
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} while (0)
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static inline void ppc_set_special_purpose_register_0( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0, val);
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}
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/**
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* @brief Sets in the Special Purpose Register with number @a spr all bits
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* which are set in @a bits. The previous register value will be masked with
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* @a mask.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED( spr, bits, mask) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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rtems_interrupt_disable( level); \
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val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \
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val &= ~mask; \
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val |= bits; \
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PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \
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rtems_interrupt_enable( level); \
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} while (0)
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static inline uint32_t ppc_special_purpose_register_1()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1);
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}
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/**
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* @brief Clears in the Special Purpose Register with number @a spr all bits
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* which are set in @a bits.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( spr, bits) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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rtems_interrupt_disable( level); \
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val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \
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val &= ~bits; \
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PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \
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rtems_interrupt_enable( level); \
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} while (0)
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static inline void ppc_set_special_purpose_register_1( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1, val);
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}
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/**
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* @brief Returns the value of the Device Control Register with number @a dcr.
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*
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* The PowerPC 4XX family has Device Control Registers.
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*
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* @note This macro uses a GNU C extension.
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*/
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#define PPC_DEVICE_CONTROL_REGISTER( dcr) \
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( { \
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uint32_t val; \
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asm volatile ( \
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"mfdcr %0, " PPC_STRINGOF( dcr) \
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: "=r" (val) \
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); \
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val;\
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} )
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static inline uint32_t ppc_special_purpose_register_2()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2);
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}
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/**
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* @brief Sets the Device Control Register with number @a dcr to the value in
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* @a val.
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*
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* The PowerPC 4XX family has Device Control Registers.
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*/
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#define PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val) \
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do { \
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asm volatile ( \
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"mtdcr " PPC_STRINGOF( dcr) ", %0" \
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: \
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: "r" (val) \
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); \
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} while (0)
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static inline void ppc_set_special_purpose_register_2( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2, val);
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}
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/**
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* @brief Sets in the Device Control Register with number @a dcr all bits
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* which are set in @a bits.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS( dcr, bits) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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rtems_interrupt_disable( level); \
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val = PPC_DEVICE_CONTROL_REGISTER( dcr); \
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val |= bits; \
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PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \
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rtems_interrupt_enable( level); \
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} while (0)
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static inline uint32_t ppc_special_purpose_register_3()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3);
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}
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/**
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* @brief Sets in the Device Control Register with number @a dcr all bits
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* which are set in @a bits. The previous register value will be masked with
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* @a mask.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED( dcr, bits, mask) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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rtems_interrupt_disable( level); \
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val = PPC_DEVICE_CONTROL_REGISTER( dcr); \
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val &= ~mask; \
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val |= bits; \
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PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \
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rtems_interrupt_enable( level); \
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} while (0)
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static inline void ppc_set_special_purpose_register_3( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3, val);
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}
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static inline uint32_t ppc_special_purpose_register_4()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4);
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}
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static inline void ppc_set_special_purpose_register_4( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4, val);
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}
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static inline uint32_t ppc_special_purpose_register_5()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5);
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}
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static inline void ppc_set_special_purpose_register_5( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5, val);
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}
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static inline uint32_t ppc_special_purpose_register_6()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6);
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}
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static inline void ppc_set_special_purpose_register_6( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6, val);
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}
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static inline uint32_t ppc_special_purpose_register_7()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7);
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}
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static inline void ppc_set_special_purpose_register_7( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7, val);
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}
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static inline uint32_t ppc_user_special_purpose_register_0()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0);
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}
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static inline void ppc_set_user_special_purpose_register_0( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0, val);
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}
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static inline uint32_t ppc_timer_control_register()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR);
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}
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static inline void ppc_set_timer_control_register( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR, val);
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}
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static inline uint32_t ppc_timer_status_register()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR);
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}
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static inline void ppc_set_timer_status_register( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR, val);
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}
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static inline uint32_t ppc_decrementer_auto_reload_register()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR);
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}
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static inline void ppc_set_decrementer_auto_reload_register( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR, val);
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}
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static inline uint32_t ppc_hardware_implementation_dependent_register_0()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0);
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}
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static inline void ppc_set_hardware_implementation_dependent_register_0( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0, val);
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}
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static inline uint32_t ppc_hardware_implementation_dependent_register_1()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1);
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}
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static inline void ppc_set_hardware_implementation_dependent_register_1( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1, val);
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}
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/**
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* @brief Clears in the Device Control Register with number @a dcr all bits
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* which are set in @a bits.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS( dcr, bits) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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rtems_interrupt_disable( level); \
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val = PPC_DEVICE_CONTROL_REGISTER( dcr); \
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val &= ~bits; \
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PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \
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rtems_interrupt_enable( level); \
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} while (0)
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static inline uint32_t ppc_time_base()
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{
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@@ -429,17 +421,17 @@ static inline uint32_t ppc_time_base()
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static inline void ppc_set_time_base( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWL, val);
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PPC_SET_SPECIAL_PURPOSE_REGISTER( TBWL, val);
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}
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static inline uint32_t ppc_time_base_upper()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( TBRU);
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return PPC_SPECIAL_PURPOSE_REGISTER( TBRU);
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}
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static inline void ppc_set_time_base_upper( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWU, val);
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PPC_SET_SPECIAL_PURPOSE_REGISTER( TBWU, val);
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}
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static inline uint64_t ppc_time_base_64()
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@@ -457,18 +449,18 @@ static inline void ppc_set_time_base_64( uint64_t val)
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#include <rtems/asm.h>
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.macro LA reg, addr
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lis \reg, (\addr)@h
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ori \reg, \reg, (\addr)@l
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lis \reg, (\addr)@h
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ori \reg, \reg, (\addr)@l
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.endm
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.macro LWI reg, value
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lis \reg, (\value)@h
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ori \reg, \reg, (\value)@l
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ori \reg, \reg, (\value)@l
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.endm
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.macro LW reg, addr
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lis \reg, \addr@ha
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lwz \reg, \addr@l(\reg)
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lis \reg, \addr@ha
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lwz \reg, \addr@l(\reg)
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.endm
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/*
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@@ -502,7 +494,7 @@ static inline void ppc_set_time_base_64( uint64_t val)
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* Obtain interrupt mask
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*/
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.macro GET_INTERRUPT_MASK mask
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mfspr \mask, sprg0
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mfspr \mask, sprg0
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.endm
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/*
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