RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2002-11-01 Andy Dachs <a.dachs@sstl.co.uk>

Browse Source 
* irq/irq.c, irq/irq_asm.S, irq/irq_init.c: Per PR288, add support
	for _ISR_Nest_level.
This commit is contained in:
Joel Sherrill
2002-11-01 14:21:47 +00:00
parent 7df02840d5
commit d36d3a3c0c
4 changed files with 473 additions and 366 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog
View File

@@ -1,3 +1,8 @@
2002-11-01 Andy Dachs <a.dachs@sstl.co.uk>
* irq/irq.c, irq/irq_asm.S, irq/irq_init.c: Per PR288, add support
for _ISR_Nest_level.
2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Reformat.

231
c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c
View File

@@ -6,7 +6,9 @@
*
* Modified for mpc8260 Andy Dachs <a.dachs@sstl.co.uk>
* Surrey Satellite Technology Limited, 2000
* Nested exception handlers not working yet.
+ * 21/4/2002 Added support for nested interrupts and improved
+ * masking operations. Now we compute priority mask based
+ * on table in irq_init.c
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
@@ -15,16 +17,14 @@
* $Id$
*/
#include <rtems/system.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <rtems/score/thread.h>
#include <rtems/score/apiext.h>
#include <libcpu/raw_exception.h>
#include <bsp/vectors.h>
/*#include <bsp/8xx_immap.h>*/
#include <libcpu/cpu.h>
#include <mpc8260.h>
/*#include <bsp/commproc.h>*/
/*
* default handler connected on each irq after bsp initialization
@@ -59,32 +59,103 @@ static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
);
}
typedef struct {
rtems_unsigned32 mask_h; /* mask for sipnr_h and simr_h */
rtems_unsigned32 mask_l; /* mask for sipnr_l and simr_l */
rtems_unsigned32 priority_h; /* mask this and lower priority ints */
rtems_unsigned32 priority_l;
} m82xxIrqMasks_t;
/*
* bit in the SIU mask registers (PPC bit numbering) that should
* be set to enable the relevant interrupt
*
* Mask fields should have a '1' in the bit position for that
* interrupt.
* Priority masks calculated later based on priority table
*/
const static unsigned int SIU_MaskBit[BSP_CPM_IRQ_NUMBER] =
static m82xxIrqMasks_t SIU_MaskBit[BSP_CPM_IRQ_NUMBER] =
{
63, 48, 49, 50, /* err, i2c, spi, rtt */
51, 52, 53, 54, /* smc1, smc2, idma1, idma2 */
55, 56, 57, 63, /* idma3, idma4, sdma, - */
59, 60, 61, 62, /* tmr1, tmr2, tmr3, tmr4 */
29, 30, 63, 17, /* pit, tmcnt, -, irq1 */
18, 19, 20, 21, /* irq2, irq3, irq4, irq5 */
22, 23, 63, 63, /* irq6, irq7, -, - */
63, 63, 63, 63, /* -, -, -, - */
32, 33, 34, 35, /* fcc1, fcc2, fcc3, - */
36, 37, 38, 39, /* mcc1, mcc2, -, - */
40, 41, 42, 43, /* scc1, scc2, scc3, scc4 */
44, 45, 46, 47, /* -, -, -, - */
0, 1, 2, 3, /* pc0, pc1, pc2, pc3 */
4, 5, 6, 7, /* pc4, pc5, pc6, pc7 */
8, 9, 10, 11, /* pc8, pc9, pc10, pc11 */
12, 13, 14, 15 /* pc12, pc13, pc14, pc15 */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* err */
{ 0x00000000, 0x00008000, 0x00000000, 0x00000000 }, /* i2c */
{ 0x00000000, 0x00004000, 0x00000000, 0x00000000 }, /* spi */
{ 0x00000000, 0x00002000, 0x00000000, 0x00000000 }, /* rtt */
{ 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* smc1 */
{ 0x00000000, 0x00000800, 0x00000000, 0x00000000 }, /* smc2 */
{ 0x00000000, 0x00000400, 0x00000000, 0x00000000 }, /* idma1 */
{ 0x00000000, 0x00000200, 0x00000000, 0x00000000 }, /* idma2 */
{ 0x00000000, 0x00000100, 0x00000000, 0x00000000 }, /* idma3 */
{ 0x00000000, 0x00000080, 0x00000000, 0x00000000 }, /* idma4 */
{ 0x00000000, 0x00000040, 0x00000000, 0x00000000 }, /* sdma */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* tmr1 */
{ 0x00000000, 0x00000008, 0x00000000, 0x00000000 }, /* tmr2 */
{ 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* tmr3 */
{ 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* tmr4 */
{ 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* tmcnt */
{ 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* pit */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* irq1 */
{ 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* irq2 */
{ 0x00001000, 0x00000000, 0x00000000, 0x00000000 }, /* irq3 */
{ 0x00000800, 0x00000000, 0x00000000, 0x00000000 }, /* irq4 */
{ 0x00000400, 0x00000000, 0x00000000, 0x00000000 }, /* irq5 */
{ 0x00000200, 0x00000000, 0x00000000, 0x00000000 }, /* irq6 */
{ 0x00000100, 0x00000000, 0x00000000, 0x00000000 }, /* irq7 */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x80000000, 0x00000000, 0x00000000 }, /* fcc1 */
{ 0x00000000, 0x40000000, 0x00000000, 0x00000000 }, /* fcc2 */
{ 0x00000000, 0x20000000, 0x00000000, 0x00000000 }, /* fcc3 */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x08000000, 0x00000000, 0x00000000 }, /* mcc1 */
{ 0x00000000, 0x04000000, 0x00000000, 0x00000000 }, /* mcc2 */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00800000, 0x00000000, 0x00000000 }, /* scc1 */
{ 0x00000000, 0x00400000, 0x00000000, 0x00000000 }, /* scc2 */
{ 0x00000000, 0x00200000, 0x00000000, 0x00000000 }, /* scc3 */
{ 0x00000000, 0x00100000, 0x00000000, 0x00000000 }, /* scc4 */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
{ 0x00010000, 0x00000000, 0x00000000, 0x00000000 }, /* pc15 */
{ 0x00020000, 0x00000000, 0x00000000, 0x00000000 }, /* pc14 */
{ 0x00040000, 0x00000000, 0x00000000, 0x00000000 }, /* pc13 */
{ 0x00080000, 0x00000000, 0x00000000, 0x00000000 }, /* pc12 */
{ 0x00100000, 0x00000000, 0x00000000, 0x00000000 }, /* pc11 */
{ 0x00200000, 0x00000000, 0x00000000, 0x00000000 }, /* pc10 */
{ 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* pc9 */
{ 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* pc8 */
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc7 */
{ 0x02000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc6 */
{ 0x04000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc5 */
{ 0x08000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc4 */
{ 0x10000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc3 */
{ 0x20000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc2 */
{ 0x40000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc1 */
{ 0x80000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc0 */
};
void dump_irq_masks(void )
{
int i;
for( i=0; i<BSP_CPM_IRQ_NUMBER;i++ )
{
printk( "%04d: %08X %08X\n",
i,
SIU_MaskBit[i].priority_h,
SIU_MaskBit[i].priority_l
);
}
}
/*
* ------------------------ RTEMS Irq helper functions ----------------
*/
@@ -97,10 +168,23 @@ const static unsigned int SIU_MaskBit[BSP_CPM_IRQ_NUMBER] =
static void compute_SIU_IvectMask_from_prio ()
{
/*
* In theory this is feasible. No time to code it yet. See i386/shared/irq.c
* for an example based on 8259 controller mask. The actual masks defined
* correspond to the priorities defined for the SIU in irq_init.c.
* The actual masks defined
* correspond to the priorities defined
* for the SIU in irq_init.c.
*/
int i,j;
for( i=0; i<BSP_CPM_IRQ_NUMBER; i++ )
{
for( j=0;j<BSP_CPM_IRQ_NUMBER; j++ )
if( internal_config->irqPrioTbl[j] < internal_config->irqPrioTbl[i] )
{
SIU_MaskBit[i].priority_h |= SIU_MaskBit[j].mask_h;
SIU_MaskBit[i].priority_l |= SIU_MaskBit[j].mask_l;
}
}
}
/*
@@ -124,11 +208,8 @@ int BSP_irq_enable_at_cpm(const rtems_irq_symbolic_name irqLine)
cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
if( SIU_MaskBit[cpm_irq_index] < 32 )
m8260.simr_h |= (0x80000000 >> SIU_MaskBit[cpm_irq_index]);
else
m8260.simr_l |= (0x80000000 >> (SIU_MaskBit[cpm_irq_index]-32));
m8260.simr_h |= SIU_MaskBit[cpm_irq_index].mask_h;
m8260.simr_l |= SIU_MaskBit[cpm_irq_index].mask_l;
return 0;
}
@@ -142,10 +223,8 @@ int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine)
cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
if( SIU_MaskBit[cpm_irq_index] < 32 )
m8260.simr_h &= ~(0x80000000 >> SIU_MaskBit[cpm_irq_index]);
else
m8260.simr_l &= ~(0x80000000 >> (SIU_MaskBit[cpm_irq_index]-32));
m8260.simr_h &= ~(SIU_MaskBit[cpm_irq_index].mask_h);
m8260.simr_l &= ~(SIU_MaskBit[cpm_irq_index].mask_l);
return 0;
@@ -160,10 +239,8 @@ int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine)
cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
if( SIU_MaskBit[cpm_irq_index] < 32 )
return m8260.simr_h & (0x80000000 >> SIU_MaskBit[cpm_irq_index]);
else
return m8260.simr_l & (0x80000000 >> (SIU_MaskBit[cpm_irq_index]-32));
return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) ||
(m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l));
}
@@ -205,13 +282,15 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
BSP_irq_enable_at_cpm (irq->name);
}
#if 0
if (is_processor_irq(irq->name)) {
/*
* Should Enable exception at processor level but not needed. Will restore
* EE flags at the end of the routine anyway.
*/
}
#endif
/*
* Enable interrupt on device
*/
@@ -219,9 +298,9 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
_CPU_ISR_Enable(level);
/*
/*
printk( "Enabled\n" );
*/
*/
return 1;
}
@@ -297,6 +376,9 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
default_rtems_entry = config->defaultEntry;
rtems_hdl_tbl = config->irqHdlTbl;
/* Fill in priority masks */
compute_SIU_IvectMask_from_prio();
_CPU_ISR_Disable(level);
/*
* start with CPM IRQ
@@ -305,8 +387,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
BSP_irq_enable_at_cpm (i);
rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
}
else {
} else {
rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
BSP_irq_disable_at_cpm (i);
}
@@ -318,11 +399,11 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) {
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
}
else {
} else {
rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
}
}
_CPU_ISR_Enable(level);
return 1;
}
@@ -337,6 +418,7 @@ int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
volatile unsigned int maxLoop = 0;
#endif
/*
* High level IRQ handler called from shared_raw_irq_code_entry
*/
@@ -348,6 +430,8 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
#endif
register unsigned msr;
register unsigned new_msr;
register unsigned old_simr_h;
register unsigned old_simr_l;
#ifdef DISPATCH_HANDLER_STAT
unsigned loopCounter;
#endif
@@ -358,10 +442,6 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
* Handle decrementer interrupt
*/
if (excNum == ASM_DEC_VECTOR) {
/*
_BSP_GPLED1_on();
*/
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
@@ -370,9 +450,6 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
_CPU_MSR_SET(msr);
/*
_BSP_GPLED1_off();
*/
return;
}
@@ -382,6 +459,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
#ifdef DISPATCH_HANDLER_STAT
loopCounter = 0;
#endif
while (1) {
if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) {
@@ -393,42 +471,40 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET;
/*
printk( "dispatching %d\n", irq );
*/
/* Clear pending register */
/* Clear mask and pending register */
if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) {
if( SIU_MaskBit[irq] < 32 )
m8260.sipnr_h = (0x80000000 >> SIU_MaskBit[irq]);
else
m8260.sipnr_l = (0x80000000 >> (SIU_MaskBit[irq]-32));
}
/* save interrupt masks */
old_simr_h = m8260.simr_h;
old_simr_l = m8260.simr_l;
/*
/* mask off current interrupt and lower priority ones */
m8260.simr_h &= SIU_MaskBit[irq].priority_h;
m8260.simr_l &= SIU_MaskBit[irq].priority_l;
/* clear pending bit */
m8260.sipnr_h |= SIU_MaskBit[irq].mask_h;
m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
/* re-enable external exceptions */
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
*/
/* call handler */
rtems_hdl_tbl[irq].hdl();
/*
/* disable exceptions again */
_CPU_MSR_SET(msr);
*/
/* restore interrupt masks */
m8260.simr_h = old_simr_h;
m8260.simr_l = old_simr_l;
#if 0
ppc_cached_irq_mask |= (oldMask & ~(SIU_IvectMask[irq]));
((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask;
#endif
}
#ifdef DISPATCH_HANDLER_STAT
++ loopCounter;
#endif
}
}
@@ -446,6 +522,7 @@ void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
_Thread_Executing->do_post_task_switch_extension = FALSE;
_API_extensions_Run_postswitch();
}
/*
* I plan to process other thread related events here.
* This will include DEBUG session requested from keyboard...

36
c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S
View File

@@ -9,15 +9,18 @@
* Modified to support the MCP750.
* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
*
* Modifications to store nesting level in global _ISR_Nest_level
* variable instead of SPRG0. Andy Dachs <a.dachs@sstl.co.uk>
*
* $Id$
*/
#include <asm.h>
#include <rtems/score/cpu.h>
#include <bsp/vectors.h>
#include <rtems/score/cpuopts.h> /* for PPC_HAS_FPU */
#include <rtems/score/cpu.h>
#include <libcpu/cpu.h>
#include <libcpu/raw_exception.h>
#include "asm.h"
#define SYNC \
sync; \
@@ -26,6 +29,7 @@
.text
.p2align 5
PUBLIC_VAR(decrementer_exception_vector_prolog_code)
SYM (decrementer_exception_vector_prolog_code):
@@ -84,7 +88,6 @@ SYM (shared_raw_irq_code_entry):
stw r0, SRR0_FRAME_OFFSET(r1)
stw r2, SRR1_FRAME_OFFSET(r1)
/*
* Enable data and instruction address translation, exception recovery
*
@@ -143,7 +146,10 @@ SYM (shared_raw_irq_code_entry):
/*
* Get current nesting level in R2
*/
mfspr r2, SPRG0
/* mfspr r2, SPRG0 */
addis r6, 0, _ISR_Nest_level@ha
lwz r2, _ISR_Nest_level@l( r6 )
/*
* Check if stack switch is necessary
*/
@@ -156,6 +162,10 @@ nested:
* Start Incrementing nesting level in R2
*/
addi r2,r2,1
addis r6, 0, _ISR_Nest_level@ha
stw r2, _ISR_Nest_level@l( r6 )
/*
* Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
*/
@@ -163,7 +173,7 @@ nested:
/*
* store new nesting level in SPRG0
*/
mtspr SPRG0, r2
/* mtspr SPRG0, r2 */
addi r6, r6, 1
mfmsr r5
@@ -180,21 +190,30 @@ nested:
* Call C exception handler for decrementer Interrupt frame is passed just
* in case...
*/
addi r3, r14, 0x8
bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */
/*
* start decrementing nesting level. Note : do not test result against 0
* value as an easy exit condition because if interrupt nesting level > 1
* then _Thread_Dispatch_disable_level > 1
*/
mfspr r2, SPRG0
/* mfspr r2, SPRG0 */
addis r6, 0, _ISR_Nest_level@ha
lwz r2, _ISR_Nest_level@l( r6 )
/*
* start decrementing _Thread_Dispatch_disable_level
*/
lwz r3,_Thread_Dispatch_disable_level@l(r15)
addi r2, r2, -1 /* Continue decrementing nesting level */
addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */
mtspr SPRG0, r2 /* End decrementing nesting level */
stw r2, _ISR_Nest_level@l( r6 )
/* mtspr SPRG0, r2 */ /* End decrementing nesting level */
stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
cmpwi r3, 0
/*
@@ -226,6 +245,7 @@ nested:
*/
stmw r16, GPR16_OFFSET(r1)
addi r3, r1, 0x8
/*
* compute SP at exception entry
*/

15
c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_init.c
View File

@@ -51,7 +51,15 @@ static rtems_irq_connect_data defaultIrq = {
/* vectorIdex, hdl , on , off , isOn */
0, nop_func , nop_func , nop_func , not_connected
};
static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
/*
List the interrupts is their order of priority (highest first).
This does not have to be the same order as the siprr settings but
without knowing more about the application they are kept the same.
*/
static rtems_irq_prio irqPrioTable[BSP_CPM_IRQ_NUMBER]={
/*
* actual priorities for interrupt :
*/
@@ -62,10 +70,7 @@ static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
2, 3, 0, 5, 15, 16, 17, 18, 49, 51, 0, 0, 0, 0, 0, 0,
6, 7, 8, 0, 11, 12, 0, 0, 20, 21, 22, 23, 0, 0, 0, 0,
29, 31, 33, 37, 38, 41, 47, 48, 55, 56, 57, 60, 64, 65, 69, 70,
/*
* Processor exceptions handled as interrupts
*/
0
};