forked from Imagelibrary/rtems
updates from John Gwynne
This commit is contained in:
Joel Sherrill
179
c/src/lib/libbsp/m68k/efi332/start/start.c
Normal file
179
c/src/lib/libbsp/m68k/efi332/start/start.c
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@@ -0,0 +1,179 @@
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#include <efi332.h>
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#include <sim.h>
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#define __START_C__
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#include "bsp.h"
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m68k_isr_entry M68Kvec[256];
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m68k_isr_entry vectors[256];
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char * const __argv[]= {"main", ""};
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char * const __env[]= {""};
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int main(const int argc, char * const argv[], char * const env[]);
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void dumby_start () __attribute__ ((noreturn));
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void dumby_start() {
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/* We need to by-pass the link instruction since the RAM chip-
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select pins are not yet configured. */
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asm volatile ( ".global start ;
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start:");
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/* disable interrupts, load stack pointer */
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asm volatile ( "oriw #0x0700, %sr;
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moveal #M68Kvec, %a0;
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movec %a0, %vbr;
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movel #_end, %d0;
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addl " STACK_SIZE ",%d0;
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movel %d0,%sp;
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link %a6, #0"
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);
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/* include in ram_init.S */
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/*
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* Initalize the SIM module.
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* The stack pointer is not usable until the RAM chip select lines
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* are configured. The following code must remain inline.
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*/
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/* Module Configuration Register */
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/* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
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*SIMCR = (unsigned short int)
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(FRZSW | FRZBM | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB));
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/* Synthesizer Control Register */
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/* see section(s) 4.8 */
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/* end include in ram_init.S */
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*SYNCR = (unsigned short int)
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( SAM(EFI_W,15,W) | SAM(0x0,14,X) | SAM(EFI_Y,8,Y) | STSIM );
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while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */
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/* include in ram_init.S */
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*SYNCR = (unsigned short int)
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( SAM(EFI_W,15,W) | SAM(EFI_X,14,X) | SAM(EFI_Y,8,Y) | STSIM );
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/* System Protection Control Register */
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/* !!! can only write to once after reset !!! */
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/* see section 3.8.4 of the SIM Reference Manual */
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*SYPCR = (unsigned char)( SAM(0x3,4,SWT) | HME | BME );
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/* Periodic Interrupr Control Register */
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/* see section 3.8.2 of the SIM Reference Manual */
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*PICR = (unsigned short int)
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( SAM(0,8,PIRQL) | SAM(EFI_PIV,0,PIV) );
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/* ^^^ zero disables interrupt, don't enable here or ram_init will
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be wrong. It's enabled below. */
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/* Periodic Interrupt Timer Register */
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/* see section 3.8.3 of the SIM Reference Manual */
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*PITR = (unsigned short int)( SAM(0x09,0,PITM) );
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/* 1.098mS interrupt */
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/* Port C Data */
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/* load values before enabled */
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*PORTC = (unsigned char) 0x0;
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/* Chip-Select Base Address Register */
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/* see section 7 of the SIM Reference Manual */
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*CSBARBT = (unsigned short int)
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(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
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*CSBAR0 = (unsigned short int)
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(((0x000000 >> 8)&0xfff8) | BS_1M ); /* 1M bytes located at 0x0000 */
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*CSBAR1 = (unsigned short int)
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(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
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*CSBAR2 = (unsigned short int)
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(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */
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*CSBAR3 = (unsigned short int)
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(0xfff8 | BS_64K); /* AVEC interrupts */
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*CSBAR10 = (unsigned short int)
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(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
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/* Chip-Select Options Registers */
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/* see section 7 of the SIM Reference Manual */
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*CSORBT = (unsigned short int)
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( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace );
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*CSOR0 = (unsigned short int)
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( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
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*CSOR1 = (unsigned short int)
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( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
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*CSOR2 = (unsigned short int)
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( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
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*CSOR3 = (unsigned short int)
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( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
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*CSOR10 = (unsigned short int)
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( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
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/* Chip Select Pin Assignment Register 0 */
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/* see section 7 of the SIM Reference Manual */
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*CSPAR0 = (unsigned short int)(
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SAM(DisOut,CS_5,0x3000) | /* PC2 */
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SAM(DisOut,CS_4,0x0c00) | /* PC1 */
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SAM(DisOut,CS_3,0x0300) | /* AVEC (internally) */
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SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS */
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SAM(CS16bit,CS_1,0x0030)| /* RAM LDS */
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SAM(CS16bit,CS_0,0x000c)| /* W/!R */
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SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */
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);
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/* Chip Select Pin Assignment Register 1 */
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/* see section 7 of the SIM Reference Manual */
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*CSPAR1 = (unsigned short int)(
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SAM(CS16bit,CS_10,0x300)| /* ECLK */
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SAM(DisOut,CS_9,0x0c0) | /* PC6 */
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SAM(DisOut,CS_8,0x030) | /* PC5 */
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SAM(DisOut,CS_7,0x00c) | /* PC4 */
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SAM(DisOut,CS_6,0x003) /* PC3 */
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);
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/* Port E and F Data Register */
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/* see section 9 of the SIM Reference Manual */
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*PORTE0 = (unsigned char) 0;
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*PORTF0 = (unsigned char) 0;
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/* Port E and F Data Direction Register */
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/* see section 9 of the SIM Reference Manual */
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*DDRE = (unsigned char) 0xff;
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*DDRF = (unsigned char) 0xfd;
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/* Port E and F Pin Assignment Register */
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/* see section 9 of the SIM Reference Manual */
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*PEPAR = (unsigned char) 0;
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*PFPAR = (unsigned char) 0;
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/* end of SIM initalization code */
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/* end include in ram_init.S */
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/*
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* Initialize RAM by copying the .data section out of ROM (if
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* needed) and "zero-ing" the .bss section.
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*/
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{
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register char *src = _endtext;
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register char *dst = _sdata;
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if (_copy_data_from_rom)
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/* ROM has data at end of text; copy it. */
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while (dst < _edata)
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*dst++ = *src++;
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/* Zero bss */
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for (dst = __bss_start; dst< _end; dst++)
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*dst = 0;
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}
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/*
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* Initalize the board.
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*/
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Spurious_Initialize();
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console_init();
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/*
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* Execute main with arguments argv and environment env
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*/
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main(1, __argv, __env);
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reboot();
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}
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void reboot() {asm("trap #15");}
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179
c/src/lib/libbsp/m68k/efi332/start332/start332.c
Normal file
179
c/src/lib/libbsp/m68k/efi332/start332/start332.c
Normal file
@@ -0,0 +1,179 @@
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#include <efi332.h>
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#include <sim.h>
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#define __START_C__
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#include "bsp.h"
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m68k_isr_entry M68Kvec[256];
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m68k_isr_entry vectors[256];
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char * const __argv[]= {"main", ""};
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char * const __env[]= {""};
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int main(const int argc, char * const argv[], char * const env[]);
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void dumby_start () __attribute__ ((noreturn));
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void dumby_start() {
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/* We need to by-pass the link instruction since the RAM chip-
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select pins are not yet configured. */
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asm volatile ( ".global start ;
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start:");
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/* disable interrupts, load stack pointer */
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asm volatile ( "oriw #0x0700, %sr;
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moveal #M68Kvec, %a0;
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movec %a0, %vbr;
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movel #_end, %d0;
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addl " STACK_SIZE ",%d0;
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movel %d0,%sp;
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link %a6, #0"
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);
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/* include in ram_init.S */
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/*
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* Initalize the SIM module.
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* The stack pointer is not usable until the RAM chip select lines
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* are configured. The following code must remain inline.
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*/
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/* Module Configuration Register */
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/* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
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*SIMCR = (unsigned short int)
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(FRZSW | FRZBM | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB));
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/* Synthesizer Control Register */
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/* see section(s) 4.8 */
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/* end include in ram_init.S */
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*SYNCR = (unsigned short int)
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( SAM(EFI_W,15,W) | SAM(0x0,14,X) | SAM(EFI_Y,8,Y) | STSIM );
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while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */
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/* include in ram_init.S */
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*SYNCR = (unsigned short int)
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( SAM(EFI_W,15,W) | SAM(EFI_X,14,X) | SAM(EFI_Y,8,Y) | STSIM );
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/* System Protection Control Register */
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/* !!! can only write to once after reset !!! */
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/* see section 3.8.4 of the SIM Reference Manual */
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*SYPCR = (unsigned char)( SAM(0x3,4,SWT) | HME | BME );
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/* Periodic Interrupr Control Register */
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/* see section 3.8.2 of the SIM Reference Manual */
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*PICR = (unsigned short int)
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( SAM(0,8,PIRQL) | SAM(EFI_PIV,0,PIV) );
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/* ^^^ zero disables interrupt, don't enable here or ram_init will
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be wrong. It's enabled below. */
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/* Periodic Interrupt Timer Register */
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/* see section 3.8.3 of the SIM Reference Manual */
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*PITR = (unsigned short int)( SAM(0x09,0,PITM) );
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/* 1.098mS interrupt */
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/* Port C Data */
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/* load values before enabled */
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*PORTC = (unsigned char) 0x0;
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/* Chip-Select Base Address Register */
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/* see section 7 of the SIM Reference Manual */
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*CSBARBT = (unsigned short int)
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(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
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*CSBAR0 = (unsigned short int)
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(((0x000000 >> 8)&0xfff8) | BS_1M ); /* 1M bytes located at 0x0000 */
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*CSBAR1 = (unsigned short int)
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(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
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*CSBAR2 = (unsigned short int)
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(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */
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*CSBAR3 = (unsigned short int)
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(0xfff8 | BS_64K); /* AVEC interrupts */
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*CSBAR10 = (unsigned short int)
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(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
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/* Chip-Select Options Registers */
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/* see section 7 of the SIM Reference Manual */
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*CSORBT = (unsigned short int)
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( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace );
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*CSOR0 = (unsigned short int)
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( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
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*CSOR1 = (unsigned short int)
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( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
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*CSOR2 = (unsigned short int)
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( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
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*CSOR3 = (unsigned short int)
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( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
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*CSOR10 = (unsigned short int)
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( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
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/* Chip Select Pin Assignment Register 0 */
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/* see section 7 of the SIM Reference Manual */
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*CSPAR0 = (unsigned short int)(
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SAM(DisOut,CS_5,0x3000) | /* PC2 */
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SAM(DisOut,CS_4,0x0c00) | /* PC1 */
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SAM(DisOut,CS_3,0x0300) | /* AVEC (internally) */
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SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS */
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SAM(CS16bit,CS_1,0x0030)| /* RAM LDS */
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SAM(CS16bit,CS_0,0x000c)| /* W/!R */
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SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */
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);
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/* Chip Select Pin Assignment Register 1 */
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/* see section 7 of the SIM Reference Manual */
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*CSPAR1 = (unsigned short int)(
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SAM(CS16bit,CS_10,0x300)| /* ECLK */
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SAM(DisOut,CS_9,0x0c0) | /* PC6 */
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SAM(DisOut,CS_8,0x030) | /* PC5 */
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SAM(DisOut,CS_7,0x00c) | /* PC4 */
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SAM(DisOut,CS_6,0x003) /* PC3 */
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);
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/* Port E and F Data Register */
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/* see section 9 of the SIM Reference Manual */
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*PORTE0 = (unsigned char) 0;
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*PORTF0 = (unsigned char) 0;
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/* Port E and F Data Direction Register */
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/* see section 9 of the SIM Reference Manual */
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*DDRE = (unsigned char) 0xff;
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*DDRF = (unsigned char) 0xfd;
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/* Port E and F Pin Assignment Register */
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/* see section 9 of the SIM Reference Manual */
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*PEPAR = (unsigned char) 0;
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*PFPAR = (unsigned char) 0;
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/* end of SIM initalization code */
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/* end include in ram_init.S */
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/*
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* Initialize RAM by copying the .data section out of ROM (if
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* needed) and "zero-ing" the .bss section.
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*/
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{
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register char *src = _endtext;
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register char *dst = _sdata;
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if (_copy_data_from_rom)
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/* ROM has data at end of text; copy it. */
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while (dst < _edata)
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*dst++ = *src++;
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/* Zero bss */
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for (dst = __bss_start; dst< _end; dst++)
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*dst = 0;
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}
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/*
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* Initalize the board.
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*/
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Spurious_Initialize();
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console_init();
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/*
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* Execute main with arguments argv and environment env
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*/
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main(1, __argv, __env);
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reboot();
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}
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void reboot() {asm("trap #15");}
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Block a user