microblaze: Rework for RTEMS 6

This reworks the existing MicroBlaze architecture port and BSP to achieve basic functionality using the latest RTEMS APIs.
2021-09-30 23:57:01 -05:00
parent 0f62af0ef8
commit d03776e804
53 changed files with 3299 additions and 1684 deletions
--- a/spec/build/bsps/microblaze/grp.yml
+++ b/spec/build/bsps/microblaze/grp.yml
@@ -0,0 +1,15 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: group
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/microblaze/include/bsp/linker-symbols.h
+ldflags: []
+links: []
+type: build
+use-after: []
+use-before: []
--- a/spec/build/bsps/microblaze/microblaze_fpga/abi.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/abi.yml
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- split: null
+- env-append: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default:
+- -mlittle-endian
+- -mno-xl-soft-div
+- -mno-xl-soft-mul
+- -Wl,-EL
+default-by-variant: []
+description: |
+  ABI flags
+enabled-by: true
+links: []
+name: ABI_FLAGS
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml
@@ -0,0 +1,24 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: microblaze
+bsp: kcu105
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+enabled-by: true
+family: microblaze_fpga
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds
+- role: build-dependency
+  uid: tstkcu105_qemu
+- role: build-dependency
+  uid: ../../opto0
+source:
+- bsps/shared/start/bspreset-loop.c
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml
@@ -0,0 +1,24 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: microblaze
+bsp: kcu105_qemu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+enabled-by: true
+family: microblaze_fpga
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds
+- role: build-dependency
+  uid: tstkcu105_qemu
+- role: build-dependency
+  uid: ../../opto0
+source:
+- bsps/microblaze/microblaze_fpga/start/bspreset.c
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
@@ -0,0 +1,36 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: group
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+enabled-by: true
+includes: []
+install: []
+ldflags: []
+links:
+- role: build-dependency
+  uid: ../grp
+- role: build-dependency
+  uid: abi
+- role: build-dependency
+  uid: obj
+- role: build-dependency
+  uid: start
+- role: build-dependency
+  uid: optconsoleinterrupts
+- role: build-dependency
+  uid: optintcbaseaddress
+- role: build-dependency
+  uid: opttimerbaseaddress
+- role: build-dependency
+  uid: opttimerfrequency
+- role: build-dependency
+  uid: optuartlitebaseaddress
+- role: build-dependency
+  uid: ../../obj
+- role: build-dependency
+  uid: ../../objirq
+- role: build-dependency
+  uid: ../../bspopts
+type: build
+use-after: []
+use-before: []
--- a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
@@ -0,0 +1,242 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  /* SPDX-License-Identifier: BSD-2-Clause */
+
+  /*
+   * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *    notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *    notice, this list of conditions and the following disclaimer in the
+   *    documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   * POSSIBILITY OF SUCH DAMAGE.
+   */
+
+  ENTRY (_start)
+  STARTUP (start.o)
+  _TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x80000000;
+
+  MEMORY
+    {
+        BRAM     (AIW) : ORIGIN = 0x00000000, LENGTH = 0x10000
+        RAM   : ORIGIN = _TEXT_START_ADDR, LENGTH = 0x1000000
+    }
+
+  REGION_ALIAS ("REGION_START", BRAM);
+  REGION_ALIAS ("REGION_VECTOR", BRAM);
+  REGION_ALIAS ("REGION_TEXT", RAM);
+  REGION_ALIAS ("REGION_TEXT_LOAD", RAM);
+  REGION_ALIAS ("REGION_RODATA", RAM);
+  REGION_ALIAS ("REGION_RODATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_DATA", RAM);
+  REGION_ALIAS ("REGION_DATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_FAST_DATA", RAM);
+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_BSS", RAM);
+  REGION_ALIAS ("REGION_WORK", RAM);
+  REGION_ALIAS ("REGION_STACK", RAM);
+
+  SECTIONS
+  {
+    .vectors.reset 0x0 : { KEEP (*(.vectors.reset)) } = 0
+    .vectors.sw_exception 0x8 : { KEEP (*(.vectors.sw_exception)) } = 0
+    .vectors.interrupt 0x10 : { KEEP (*(.vectors.interrupt)) } = 0
+    .vectors.debug_sw_break 0x18 : { KEEP (*(.vectors.debug_sw_break)) } = 0
+    .vectors.hw_exception 0x20 : { KEEP (*(.vectors.hw_exception)) } = 0
+    . = _TEXT_START_ADDR;
+    .text : ALIGN_WITH_INPUT {
+      bsp_section_text_begin = .;
+      *(.text.unlikely .text.*_unlikely)
+      *(.text .stub .text.* .gnu.linkonce.t.*)
+      /* .gnu.warning sections are handled specially by elf32.em.  */
+      *(.gnu.warning)
+      *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
+    } > REGION_TEXT AT > REGION_TEXT_LOAD
+    .init : ALIGN_WITH_INPUT {
+      KEEP (*(.init))
+    } > REGION_TEXT AT > REGION_TEXT_LOAD
+    .fini : ALIGN_WITH_INPUT {
+      KEEP (*(.fini))
+
+      /*
+      * If requested, align the size of the combined start and text
+      * section to the next power of two to meet MPU region
+      * alignment requirements.
+      */
+      . = DEFINED (bsp_align_text_and_rodata_end_to_power_of_2) ?
+          bsp_section_start_begin
+          + ALIGN (. - bsp_section_start_begin,
+          1 << LOG2CEIL (. - bsp_section_start_begin)) : .;
+
+      bsp_section_text_end = .;
+    } > REGION_TEXT AT > REGION_TEXT_LOAD
+    bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin;
+    bsp_section_text_load_begin = LOADADDR (.text);
+    bsp_section_text_load_end = bsp_section_text_load_begin + bsp_section_text_size;
+
+    . = ALIGN(4);
+
+    /* Added to handle pic code */
+    .got : {
+      *(.got)
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    .got1 : {
+      *(.got1)
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    .got2 : {
+      *(.got2)
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+
+    _frodata = . ;
+    .rodata : {
+      *(.rodata)
+      *(.rodata.*)
+      *(.gnu.linkonce.r.*)
+      CONSTRUCTORS; /* Is this needed? */
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    _erodata = .;
+    .eh_frame : {
+      *(.eh_frame)
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    .jcr : {
+      *(.jcr)
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    .gcc_except_table : {
+      *(.gcc_except_table)
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    .tdata : ALIGN_WITH_INPUT {
+      _TLS_Data_begin = .;
+      *(.tdata .tdata.* .gnu.linkonce.td.*)
+      _TLS_Data_end = .;
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    .tbss : ALIGN_WITH_INPUT {
+      _TLS_BSS_begin = .;
+      *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+      _TLS_BSS_end = .;
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
+    _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
+    _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
+    _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
+    _TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
+    _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+
+    .ctors : {
+      _dummy_symbol__ = .;
+      __CTOR_LIST__ = .;
+      ___CTORS_LIST___ = .;
+      KEEP (*crtbegin.o(.ctors))
+      KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+      KEEP (*(SORT(.ctors.*)))
+      KEEP (*(.ctors*))
+      __CTOR_END__ = .;
+      ___CTORS_END___ = .;
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    .dtors : {
+      __DTOR_LIST__ = .;
+      ___DTORS_LIST___ = .;
+      KEEP (*crtbegin.o(.dtors))
+      KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+      KEEP (*(SORT(.dtors.*)))
+      KEEP (*(.dtors))
+      PROVIDE(__DTOR_END__ = .);
+      PROVIDE(___DTORS_END___ = .);
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+    .rtemsroset : {
+      /* Special FreeBSD linker set sections */
+      __start_set_sysctl_set = .;
+      *(set_sysctl_*);
+      __stop_set_sysctl_set = .;
+      *(set_domain_*);
+      *(set_pseudo_*);
+
+      KEEP (*(SORT(.rtemsroset.*)))
+      bsp_section_rodata_end = .;
+    } > REGION_RODATA AT > REGION_RODATA_LOAD
+
+    .data : ALIGN_WITH_INPUT {
+      bsp_section_data_begin = .;
+      *(.data .data.* .gnu.linkonce.d.*)
+      SORT(CONSTRUCTORS)
+    } > REGION_DATA AT > REGION_DATA_LOAD
+    .data1 : ALIGN_WITH_INPUT {
+      *(.data1)
+    } > REGION_DATA AT > REGION_DATA_LOAD
+    .rtemsrwset : ALIGN_WITH_INPUT {
+      KEEP (*(SORT(.rtemsrwset.*)))
+      bsp_section_data_end = .;
+    } > REGION_DATA AT > REGION_DATA_LOAD
+    bsp_section_data_size = bsp_section_data_end - bsp_section_data_begin;
+    bsp_section_data_load_begin = LOADADDR (.data);
+    bsp_section_data_load_end = bsp_section_data_load_begin + bsp_section_data_size;
+
+    .bss : ALIGN_WITH_INPUT {
+      bsp_section_bss_begin = .;
+      *(.dynbss)
+      *(.bss .bss.* .gnu.linkonce.b.*)
+      *(COMMON)
+      bsp_section_bss_end = .;
+    } > REGION_BSS AT > REGION_BSS
+    bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_begin;
+
+    . = ALIGN(8);
+
+    .rtemsstack (NOLOAD) : ALIGN_WITH_INPUT {
+      bsp_section_rtemsstack_begin = .;
+      *(SORT_BY_ALIGNMENT (SORT_BY_NAME (.rtemsstack*)))
+      bsp_section_rtemsstack_end = .;
+    } > REGION_WORK AT > REGION_WORK
+    bsp_section_rtemsstack_size = bsp_section_rtemsstack_end - bsp_section_rtemsstack_begin;
+
+    .work : ALIGN_WITH_INPUT {
+      /*
+      * The work section will occupy the remaining REGION_WORK region and
+      * contains the RTEMS work space and heap.
+      */
+      bsp_section_work_begin = .;
+      . += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.);
+      bsp_section_work_end = .;
+    } > REGION_WORK AT > REGION_WORK
+    bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin;
+
+    .stack : ALIGN_WITH_INPUT {
+      /*
+      * The stack section will occupy the remaining REGION_STACK region and may
+      * contain the task stacks.  Depending on the region distribution this
+      * section may be of zero size.
+      */
+      bsp_section_stack_begin = .;
+      . += ORIGIN (REGION_STACK) + LENGTH (REGION_STACK) - ABSOLUTE (.);
+      bsp_section_stack_end = .;
+    } > REGION_STACK AT > REGION_STACK
+    bsp_section_stack_size = bsp_section_stack_end - bsp_section_stack_begin;
+
+    RamBase = ORIGIN (REGION_WORK);
+    RamSize = LENGTH (REGION_WORK);
+    RamEnd = RamBase + RamSize;
+    WorkAreaBase = bsp_section_work_begin;
+    HeapSize = 0;
+  }
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/obj.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml
@@ -0,0 +1,47 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}
+  source:
+  - bsps/microblaze/microblaze_fpga/include/bsp.h
+  - bsps/microblaze/microblaze_fpga/include/tm27.h
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/microblaze/microblaze_fpga/include/bsp/irq.h
+  - bsps/microblaze/include/common/xil_types.h
+  - bsps/microblaze/include/dev/serial/uartlite.h
+  - bsps/microblaze/include/dev/serial/uartlite_l.h
+links: []
+source:
+- bsps/microblaze/microblaze_fpga/clock/clock.c
+- bsps/microblaze/microblaze_fpga/console/console-io.c
+- bsps/microblaze/microblaze_fpga/console/debug-io.c
+- bsps/microblaze/microblaze_fpga/irq/irq.c
+- bsps/microblaze/microblaze_fpga/start/_exception_handler.S
+- bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S
+- bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
+- bsps/microblaze/microblaze_fpga/start/bspreset.c
+- bsps/microblaze/microblaze_fpga/start/bspstart.c
+- bsps/microblaze/microblaze_fpga/start/crtinit.S
+- bsps/microblaze/shared/dev/serial/uartlite.c
+- bsps/microblaze/shared/dev/serial/uartlite_l.c
+- bsps/shared/cache/nocache.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
+- bsps/shared/dev/cpucounter/cpucounterfrequency.c
+- bsps/shared/dev/cpucounter/cpucounterread.c
+- bsps/shared/dev/getentropy/getentropy-cpucounter.c
+- bsps/shared/dev/serial/console-termios-init.c
+- bsps/shared/dev/serial/console-termios.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/shared/start/bspfatal-default.c
+- bsps/shared/start/bspgetworkarea-default.c
+- bsps/shared/start/gettargethash-default.c
+- bsps/shared/start/sbrk.c
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml
@@ -0,0 +1,15 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: true
+default-by-variant: []
+description: |
+  use interrupt driven mode for console
+enabled-by: true
+links: []
+name: BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 0x41200000
+default-by-variant: []
+description: |
+  base address of the AXI Interrupt Controller
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_INTC_BASE
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 0x41C00000
+default-by-variant: []
+description: |
+  base address of the AXI Timer
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_TIMER_BASE
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 100000000
+default-by-variant: []
+description: |
+  frequency of the AXI Timer
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 0x40600000
+default-by-variant: []
+description: |
+  base address of the AXI UART Lite
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_UART_BASE
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/start.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/start.yml
@@ -0,0 +1,14 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+asflags: []
+build-type: start-file
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+enabled-by: true
+includes: []
+install-path: ${BSP_LIBDIR}
+links: []
+source:
+- bsps/microblaze/shared/start/start.S
+target: start.o
+type: build
--- a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
@@ -0,0 +1,14 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- set-test-state:
+    # expected to fail, don't compile these
+    minimum: exclude
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: null
+default-by-variant: []
+description: ''
+enabled-by: true
+links: []
+type: build
--- a/spec/build/cpukit/cpumicroblaze.yml
+++ b/spec/build/cpukit/cpumicroblaze.yml
@@ -0,0 +1,29 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+cxxflags: []
+enabled-by:
+- microblaze
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/rtems
+  source:
+  - cpukit/score/cpu/microblaze/include/rtems/asm.h
+- destination: ${BSP_INCLUDEDIR}/rtems/score
+  source:
+  - cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+  - cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h
+  - cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
+  - cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h
+links: []
+source:
+- cpukit/score/cpu/microblaze/__tls_get_addr.c
+- cpukit/score/cpu/microblaze/microblaze-context-switch.S
+- cpukit/score/cpu/microblaze/microblaze-context-validate.S
+- cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S
+- cpukit/score/cpu/microblaze/cpu.c
+- cpukit/score/cpu/microblaze/cpu_asm.S
+type: build
--- a/spec/build/cpukit/librtemscpu.yml
+++ b/spec/build/cpukit/librtemscpu.yml
@@ -471,6 +471,8 @@ links:
  uid: cpum68k
 - role: build-dependency
  uid: cpumips
+- role: build-dependency
+  uid: cpumicroblaze
 - role: build-dependency
  uid: cpumoxie
 - role: build-dependency