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2011-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* rtems/powerpc/registers.h: Added MSR_UCLE, MSR_SPE, MSR_WE, and
	MSR_UBLE defines.
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Sebastian Huber
2011-02-15 07:45:16 +00:00
parent eed0ffceb4
commit cffdf7b3f6
2 changed files with 9 additions and 0 deletions
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5
cpukit/score/cpu/powerpc/ChangeLog
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@@ -1,3 +1,8 @@
2011-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
* rtems/powerpc/registers.h: Added MSR_UCLE, MSR_SPE, MSR_WE, and
MSR_UBLE defines.
2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org> 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* rtems/powerpc/registers.h, rtems/score/cpu.h: * rtems/powerpc/registers.h, rtems/score/cpu.h:

4
cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
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@@ -19,8 +19,11 @@
#define _RTEMS_POWERPC_REGISTERS_H #define _RTEMS_POWERPC_REGISTERS_H
/* Bit encodings for Machine State Register (MSR) */ /* Bit encodings for Machine State Register (MSR) */
#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
#define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */ #define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */
#define MSR_SPE (1<<25) /* SPE enable (e500) */
#define MSR_POW (1<<18) /* Enable Power Management */ #define MSR_POW (1<<18) /* Enable Power Management */
#define MSR_WE (1<<18) /* Wait state enable (e500) */
#define MSR_TGPR (1<<17) /* TLB Update registers in use */ #define MSR_TGPR (1<<17) /* TLB Update registers in use */
#define MSR_CE (1<<17) /* BookE critical interrupt */ #define MSR_CE (1<<17) /* BookE critical interrupt */
#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ #define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
@@ -30,6 +33,7 @@
#define MSR_ME (1<<12) /* Machine Check enable */ #define MSR_ME (1<<12) /* Machine Check enable */
#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
#define MSR_SE (1<<10) /* Single Step */ #define MSR_SE (1<<10) /* Single Step */
#define MSR_UBLE (1<<10) /* User-mode BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */ #define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* BookE debug exception */ #define MSR_DE (1<<9) /* BookE debug exception */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */