2010-12-16 Sebastian Huber <sebastian.huber@embedded-brains.de>

* configure.ac, include/bspopts.h.in: More options.
	* include/lpc32xx.h: Added watchdog definitions.
	* include/mmu.h, misc/mmu.c: Added const qualifier.
	* startup/bspreset.c: Use watchdog reset.

c/src/lib/libbsp/arm/lpc32xx/ChangeLog

@@ -1,3 +1,10 @@
+2010-12-16	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* configure.ac, include/bspopts.h.in: More options.
+	* include/lpc32xx.h: Added watchdog definitions.
+	* include/mmu.h, misc/mmu.c: Added const qualifier.
+	* startup/bspreset.c: Use watchdog reset.
+
 2010-12-03	Sebastian Huber <sebastian.huber@embedded-brains.de>
 
 	* startup/linkcmds.lpc32xx_mzx, startup/linkcmds.lpc32xx_mzx_stage_1,

c/src/lib/libbsp/arm/lpc32xx/configure.ac

@@ -86,9 +86,15 @@ RTEMS_BSPOPTS_HELP([LPC32XX_STOP_ETHERNET],[stop Ethernet controller at start-up
 RTEMS_BSPOPTS_SET([LPC32XX_STOP_USB],[*],[1])
 RTEMS_BSPOPTS_HELP([LPC32XX_STOP_USB],[stop USB controller at start-up to avoid DMA interference])
 
+RTEMS_BSPOPTS_SET([LPC32XX_ENABLE_WATCHDOG_RESET],[*],[1])
+RTEMS_BSPOPTS_HELP([LPC32XX_ENABLE_WATCHDOG_RESET],[bsp_reset() will use the watchdog to reset the chip])
+
 RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
 RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
 
+RTEMS_BSPOPTS_SET([TESTS_USE_PRINTK],[*],[1])
+RTEMS_BSPOPTS_HELP([TESTS_USE_PRINTK],[tests use printk() for output])
+
 RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
 RTEMS_BSP_LINKCMDS
 

c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in

@@ -45,6 +45,9 @@
 /* disable cache for read-write data sections */
 #undef LPC32XX_DISABLE_READ_WRITE_DATA_CACHE
 
+/* bsp_reset() will use the watchdog to reset the chip */
+#undef LPC32XX_ENABLE_WATCHDOG_RESET
+
 /* enable RMII for Ethernet */
 #undef LPC32XX_ETHERNET_RMII
 
@@ -95,3 +98,6 @@
 
 /* Define to the version of this package. */
 #undef PACKAGE_VERSION
+
+/* tests use printk() for output */
+#undef TESTS_USE_PRINTK

c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h

@@ -221,6 +221,17 @@
 
 /** @} */
 
+/**
+ * @name Timer Clock Control Register (TIMCLK_CTRL)
+ *
+ * @{
+ */
+
+#define TIMCLK_CTRL_WDT BSP_BIT32(0)
+#define TIMCLK_CTRL_HST BSP_BIT32(1)
+
+/** @} */
+
 #define LPC32XX_RESERVED(a, b, s) (((b) - (a) - sizeof(s)) / 4)
 
 typedef struct {
@@ -259,8 +270,76 @@ typedef struct {
 typedef struct {
 } lpc32xx_hs_timer;
 
+/**
+ * @name Watchdog Timer Interrupt Status Register (WDTIM_INT)
+ *
+ * @{
+ */
+
+#define WDTTIM_INT_MATCH_INT BSP_BIT32(0)
+
+/** @} */
+
+/**
+ * @name Watchdog Timer Control Register (WDTIM_CTRL)
+ *
+ * @{
+ */
+
+#define WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0)
+#define WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1)
+#define WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2)
+
+/** @} */
+
+/**
+ * @name Watchdog Timer Match Control Register (WDTIM_MCTRL)
+ *
+ * @{
+ */
+
+#define WDTTIM_MCTRL_MR0_INT BSP_BIT32(0)
+#define WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1)
+#define WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2)
+#define WDTTIM_MCTRL_M_RES1 BSP_BIT32(3)
+#define WDTTIM_MCTRL_M_RES2 BSP_BIT32(4)
+#define WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5)
+#define WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6)
+
+/** @} */
+
+/**
+ * @name Watchdog Timer External Match Control Register (WDTIM_EMR)
+ *
+ * @{
+ */
+
+#define WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0)
+#define WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5)
+#define WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
+
+/** @} */
+
+/**
+ * @name Watchdog Timer Reset Source Register (WDTIM_RES)
+ *
+ * @{
+ */
+
+#define WDTTIM_RES_WDT BSP_BIT32(0)
+
+/** @} */
+
 typedef struct {
-} lpc32xx_wdg_timer;
+  uint32_t intr;
+  uint32_t ctrl;
+  uint32_t counter;
+  uint32_t mctrl;
+  uint32_t match0;
+  uint32_t emr;
+  uint32_t pulse;
+  uint32_t res;
+} lpc32xx_wdt;
 
 typedef struct {
 } lpc32xx_debug;
@@ -545,8 +624,8 @@ typedef struct {
   uint32_t reserved_26 [LPC32XX_RESERVED(0x40034000, 0x40038000, lpc32xx_ms_timer)];
   lpc32xx_hs_timer hs_timer;
   uint32_t reserved_27 [LPC32XX_RESERVED(0x40038000, 0x4003c000, lpc32xx_hs_timer)];
-  lpc32xx_wdg_timer wdg_timer;
+  lpc32xx_wdt wdt;
-  uint32_t reserved_28 [LPC32XX_RESERVED(0x4003c000, 0x40040000, lpc32xx_wdg_timer)];
+  uint32_t reserved_28 [LPC32XX_RESERVED(0x4003c000, 0x40040000, lpc32xx_wdt)];
   lpc32xx_debug debug;
   uint32_t reserved_29 [LPC32XX_RESERVED(0x40040000, 0x40044000, lpc32xx_debug)];
   lpc_timer timer_0;

c/src/lib/libbsp/arm/lpc32xx/include/mmu.h

@@ -56,8 +56,8 @@ extern "C" {
   (LPC32XX_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
 
 void lpc32xx_set_translation_table_entries(
-  void *begin,
+  const void *begin,
-  void *end,
+  const void *end,
   uint32_t section_flags
 );
 

c/src/lib/libbsp/arm/lpc32xx/misc/mmu.c

@@ -23,8 +23,8 @@
 #include <bsp/mmu.h>
 
 void lpc32xx_set_translation_table_entries(
-  void *begin,
+  const void *begin,
-  void *end,
+  const void *end,
   uint32_t section_flags
 )
 {

c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c

@@ -7,24 +7,39 @@
  */
 
 /*
- * Copyright (c) 2009
+ * Copyright (c) 2009-2010 embedded brains GmbH.  All rights reserved.
- * embedded brains GmbH
+ *
- * Obere Lagerstr. 30
+ *  embedded brains GmbH
- * D-82178 Puchheim
+ *  Obere Lagerstr. 30
- * Germany
+ *  82178 Puchheim
- * <rtems@embedded-brains.de>
+ *  Germany
+ *  <rtems@embedded-brains.de>
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
  * http://www.rtems.com/license/LICENSE.
  */
 
-#include <rtems.h>
+#include <bspopts.h>
-
 #include <bsp/bootcard.h>
+#include <bsp/lpc32xx.h>
+
+static void watchdog_reset(void)
+{
+  #ifdef LPC32XX_ENABLE_WATCHDOG_RESET
+    LPC32XX_TIMCLK_CTRL |= TIMCLK_CTRL_WDT;
+    lpc32xx.wdt.mctrl |= WDTTIM_MCTRL_M_RES1 | WDTTIM_MCTRL_M_RES2;
+    lpc32xx.wdt.emr = WDTTIM_EMR_MATCH_CTRL_SET(lpc32xx.wdt.emr, 0x2);
+    lpc32xx.wdt.ctrl |= WDTTIM_CTRL_COUNT_ENAB;
+    lpc32xx.wdt.match0 = 1;
+    lpc32xx.wdt.counter = 0;
+  #endif
+}
 
 void bsp_reset( void)
 {
+  watchdog_reset();
+
   while (true) {
     /* Do nothing */
   }