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bsps/aarch64: Use fatal error for data cache disable

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On the Cortex-A cores, at least the L1 data cache is required to provide
support for atomic operations.

Update #5050.
This commit is contained in:
Sebastian Huber
2024-10-04 03:48:19 +02:00
parent 3fd063159d
commit cfd885850a
3 changed files with 8 additions and 13 deletions
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13
bsps/aarch64/shared/cache/cache.c vendored
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@@ -335,18 +335,9 @@ static inline void _CPU_cache_enable_data(void)
rtems_interrupt_local_enable(level);
}
static inline void _CPU_cache_disable_data(void)
static RTEMS_NO_RETURN inline void _CPU_cache_disable_data(void)
{
rtems_interrupt_level level;
uint64_t sctlr;
rtems_interrupt_local_disable(level);
AArch64_data_cache_clean_all_levels();
AArch64_data_cache_invalidate_all_levels();
sctlr = _AArch64_Read_sctlr_el1();
sctlr &= ~AARCH64_SCTLR_EL1_C;
_AArch64_Write_sctlr_el1(sctlr);
rtems_interrupt_local_enable(level);
_Internal_error( INTERNAL_ERROR_CANNOT_DISABLE_DATA_CACHE );
}
#ifdef RTEMS_SMP