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2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* rtems/powerpc/registers.h: Renamed defines XER in PPC_XER, LR in
	PPC_LR, CTR in PPC_CTR, PVR in PPC_PVR, RPA in PPC_RPA, DAR in
	PPC_DAR, DEC in PPC_DEC, and EAR in PPC_EAR.
This commit is contained in:
Sebastian Huber
2011-08-24 09:43:06 +00:00
parent 76c0fb0012
commit cf3d1948b0
2 changed files with 14 additions and 8 deletions
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6
cpukit/score/cpu/powerpc/ChangeLog
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@@ -1,3 +1,9 @@
2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
* rtems/powerpc/registers.h: Renamed defines XER in PPC_XER, LR in
PPC_LR, CTR in PPC_CTR, PVR in PPC_PVR, RPA in PPC_RPA, DAR in
PPC_DAR, DEC in PPC_DEC, and EAR in PPC_EAR.
2011-07-21 Sebastian Huber <sebastian.huber@embedded-brains.de> 2011-07-21 Sebastian Huber <sebastian.huber@embedded-brains.de>
* rtems/score/cpu.h: Added SPE support to CPU context. * rtems/score/cpu.h: Added SPE support to CPU context.

16
cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
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@@ -122,14 +122,14 @@ n:
#define TBRL 268 #define TBRL 268
#define TBWU 285 /* Time base Upper/Lower (Writing) */ #define TBWU 285 /* Time base Upper/Lower (Writing) */
#define TBWL 284 #define TBWL 284
#define XER 1 #define PPC_XER 1
#define LR 8 #define PPC_LR 8
#define CTR 9 #define PPC_CTR 9
#define HID0 1008 /* Hardware Implementation 0 */ #define HID0 1008 /* Hardware Implementation 0 */
#define HID1 1009 /* Hardware Implementation 1 */ #define HID1 1009 /* Hardware Implementation 1 */
#define HID2 1011 /* Hardware Implementation 2 */ #define HID2 1011 /* Hardware Implementation 2 */
#define DABR 1013 /* Data Access Breakpoint */ #define DABR 1013 /* Data Access Breakpoint */
#define PVR 287 /* Processor Version */ #define PPC_PVR 287 /* Processor Version */
#define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ #define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */
#define IBAT0L 529 #define IBAT0L 529
#define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ #define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */
@@ -174,9 +174,9 @@ n:
#define HASH2 979 #define HASH2 979
#define IMISS 980 #define IMISS 980
#define ICMP 981 #define ICMP 981
#define RPA 982 #define PPC_RPA 982
#define SDR1 25 /* MMU hash base register */ #define SDR1 25 /* MMU hash base register */
#define DAR 19 /* Data Address Register */ #define PPC_DAR 19 /* Data Address Register */
#define DEAR_BOOKE 61 #define DEAR_BOOKE 61
#define DEAR_405 981 #define DEAR_405 981
#define SPR0 272 /* Supervisor Private Registers */ #define SPR0 272 /* Supervisor Private Registers */
@@ -196,8 +196,8 @@ n:
#define SRR0 26 /* Saved Registers (exception) */ #define SRR0 26 /* Saved Registers (exception) */
#define SRR1 27 #define SRR1 27
#define IABR 1010 /* Instruction Address Breakpoint */ #define IABR 1010 /* Instruction Address Breakpoint */
#define DEC 22 /* Decrementer */ #define PPC_DEC 22 /* Decrementer */
#define EAR 282 /* External Address Register */ #define PPC_EAR 282 /* External Address Register */
#define MSSCR0 1014 /* Memory Subsystem Control Register */ #define MSSCR0 1014 /* Memory Subsystem Control Register */