Moved i386 and m68k cache management code to libcpu. Everything

now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.

c/src/lib/libcpu/shared/include/cache.h

@@ -0,0 +1,32 @@
+/*
+ *  libcpu Cache Manager Support
+ *
+ *  $Id$
+ */
+
+#ifndef __LIBCPU_CACHE_h
+#define __LIBCPU_CACHE_h
+
+#include <sys/types.h>
+
+void _CPU_disable_cache();
+void _CPU_enable_cache();
+
+void _CPU_flush_1_data_cache_line(const void *d_addr);
+void _CPU_invalidate_1_data_cache_line(const void *d_addr);
+void _CPU_freeze_data_cache(void);
+void _CPU_unfreeze_data_cache(void);
+void _CPU_invalidate_1_inst_cache_line(const void *d_addr);
+void _CPU_freeze_inst_cache(void);
+void _CPU_unfreeze_inst_cache(void);
+
+void _CPU_flush_entire_data_cache(void);
+void _CPU_invalidate_entire_data_cache(void);
+void _CPU_enable_data_cache(void);
+void _CPU_disable_data_cache(void);
+void _CPU_invalidate_entire_inst_cache(void);
+void _CPU_enable_inst_cache(void);
+void _CPU_disable_inst_cache(void);
+
+#endif
+/* end of include file */

c/src/lib/libcpu/shared/src/cache_aligned_malloc.c

@@ -0,0 +1,43 @@
+/*
+ *  RTEMS Cache Aligned Malloc
+ *
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <cache_.h>
+
+/*
+ *  rtems_cache_aligned_malloc
+ *
+ *  DESCRIPTION:
+ *
+ *  This function is used to allocate storage that spans an
+ *  integral number of cache blocks.
+ */
+
+void *rtems_cache_aligned_malloc (
+  size_t nbytes
+)
+{
+  /*
+   * Arrange to have the user storage start on the first cache
+   * block beyond the header.
+   */
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+  return (void *) ((((unsigned long)
+     malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 ))
+        + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) );
+#else
+  return malloc( nbytes );
+#endif
+}
+

c/src/lib/libcpu/shared/src/cache_manager.c

@@ -0,0 +1,292 @@
+/*
+ *  Cache Manager
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  
+ *  The functions in this file implement the API to the RTEMS Cache Manager and
+ *  are divided into data cache and instruction cache functions. Data cache
+ *  functions are only declared if a data cache is supported. Instruction
+ *  cache functions are only declared if an instruction cache is supported.
+ *  Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is
+ *  defined, where x E {DATA, INST}. These definitions are found in the CPU
+ *  dependent source files in the supercore, often
+ *  
+ *  rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h
+ *  
+ *  The functions below are implemented with CPU dependent inline routines
+ *  also found in the above file. In the event that a CPU does not support a
+ *  specific function, the CPU dependent routine does nothing (but does exist).
+ *  
+ *  At this point, the Cache Manager makes no considerations, and provides no
+ *  support for BSP specific issues such as a secondary cache. In such a system,
+ *  the CPU dependent routines would have to be modified, or a BSP layer added
+ *  to this Manager.
+ */
+
+#include <rtems.h>
+#include <sys/types.h>
+#include <libcpu/cache.h>
+#include "cache_.h"
+
+
+/*
+ * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE
+ */
+
+/*
+ * This function is called to flush the data cache by performing cache
+ * copybacks. It must determine how many cache lines need to be copied
+ * back and then perform the copybacks.
+ */
+void
+rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
+{
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+  const void * final_address;
+
+ /*
+  * Set d_addr to the beginning of the cache line; final_address indicates
+  * the last address_t which needs to be pushed. Increment d_addr and push
+  * the resulting line until final_address is passed.
+  */
+
+  final_address = (void *)((size_t)d_addr + n_bytes - 1);
+  d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
+  while( d_addr <= final_address )  {
+    _CPU_flush_1_data_cache_line( d_addr );
+    d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
+  }
+#endif
+}
+
+
+/*
+ * This function is responsible for performing a data cache invalidate.
+ * It must determine how many cache lines need to be invalidated and then
+ * perform the invalidations.
+ */
+
+void
+rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
+{
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+  const void * final_address;
+
+ /*
+  * Set d_addr to the beginning of the cache line; final_address indicates
+  * the last address_t which needs to be invalidated. Increment d_addr and
+  * invalidate the resulting line until final_address is passed.
+  */
+
+  final_address = (void *)((size_t)d_addr + n_bytes - 1);
+  d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
+  while( final_address > d_addr ) {
+    _CPU_invalidate_1_data_cache_line( d_addr );
+    d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
+  }
+#endif
+}
+
+
+/*
+ * This function is responsible for performing a data cache flush.
+ * It flushes the entire cache.
+ */
+void
+rtems_flush_entire_data_cache( void )
+{
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+   /*
+    * Call the CPU-specific routine
+    */
+   _CPU_flush_entire_data_cache();
+#endif
+}
+
+
+/*
+ * This function is responsible for performing a data cache
+ * invalidate. It invalidates the entire cache.
+ */
+void
+rtems_invalidate_entire_data_cache( void )
+{
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+ /*
+  * Call the CPU-specific routine
+  */
+
+ _CPU_invalidate_entire_data_cache();
+#endif
+}
+
+
+/*
+ * This function returns the data cache granularity.
+ */
+int
+rtems_get_data_cache_line_size( void )
+{
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+  return _CPU_DATA_CACHE_ALIGNMENT;
+#else
+  return 0;
+#endif
+}
+
+
+/*
+ * This function freezes the data cache; cache lines
+ * are not replaced.
+ */
+void
+rtems_freeze_data_cache( void )
+{
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+  _CPU_freeze_data_cache();
+#endif
+}
+
+
+/*
+ * This function unfreezes the instruction cache.
+ */
+void rtems_unfreeze_data_cache( void )
+{
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+  _CPU_unfreeze_data_cache();
+#endif
+}
+
+
+/* Turn on the data cache. */
+void
+rtems_enable_data_cache( void )
+{
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+  _CPU_enable_data_cache();
+#endif
+}
+
+
+/* Turn off the data cache. */
+void
+rtems_disable_data_cache( void )
+{
+#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+  _CPU_disable_data_cache();
+#endif
+}
+
+
+
+/*
+ * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE
+ */
+
+/*
+ * This function is responsible for performing an instruction cache
+ * invalidate. It must determine how many cache lines need to be invalidated
+ * and then perform the invalidations.
+ */
+void
+rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes )
+{
+#if defined(_CPU_INST_CACHE_ALIGNMENT)
+  const void * final_address;
+
+ /*
+  * Set i_addr to the beginning of the cache line; final_address indicates
+  * the last address_t which needs to be invalidated. Increment i_addr and
+  * invalidate the resulting line until final_address is passed.
+  */
+
+  final_address = (void *)((size_t)i_addr + n_bytes - 1);
+  i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1));
+  while( final_address > i_addr ) {
+    _CPU_invalidate_1_inst_cache_line( i_addr );
+    i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT);
+  }
+#endif
+}
+
+
+/*
+ * This function is responsible for performing an instruction cache
+ * invalidate. It invalidates the entire cache.
+ */
+void
+rtems_invalidate_entire_inst_cache( void )
+{
+#if defined(_CPU_INST_CACHE_ALIGNMENT)
+ /*
+  * Call the CPU-specific routine
+  */
+
+ _CPU_invalidate_entire_inst_cache();
+#endif
+}
+
+
+/*
+ * This function returns the instruction cache granularity.
+ */
+int
+rtems_get_inst_cache_line_size( void )
+{
+#if defined(_CPU_INST_CACHE_ALIGNMENT)
+  return _CPU_INST_CACHE_ALIGNMENT;
+#else
+  return 0;
+#endif
+}
+
+
+/*
+ * This function freezes the instruction cache; cache lines
+ * are not replaced.
+ */
+void
+rtems_freeze_inst_cache( void )
+{
+#if defined(_CPU_INST_CACHE_ALIGNMENT)
+  _CPU_freeze_inst_cache();
+#endif
+}
+
+
+/*
+ * This function unfreezes the instruction cache.
+ */
+void rtems_unfreeze_inst_cache( void )
+{
+#if defined(_CPU_INST_CACHE_ALIGNMENT)
+  _CPU_unfreeze_inst_cache();
+#endif
+}
+
+
+/* Turn on the instruction cache. */
+void
+rtems_enable_inst_cache( void )
+{
+#if defined(_CPU_INST_CACHE_ALIGNMENT)
+  _CPU_enable_inst_cache();
+#endif
+}
+
+
+/* Turn off the instruction cache. */
+void
+rtems_disable_inst_cache( void )
+{
+#if defined(_CPU_INST_CACHE_ALIGNMENT)
+  _CPU_disable_inst_cache();
+#endif
+}