forked from Imagelibrary/rtems
leon, grspw_router: Move register bit defs to header
This commit is contained in:
Javier Jalle
committed by
Daniel Hellstrom
Daniel Hellstrom
parent
59af2cc58e
commit
cc40f0bfca
@@ -141,6 +141,80 @@ extern int router_routing_table_set(void *d,
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extern int router_routing_table_get(void *d,
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struct router_routing_table *cfg);
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/*
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* ROUTER PCTRL register fields
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*/
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#define PCTRL_RD (0xff << PCTRL_RD_BIT)
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#define PCTRL_ST (0x1 << PCTRL_ST_BIT)
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#define PCTRL_SR (0x1 << PCTRL_SR_BIT)
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#define PCTRL_AD (0x1 << PCTRL_AD_BIT)
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#define PCTRL_LR (0x1 << PCTRL_LR_BIT)
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#define PCTRL_PL (0x1 << PCTRL_PL_BIT)
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#define PCTRL_TS (0x1 << PCTRL_TS_BIT)
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#define PCTRL_IC (0x1 << PCTRL_IC_BIT)
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#define PCTRL_ET (0x1 << PCTRL_ET_BIT)
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#define PCTRL_NP (0x1 << PCTRL_NP_BIT)
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#define PCTRL_PS (0x1 << PCTRL_PS_BIT)
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#define PCTRL_BE (0x1 << PCTRL_BE_BIT)
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#define PCTRL_DI (0x1 << PCTRL_DI_BIT)
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#define PCTRL_TR (0x1 << PCTRL_TR_BIT)
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#define PCTRL_PR (0x1 << PCTRL_PR_BIT)
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#define PCTRL_TF (0x1 << PCTRL_TF_BIT)
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#define PCTRL_RS (0x1 << PCTRL_RS_BIT)
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#define PCTRL_TE (0x1 << PCTRL_TE_BIT)
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#define PCTRL_CE (0x1 << PCTRL_CE_BIT)
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#define PCTRL_AS (0x1 << PCTRL_AS_BIT)
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#define PCTRL_LS (0x1 << PCTRL_LS_BIT)
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#define PCTRL_LD (0x1 << PCTRL_LD_BIT)
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#define PCTRL_RD_BIT 24
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#define PCTRL_ST_BIT 21
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#define PCTRL_SR_BIT 20
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#define PCTRL_AD_BIT 19
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#define PCTRL_LR_BIT 18
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#define PCTRL_PL_BIT 17
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#define PCTRL_TS_BIT 16
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#define PCTRL_IC_BIT 15
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#define PCTRL_ET_BIT 14
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#define PCTRL_NP_BIT 13
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#define PCTRL_PS_BIT 12
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#define PCTRL_BE_BIT 11
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#define PCTRL_DI_BIT 10
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#define PCTRL_TR_BIT 9
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#define PCTRL_PR_BIT 8
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#define PCTRL_TF_BIT 7
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#define PCTRL_RS_BIT 6
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#define PCTRL_TE_BIT 5
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#define PCTRL_CE_BIT 3
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#define PCTRL_AS_BIT 2
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#define PCTRL_LS_BIT 1
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#define PCTRL_LD_BIT 0
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/*
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* ROUTER PCTRL2 register fields
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*/
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#define PCTRL2_SM (0xff << PCTRL2_SM_BIT)
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#define PCTRL2_SV (0xff << PCTRL2_SV_BIT)
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#define PCTRL2_OR (0x1 << PCTRL2_OR_BIT)
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#define PCTRL2_UR (0x1 << PCTRL2_UR_BIT)
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#define PCTRL2_AT (0x1 << PCTRL2_AT_BIT)
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#define PCTRL2_AR (0x1 << PCTRL2_AR_BIT)
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#define PCTRL2_IT (0x1 << PCTRL2_IT_BIT)
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#define PCTRL2_IR (0x1 << PCTRL2_IR_BIT)
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#define PCTRL2_SD (0x1f << PCTRL2_SD_BIT)
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#define PCTRL2_SC (0x1f << PCTRL2_SC_BIT)
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#define PCTRL2_SM_BIT 24
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#define PCTRL2_SV_BIT 16
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#define PCTRL2_OR_BIT 15
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#define PCTRL2_UR_BIT 14
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#define PCTRL2_AT_BIT 12
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#define PCTRL2_AR_BIT 11
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#define PCTRL2_IT_BIT 10
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#define PCTRL2_IR_BIT 9
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#define PCTRL2_SD_BIT 1
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#define PCTRL2_SC_BIT 0
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/* Router Set/Get Port configuration */
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extern int router_port_ioc(void *d, int port, struct router_port *cfg);
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@@ -161,6 +235,94 @@ extern int router_port_maxplen_get(void *d, int port, uint32_t *length);
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/* Set Maximum packet length for a specific port */
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extern int router_port_maxplen_set(void *d, int port, uint32_t length);
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/*
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* ROUTER PSTSCFG register fields
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*/
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#define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT)
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#define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT)
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#define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT)
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#define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT)
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#define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT)
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#define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT)
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#define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT)
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#define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT)
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#define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT)
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#define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT)
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#define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT)
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#define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT)
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#define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT)
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#define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT)
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#define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \
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PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \
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PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \
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PSTSCFG_ME | PSTSCFG_CP)
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#define PSTSCFG_WCLEAR2 (PSTSCFG_CE | PSTSCFG_CP)
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#define PSTSCFG_EO_BIT 31
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#define PSTSCFG_EE_BIT 30
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#define PSTSCFG_PL_BIT 29
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#define PSTSCFG_TT_BIT 28
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#define PSTSCFG_PT_BIT 27
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#define PSTSCFG_HC_BIT 26
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#define PSTSCFG_PI_BIT 25
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#define PSTSCFG_CE_BIT 24
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#define PSTSCFG_EC_BIT 20
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#define PSTSCFG_TS_BIT 18
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#define PSTSCFG_ME_BIT 17
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#define PSTSCFG_IP_BIT 7
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#define PSTSCFG_CP_BIT 4
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#define PSTSCFG_PC_BIT 0
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/*
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* ROUTER PSTS register fields
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*/
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#define PSTS_PT (0x3 << PSTS_PT_BIT)
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#define PSTS_PL (0x1 << PSTS_PL_BIT)
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#define PSTS_TT (0x1 << PSTS_TT_BIT)
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#define PSTS_RS (0x1 << PSTS_RS_BIT)
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#define PSTS_SR (0x1 << PSTS_SR_BIT)
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#define PSTS_LR (0x1 << PSTS_LR_BIT)
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#define PSTS_SP (0x1 << PSTS_SP_BIT)
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#define PSTS_AC (0x1 << PSTS_AC_BIT)
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#define PSTS_TS (0x1 << PSTS_TS_BIT)
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#define PSTS_ME (0x1 << PSTS_ME_BIT)
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#define PSTS_TF (0x1 << PSTS_TF_BIT)
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#define PSTS_RE (0x1 << PSTS_RE_BIT)
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#define PSTS_LS (0x7 << PSTS_LS_BIT)
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#define PSTS_IP (0x1f << PSTS_IP_BIT)
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#define PSTS_PR (0x1 << PSTS_PR_BIT)
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#define PSTS_PB (0x1 << PSTS_PB_BIT)
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#define PSTS_IA (0x1 << PSTS_IA_BIT)
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#define PSTS_CE (0x1 << PSTS_CE_BIT)
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#define PSTS_ER (0x1 << PSTS_ER_BIT)
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#define PSTS_DE (0x1 << PSTS_DE_BIT)
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#define PSTS_PE (0x1 << PSTS_PE_BIT)
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#define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \
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PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \
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PSTS_ER | PSTS_DE | PSTS_PE)
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#define PSTS_PT_BIT 30
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#define PSTS_PL_BIT 29
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#define PSTS_TT_BIT 28
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#define PSTS_RS_BIT 27
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#define PSTS_SR_BIT 26
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#define PSTS_LR_BIT 22
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#define PSTS_SP_BIT 21
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#define PSTS_AC_BIT 20
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#define PSTS_TS_BIT 18
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#define PSTS_ME_BIT 17
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#define PSTS_TF_BIT 16
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#define PSTS_RE_BIT 15
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#define PSTS_LS_BIT 12
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#define PSTS_IP_BIT 7
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#define PSTS_PR_BIT 6
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#define PSTS_PB_BIT 5
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#define PSTS_IA_BIT 4
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#define PSTS_CE_BIT 3
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#define PSTS_ER_BIT 2
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#define PSTS_DE_BIT 1
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#define PSTS_PE_BIT 0
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/* Check Port Status register and clear errors if there are */
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extern int router_port_status(void *d, int port, uint32_t *sts);
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@@ -104,139 +104,18 @@
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/*
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* ROUTER PCTRL register fields
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* DEFINED IN HEADER
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*/
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#define PCTRL_RD (0xff << PCTRL_RD_BIT)
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#define PCTRL_ST (0x1 << PCTRL_ST_BIT)
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#define PCTRL_SR (0x1 << PCTRL_SR_BIT)
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#define PCTRL_AD (0x1 << PCTRL_AD_BIT)
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#define PCTRL_LR (0x1 << PCTRL_LR_BIT)
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#define PCTRL_PL (0x1 << PCTRL_PL_BIT)
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#define PCTRL_TS (0x1 << PCTRL_TS_BIT)
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#define PCTRL_IC (0x1 << PCTRL_IC_BIT)
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#define PCTRL_ET (0x1 << PCTRL_ET_BIT)
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#define PCTRL_NP (0x1 << PCTRL_NP_BIT)
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#define PCTRL_PS (0x1 << PCTRL_PS_BIT)
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#define PCTRL_BE (0x1 << PCTRL_BE_BIT)
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#define PCTRL_DI (0x1 << PCTRL_DI_BIT)
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#define PCTRL_TR (0x1 << PCTRL_TR_BIT)
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#define PCTRL_PR (0x1 << PCTRL_PR_BIT)
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#define PCTRL_TF (0x1 << PCTRL_TF_BIT)
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#define PCTRL_RS (0x1 << PCTRL_RS_BIT)
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#define PCTRL_TE (0x1 << PCTRL_TE_BIT)
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#define PCTRL_CE (0x1 << PCTRL_CE_BIT)
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#define PCTRL_AS (0x1 << PCTRL_AS_BIT)
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#define PCTRL_LS (0x1 << PCTRL_LS_BIT)
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#define PCTRL_LD (0x1 << PCTRL_LD_BIT)
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#define PCTRL_RD_BIT 24
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#define PCTRL_ST_BIT 21
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#define PCTRL_SR_BIT 20
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#define PCTRL_AD_BIT 19
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#define PCTRL_LR_BIT 18
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#define PCTRL_PL_BIT 17
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#define PCTRL_TS_BIT 16
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#define PCTRL_IC_BIT 15
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#define PCTRL_ET_BIT 14
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#define PCTRL_NP_BIT 13
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#define PCTRL_PS_BIT 12
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#define PCTRL_BE_BIT 11
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#define PCTRL_DI_BIT 10
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#define PCTRL_TR_BIT 9
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#define PCTRL_PR_BIT 8
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#define PCTRL_TF_BIT 7
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#define PCTRL_RS_BIT 6
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#define PCTRL_TE_BIT 5
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#define PCTRL_CE_BIT 3
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#define PCTRL_AS_BIT 2
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#define PCTRL_LS_BIT 1
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#define PCTRL_LD_BIT 0
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/*
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* ROUTER PSTSCFG register fields
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* DEFINED IN HEADER
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*/
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#define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT)
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#define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT)
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#define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT)
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#define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT)
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#define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT)
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#define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT)
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#define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT)
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#define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT)
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#define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT)
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#define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT)
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#define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT)
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#define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT)
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#define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT)
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#define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT)
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#define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \
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PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \
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PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \
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PSTSCFG_ME | PSTSCFG_CP)
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#define PSTSCFG_EO_BIT 31
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#define PSTSCFG_EE_BIT 30
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#define PSTSCFG_PL_BIT 29
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#define PSTSCFG_TT_BIT 28
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#define PSTSCFG_PT_BIT 27
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#define PSTSCFG_HC_BIT 26
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#define PSTSCFG_PI_BIT 25
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#define PSTSCFG_CE_BIT 24
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#define PSTSCFG_EC_BIT 20
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#define PSTSCFG_TS_BIT 18
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#define PSTSCFG_ME_BIT 17
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#define PSTSCFG_IP_BIT 7
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#define PSTSCFG_CP_BIT 4
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#define PSTSCFG_PC_BIT 0
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/*
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* ROUTER PSTS register fields
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* DEFINED IN HEADER
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*/
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#define PSTS_PT (0x3 << PSTS_PT_BIT)
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#define PSTS_PL (0x1 << PSTS_PL_BIT)
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#define PSTS_TT (0x1 << PSTS_TT_BIT)
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#define PSTS_RS (0x1 << PSTS_RS_BIT)
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#define PSTS_SR (0x1 << PSTS_SR_BIT)
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#define PSTS_LR (0x1 << PSTS_LR_BIT)
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#define PSTS_SP (0x1 << PSTS_SP_BIT)
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#define PSTS_AC (0x1 << PSTS_AC_BIT)
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#define PSTS_TS (0x1 << PSTS_TS_BIT)
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#define PSTS_ME (0x1 << PSTS_ME_BIT)
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#define PSTS_TF (0x1 << PSTS_TF_BIT)
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#define PSTS_RE (0x1 << PSTS_RE_BIT)
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#define PSTS_LS (0x7 << PSTS_LS_BIT)
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#define PSTS_IP (0x1f << PSTS_IP_BIT)
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#define PSTS_PR (0x1 << PSTS_PR_BIT)
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#define PSTS_PB (0x1 << PSTS_PB_BIT)
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#define PSTS_IA (0x1 << PSTS_IA_BIT)
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#define PSTS_CE (0x1 << PSTS_CE_BIT)
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#define PSTS_ER (0x1 << PSTS_ER_BIT)
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#define PSTS_DE (0x1 << PSTS_DE_BIT)
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#define PSTS_PE (0x1 << PSTS_PE_BIT)
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#define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \
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PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \
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PSTS_ER | PSTS_DE | PSTS_PE)
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#define PSTS_PT_BIT 30
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#define PSTS_PL_BIT 29
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#define PSTS_TT_BIT 28
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#define PSTS_RS_BIT 27
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#define PSTS_SR_BIT 26
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#define PSTS_LR_BIT 22
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#define PSTS_SP_BIT 21
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#define PSTS_AC_BIT 20
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#define PSTS_TS_BIT 18
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#define PSTS_ME_BIT 17
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#define PSTS_TF_BIT 16
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#define PSTS_RE_BIT 15
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#define PSTS_LS_BIT 12
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#define PSTS_IP_BIT 7
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#define PSTS_PR_BIT 6
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#define PSTS_PB_BIT 5
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#define PSTS_IA_BIT 4
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#define PSTS_CE_BIT 3
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#define PSTS_ER_BIT 2
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#define PSTS_DE_BIT 1
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#define PSTS_PE_BIT 0
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/*
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* ROUTER PTIMER register fields
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@@ -247,28 +126,8 @@
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/*
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* ROUTER PCTRL2 register fields
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* DEFINED IN HEADER
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*/
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#define PCTRL2_SM (0xff << PCTRL2_SM_BIT)
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#define PCTRL2_SV (0xff << PCTRL2_SV_BIT)
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#define PCTRL2_OR (0x1 << PCTRL2_OR_BIT)
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#define PCTRL2_UR (0x1 << PCTRL2_UR_BIT)
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#define PCTRL2_AT (0x1 << PCTRL2_AT_BIT)
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#define PCTRL2_AR (0x1 << PCTRL2_AR_BIT)
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#define PCTRL2_IT (0x1 << PCTRL2_IT_BIT)
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#define PCTRL2_IR (0x1 << PCTRL2_IR_BIT)
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#define PCTRL2_SD (0x1f << PCTRL2_SD_BIT)
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#define PCTRL2_SC (0x1f << PCTRL2_SC_BIT)
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#define PCTRL2_SM_BIT 24
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#define PCTRL2_SV_BIT 16
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#define PCTRL2_OR_BIT 15
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#define PCTRL2_UR_BIT 14
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#define PCTRL2_AT_BIT 12
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#define PCTRL2_AR_BIT 11
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#define PCTRL2_IT_BIT 10
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#define PCTRL2_IR_BIT 9
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#define PCTRL2_SD_BIT 1
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#define PCTRL2_SC_BIT 0
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/*
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* ROUTER RTRCFG register fields
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