RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

Add NOP after writing the CACR is there to address the issue

Browse Source 
noted in "Device Errata MCF5282DE", Rev. 1.7, 09/2004.
This commit is contained in:
Eric Norum
2005-03-10 19:52:35 +00:00
parent 8008148cc3
commit cbb615bfa5
2 changed files with 28 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
c/src/lib/libbsp/m68k/uC5282/ChangeLog
View File

@@ -1,3 +1,7 @@
2005-03-10 Eric Norum <norume@aps.anl.gov>
* startup/bspstart.c: Add NOP after CACR writes. (work around hardware bug)
2005-02-14 Eric Norum <norume@aps.anl.gov>
* startup/bspstart.c: Don't cache flash -- it messes up programming.

25
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
View File

@@ -45,8 +45,31 @@ char *rtems_progname;
/*
* CPU-space access
* The NOP after writing the CACR is there to address the following issue as
* described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
*
* 6 Possible Cache Corruption after Setting CACR[CINV]
* 6.1 Description
* The cache on the MCF5282 was enhanced to function as a unified data and
* instruction cache, an instruction cache, or an operand cache. The cache
* function and organization is controlled by the cache control register (CACR).
* The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
* If the cache is configured as a unified cache and the CINV bit is set, the
* scope of the cache clear is controlled by two other bits in the CACR,
* INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
* cache only). These bits allow the entire cache, just the instruction
* portion of the cache, or just the data portion of the cache to be cleared.
* If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
* and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
* then cache corruption may occur.
*
* 6.2 Workaround
* All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
* should be followed immediately by a NOP instruction. This avoids the cache
* corruption problem.
* DATECODES AFFECTED: All
*/
#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr ; nop" : : "d" (_cacr))
#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))