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doc: Fix interrupt level ARM documentation

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This commit is contained in:
Sebastian Huber
2015-06-26 21:39:16 +02:00
parent d84408a9aa
commit cb2b8f02dd
1 changed files with 3 additions and 4 deletions
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7
doc/cpu_supplement/arm.t
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@@ -152,10 +152,9 @@ confusion.
@subsection Interrupt Levels @subsection Interrupt Levels
The RTEMS interrupt level mapping scheme for the ARM is not a numeric level as There are exactly two interrupt levels on ARM with respect to RTEMS. Level
on most RTEMS ports. It is a bit mapping that corresponds the enable bit zero corresponds to interrupts enabled. Level one corresponds to interrupts
postions in the Current Program Status Register (CPSR). There are only two disabled.
levels: IRQ enabled and IRQ disabled.
@subsection Interrupt Stack @subsection Interrupt Stack