forked from Imagelibrary/rtems
New (CVS import Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>'s
submission).
This commit is contained in:
Ralf Corsepius
209
c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
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209
c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
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/*===============================================================*\
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| Project: RTEMS generic MPC5200 BSP |
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+-----------------------------------------------------------------+
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| File: $File$
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+-----------------------------------------------------------------+
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| Partially based on the code references which are named below. |
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| Adaptions, modifications, enhancements and any recent parts of |
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| the code are: |
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| Copyright (c) 2005 |
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| Embedded Brains GmbH |
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| Obere Lagerstr. 30 |
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| D-82178 Puchheim |
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| Germany |
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| rtems@embedded-brains.de |
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+-----------------------------------------------------------------+
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| The license and distribution terms for this file may be |
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| found in the file LICENSE in this distribution or at |
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| |
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| http://www.rtems.com/license/LICENSE. |
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| |
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+-----------------------------------------------------------------+
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| this file contains the code to initialize the cpu |
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+-----------------------------------------------------------------+
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| date history ID |
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| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 01.12.05 creation doe |
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|*****************************************************************|
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|*CVS information: |
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|*(the following information is created automatically, |
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|*do not edit here) |
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|*****************************************************************|
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|* $Log$
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|* Revision 1.8 2005/12/09 09:05:16 thomas
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|* changed names of board variations
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|*
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|* Revision 1.7 2005/12/09 08:57:03 thomas
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|* added/modifed file headers
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|*
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|* Revision 1.6 2005/12/06 14:11:12 thomas
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|* added EB file headers
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|*
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*
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|*****************************************************************|
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\*===============================================================*/
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/***********************************************************************/
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/* */
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/* Module: cpuinit.c */
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/* Date: 07/17/2003 */
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/* Purpose: RTEMS MPC5x00 C level startup code */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Description: This file contains additional functions for */
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/* initializing the MPC5x00 CPU */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Code */
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/* References: MPC8260ads additional CPU initialization */
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/* Module: cpuinit.c */
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/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
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/* Version 1.1 */
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/* Date: 10/22/2002 */
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/* */
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/* Author(s) / Copyright(s): */
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/* */
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/* Written by Jay Monkman (jmonkman@frasca.com) */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Partially based on the code references which are named above. */
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/* Adaptions, modifications, enhancements and any recent parts of */
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/* the code are under the right of */
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/* */
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/* IPR Engineering, Dachauer Stra<72>e 38, D-80335 M<>nchen */
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/* Copyright(C) 2003 */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* IPR Engineering makes no representation or warranties with */
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/* respect to the performance of this computer program, and */
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/* specifically disclaims any responsibility for any damages, */
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/* special or consequential, connected with the use of this program. */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Version history: 1.0 */
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/* */
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/***********************************************************************/
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#include "../include/bsp.h"
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#include <rtems/powerpc/registers.h>
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#include "../include/mpc5200.h"
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#include <libcpu/mmu.h>
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#include <libcpu/spr.h>
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#include <string.h>
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/* Macros for HID0 access */
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#define SET_HID0(r) __asm__ volatile ("mtspr 0x3F0,%0\n" ::"r"(r))
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#define GET_HID0(r) __asm__ volatile ("mfspr %0,0x3F0\n" :"=r"(r))
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#define DBAT_MTSPR(val,name) __MTSPR(val,name);
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#define SET_DBAT(n,uv,lv) {DBAT_MTSPR(uv,DBAT##n##U);DBAT_MTSPR(lv,DBAT##n##L);}
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void calc_dbat_regvals(BAT *bat_ptr,
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uint32_t base_addr,
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uint32_t size,
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boolean flg_w,
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boolean flg_i,
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boolean flg_m,
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boolean flg_g,
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boolean flg_bpp)
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{
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uint32_t block_mask;
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uint32_t end_addr;
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/*
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* determine block mask, that overlaps the whole block
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*/
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end_addr = base_addr+size-1;
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block_mask = ~0;
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while ((end_addr & block_mask) != (base_addr & block_mask)) {
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block_mask <<= 1;
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}
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bat_ptr->batu.bepi = base_addr >> (32-15);
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bat_ptr->batu.bl = ~(block_mask >> (28-11));
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bat_ptr->batu.vs = 1;
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bat_ptr->batu.vp = 1;
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bat_ptr->batl.brpn = base_addr >> (32-15);
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bat_ptr->batl.w = flg_w;
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bat_ptr->batl.i = flg_i;
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bat_ptr->batl.m = flg_m;
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bat_ptr->batl.g = flg_g;
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bat_ptr->batl.pp = flg_bpp;
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}
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void cpu_init(void)
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{
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register unsigned long reg;
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BAT dbat;
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/*
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* clear dbat
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*/
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memset(&dbat, 0,sizeof(dbat));
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/* enable instruction cache */
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GET_HID0(reg);
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reg |= HID0_ICE;
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SET_HID0(reg);
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/*
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* set up DBAT registers in MMU
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*/
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#if defined (BRS5L)
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calc_dbat_regvals(&dbat,RAM_START,RAM_SIZE,1,0,0,0,BPP_RW);
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SET_DBAT(0,dbat.batu,dbat.batl);
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calc_dbat_regvals(&dbat,ROM_START,ROM_SIZE,1,0,0,0,BPP_RX);
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SET_DBAT(1,dbat.batu,dbat.batl);
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calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW);
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SET_DBAT(2,dbat.batu,dbat.batl);
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calc_dbat_regvals(&dbat,DPRAM_START,128*1024,1,1,1,1,BPP_RW);
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SET_DBAT(3,dbat.batu,dbat.batl);
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#endif
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#if defined (HAS_UBOOT)
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calc_dbat_regvals(&dbat,
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uboot_bdinfo_ptr->bi_memstart,
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uboot_bdinfo_ptr->bi_memsize,
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1,0,0,0,BPP_RW);
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SET_DBAT(0,dbat.batu,dbat.batl);
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calc_dbat_regvals(&dbat,
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uboot_bdinfo_ptr->bi_flashstart,
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uboot_bdinfo_ptr->bi_flashsize,
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1,0,0,0,BPP_RX);
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SET_DBAT(1,dbat.batu,dbat.batl);
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calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW);
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SET_DBAT(2,dbat.batu,dbat.batl);
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if (uboot_bdinfo_ptr->bi_sramsize != 0) {
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calc_dbat_regvals(&dbat,
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uboot_bdinfo_ptr->bi_sramstart,
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uboot_bdinfo_ptr->bi_sramsize,
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0,1,1,1,BPP_RW);
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SET_DBAT(3,dbat.batu,dbat.batl);
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}
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#endif
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/*
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* enable data MMU in MSR
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*/
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_write_MSR(_read_MSR() | MSR_DR);
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#if 1 /* TRACE32 now supports data cache for MGT5x00 */
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/*
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* enable data cache
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*/
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GET_HID0(reg);
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reg |= HID0_DCE;
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SET_HID0(reg);
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#endif
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}
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