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bsps: Remove networking drivers

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Update #3850
This commit is contained in:
Vijay Kumar Banerjee
2021-02-24 19:09:56 -07:00
parent 6692e03e9d
commit c90fa83041
127 changed files with 0 additions and 111535 deletions
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940
bsps/m68k/av5282/net/network.c
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@@ -1,940 +0,0 @@
#include <machine/rtems-bsd-kernel-space.h>
#include <bsp.h>
#include <stdio.h>
#include <errno.h>
#include <stdarg.h>
#include <string.h>
#include <rtems.h>
#include <rtems/error.h>
#include <rtems/rtems_bsdnet.h>
#include <sys/param.h>
#include <sys/mbuf.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
/*
* Number of interfaces supported by this driver
*/
#define NIFACES 1
#define FEC_INTC0_TX_VECTOR (64+23)
#define FEC_INTC0_RX_VECTOR (64+27)
#define FEC_INTC0_TX_VECTOR (64+23)
#define FEC_INTC0_RX_VECTOR (64+27)
#define MII_VECTOR (64+7) /* IRQ7* pin connected to external transceiver */
#define MII_EPPAR MCF5282_EPORT_EPPAR_EPPA7_LEVEL
#define MII_EPDDR MCF5282_EPORT_EPDDR_EPDD7
#define MII_EPIER MCF5282_EPORT_EPIER_EPIE7
#define MII_EPPDR MCF5282_EPORT_EPPDR_EPPD7
/*
* Default number of buffer descriptors set aside for this driver.
* The number of transmit buffer descriptors has to be quite large
* since a single frame often uses three or more buffer descriptors.
*/
#define RX_BUF_COUNT 32
#define TX_BUF_COUNT 20
#define TX_BD_PER_BUF 3
#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
/*
* RTEMS event used by interrupt handler to signal daemons.
* This must *not* be the same event used by the TCP/IP task synchronization.
*/
#define TX_INTERRUPT_EVENT RTEMS_EVENT_1
#define RX_INTERRUPT_EVENT RTEMS_EVENT_1
/*
* RTEMS event used to start transmit daemon.
* This must not be the same as INTERRUPT_EVENT.
*/
#define START_TRANSMIT_EVENT RTEMS_EVENT_2
/*
* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
* Round off to nearest multiple of RBUF_ALIGN.
*/
#define MAX_MTU_SIZE 1518
#define RBUF_ALIGN 4
#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
#if (MCLBYTES < RBUF_SIZE)
#error "Driver must have MCLBYTES > RBUF_SIZE"
#endif
typedef struct mcf5282BufferDescriptor_ {
volatile uint16_t status;
uint16_t length;
volatile void *buffer;
} mcf5282BufferDescriptor_t;
/*
* Per-device data
*/
struct mcf5282_enet_struct {
struct arpcom arpcom;
struct mbuf **rxMbuf;
struct mbuf **txMbuf;
int acceptBroadcast;
int rxBdCount;
int txBdCount;
int txBdHead;
int txBdTail;
int txBdActiveCount;
mcf5282BufferDescriptor_t *rxBdBase;
mcf5282BufferDescriptor_t *txBdBase;
rtems_id rxDaemonTid;
rtems_id txDaemonTid;
/*
* Statistics
*/
unsigned long rxInterrupts;
unsigned long txInterrupts;
unsigned long miiInterrupts;
unsigned long txRawWait;
unsigned long txRealign;
unsigned long txRealignDrop;
uint16_t mii_sr2;
};
static struct mcf5282_enet_struct enet_driver[NIFACES];
static int
getMII(int phyNumber, int regNumber);
static rtems_isr
mcf5282_fec_rx_interrupt_handler( rtems_vector_number v )
{
MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
enet_driver[0].rxInterrupts++;
rtems_bsdnet_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
}
static rtems_isr
mcf5282_fec_tx_interrupt_handler( rtems_vector_number v )
{
MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
enet_driver[0].txInterrupts++;
rtems_bsdnet_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
}
static rtems_isr
mcf5282_mii_interrupt_handler( rtems_vector_number v )
{
uint16_t sr2;
enet_driver[0].miiInterrupts++;
getMII(1, 19); /* Read and clear interrupt status bits */
enet_driver[0].mii_sr2 = sr2 = getMII(1, 17);
if (((sr2 & 0x200) != 0)
&& ((MCF5282_FEC_TCR & MCF5282_FEC_TCR_FDEN) == 0))
MCF5282_FEC_TCR |= MCF5282_FEC_TCR_FDEN;
else if (((sr2 & 0x200) == 0)
&& ((MCF5282_FEC_TCR & MCF5282_FEC_TCR_FDEN) != 0))
MCF5282_FEC_TCR &= ~MCF5282_FEC_TCR_FDEN;
}
/*
* Allocate buffer descriptors from (non-cached) on-chip static RAM
* Ensure 128-bit (16-byte) alignment
*/
extern char __SRAMBASE[];
static mcf5282BufferDescriptor_t *
mcf5282_bd_allocate(unsigned int count)
{
static mcf5282BufferDescriptor_t *bdp = (mcf5282BufferDescriptor_t *)__SRAMBASE;
mcf5282BufferDescriptor_t *p = bdp;
bdp += count;
if ((int)bdp & 0xF)
bdp = (mcf5282BufferDescriptor_t *)((char *)bdp + (16 - ((int)bdp & 0xF)));
return p;
}
/*
* Read MII register
* Busy-waits, but transfer time should be short!
*/
static int
getMII(int phyNumber, int regNumber)
{
MCF5282_FEC_MMFR = (0x1 << 30) |
(0x2 << 28) |
(phyNumber << 23) |
(regNumber << 18) |
(0x2 << 16);
while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
return MCF5282_FEC_MMFR & 0xFFFF;
}
/*
* Write MII register
* Busy-waits, but transfer time should be short!
*/
static void
setMII(int phyNumber, int regNumber, int value)
{
MCF5282_FEC_MMFR = (0x1 << 30) |
(0x1 << 28) |
(phyNumber << 23) |
(regNumber << 18) |
(0x2 << 16) |
(value & 0xFFFF);
while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
}
static void
mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
{
int i;
const unsigned char *hwaddr;
rtems_status_code status;
rtems_isr_entry old_handler;
uint32_t clock_speed = get_CPU_clock_speed();
/*
* Issue reset to FEC
*/
MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
rtems_task_wake_after(1);
MCF5282_FEC_ECR = 0;
/*
* Configuration of I/O ports is done outside of this function
*/
#if 0
imm->gpio.pbcnt |= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
#endif
/*
* Set our physical address
*/
hwaddr = sc->arpcom.ac_enaddr;
MCF5282_FEC_PALR = (hwaddr[0] << 24) | (hwaddr[1] << 16) |
(hwaddr[2] << 8) | (hwaddr[3] << 0);
MCF5282_FEC_PAUR = (hwaddr[4] << 24) | (hwaddr[5] << 16);
/*
* Clear the hash table
*/
MCF5282_FEC_GAUR = 0;
MCF5282_FEC_GALR = 0;
/*
* Set up receive buffer size
*/
MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf)
rtems_panic("No memory for mbuf pointers");
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
MCF5282_FEC_ETDSR = (int)sc->txBdBase;
/*
* Set up Receive Control Register:
* Not promiscuous
* MII mode
* Full duplex
* No loopback
*/
MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5282_FEC_RCR_MII_MODE;
/*
* Set up Transmit Control Register:
* Full duplex
* No heartbeat
*/
MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN;
/*
* Initialize statistic counters
*/
MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
{
vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
*vuip++ = 0;
}
MCF5282_FEC_MIBC = 0;
/*
* Set MII speed to <= 2.5 MHz
*/
i = (clock_speed + 5000000 - 1) / 5000000;
MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(i);
/*
* Set PHYS to 100 Mb/s, full duplex
*/
setMII(1, 0, 0x2100);
setMII(1, 4, 0x0181);
setMII(1, 0, 0x0000);
rtems_task_wake_after(2);
sc->mii_sr2 = getMII(1, 17);
setMII(1, 18, 0x0072);
setMII(1, 0, 0x1000);
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++)
(sc->rxBdBase + i)->status = 0;
/*
* Set up transmit buffer descriptors
*/
for (i = 0 ; i < sc->txBdCount ; i++) {
sc->txBdBase[i].status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Set up interrupts
*/
status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
rtems_status_text(status));
status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
rtems_status_text(status));
MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) |
MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 | MCF5282_INTC_IMRL_MASKALL);
MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) |
MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 | MCF5282_INTC_IMRL_MASKALL);
status = rtems_interrupt_catch(mcf5282_mii_interrupt_handler, MII_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC MII interrupt handler: %s\n",
rtems_status_text(status));
MCF5282_EPORT_EPPAR &= ~MII_EPPAR;
MCF5282_EPORT_EPDDR &= ~MII_EPDDR;
MCF5282_EPORT_EPIER |= MII_EPIER;
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT7 | MCF5282_INTC_IMRL_MASKALL);
}
/*
* Soak up buffer descriptors that have been sent.
*/
void
fec_retire_tx_bd(volatile struct mcf5282_enet_struct *sc )
{
struct mbuf *m, *n;
uint16_t status;
while ((sc->txBdActiveCount != 0)
&& (((status = sc->txBdBase[sc->txBdTail].status) & MCF5282_FEC_TxBD_R) == 0)) {
if ((status & MCF5282_FEC_TxBD_TO1) == 0) {
m = sc->txMbuf[sc->txBdTail];
MFREE(m, n);
}
if (++sc->txBdTail == sc->txBdCount)
sc->txBdTail = 0;
sc->txBdActiveCount--;
}
}
static void
fec_rxDaemon (void *arg)
{
volatile struct mcf5282_enet_struct *sc = (volatile struct mcf5282_enet_struct *)arg;
struct ifnet *ifp = (struct ifnet* )&sc->arpcom.ac_if;
struct mbuf *m;
volatile uint16_t status;
volatile mcf5282BufferDescriptor_t *rxBd;
int rxBdIndex;
/*
* Allocate space for incoming packets and start reception
*/
for (rxBdIndex = 0 ; ;) {
rxBd = sc->rxBdBase + rxBdIndex;
MGETHDR(m, M_WAIT, MT_DATA);
MCLGET(m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
rxBd->buffer = mtod(m, void *);
rxBd->status = MCF5282_FEC_RxBD_E;
if (++rxBdIndex == sc->rxBdCount) {
rxBd->status |= MCF5282_FEC_RxBD_W;
break;
}
}
/*
* Input packet handling loop
*/
/* Indicate we have some ready buffers available */
MCF5282_FEC_RDAR = 0;
rxBdIndex = 0;
for (;;) {
rxBd = sc->rxBdBase + rxBdIndex;
/*
* Wait for packet if there's not one ready
*/
if ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
/*
* Clear old events.
*/
MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
/*
* Wait for packet to arrive.
* Check the buffer descriptor before waiting for the event.
* This catches the case when a packet arrives between the
* `if' above, and the clearing of the RXF bit in the EIR.
*/
while ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
rtems_event_set events;
int level;
rtems_interrupt_disable(level);
MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_RXF;
rtems_interrupt_enable(level);
rtems_bsdnet_event_receive (RX_INTERRUPT_EVENT,
RTEMS_WAIT|RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT,
&events);
}
}
/*
* Check that packet is valid
*/
if (status & MCF5282_FEC_RxBD_L) {
/*
* Pass the packet up the chain.
* FIXME: Packet filtering hook could be done here.
*/
struct ether_header *eh;
int len = rxBd->length - sizeof(uint32_t);
/*
* Invalidate the cache and push the packet up.
* The cache is so small that it's more efficient to just
* invalidate the whole thing unless the packet is very small.
*/
m = sc->rxMbuf[rxBdIndex];
if (len < 128)
rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
else
rtems_cache_invalidate_entire_data();
m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
eh = mtod(m, struct ether_header *);
m->m_data += sizeof(struct ether_header);
ether_input(ifp, eh, m);
/*
* Allocate a new mbuf
*/
MGETHDR(m, M_WAIT, MT_DATA);
MCLGET(m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
rxBd->buffer = mtod(m, void *);
}
/*
* Reenable the buffer descriptor
*/
rxBd->status = (status & MCF5282_FEC_RxBD_W) | MCF5282_FEC_RxBD_E;
MCF5282_FEC_RDAR = 0;
/*
* Move to next buffer descriptor
*/
if (++rxBdIndex == sc->rxBdCount)
rxBdIndex = 0;
}
}
static void
fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
{
struct mcf5282_enet_struct *sc = ifp->if_softc;
volatile mcf5282BufferDescriptor_t *firstTxBd, *txBd;
int nAdded;
uint16_t status;
/*
* Free up buffer descriptors
*/
fec_retire_tx_bd(sc);
/*
* Set up the transmit buffer descriptors.
* No need to pad out short packets since the
* hardware takes care of that automatically.
* No need to copy the packet to a contiguous buffer
* since the hardware is capable of scatter/gather DMA.
*/
nAdded = 0;
firstTxBd = sc->txBdBase + sc->txBdHead;
while(m != NULL) {
/*
* Wait for buffer descriptor to become available
*/
if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
/*
* Clear old events.
*/
MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
/*
* Wait for buffer descriptor to become available.
* Check for buffer descriptors before waiting for the event.
* This catches the case when a buffer became available between
* the `if' above, and the clearing of the TXF bit in the EIR.
*/
fec_retire_tx_bd(sc);
while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
rtems_event_set events;
int level;
rtems_interrupt_disable(level);
MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF;
rtems_interrupt_enable(level);
sc->txRawWait++;
rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
RTEMS_WAIT|RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT,
&events);
fec_retire_tx_bd(sc);
}
}
/*
* Don't set the READY flag on the first fragment
* until the whole packet has been readied.
*/
status = nAdded ? MCF5282_FEC_TxBD_R : 0;
/*
* The IP fragmentation routine in ip_output
* can produce fragments with zero length.
*/
if (m->m_len){
char *p = mtod(m, char *);
int offset = (int) p & 0x3;
txBd = sc->txBdBase + sc->txBdHead;
if (offset == 0) {
txBd->buffer = p;
txBd->length = m->m_len;
sc->txMbuf[sc->txBdHead] = m;
m = m->m_next;
}
else {
/*
* Stupid FEC can't handle misaligned data!
* Move offending bytes to a local buffer.
* Use buffer descriptor TO1 bit to indicate this.
*/
int nmove = 4 - offset;
char *d = (char *)&sc->txMbuf[sc->txBdHead];
status |= MCF5282_FEC_TxBD_TO1;
sc->txRealign++;
if (nmove > m->m_len)
nmove = m->m_len;
m->m_data += nmove;
m->m_len -= nmove;
txBd->buffer = d;
txBd->length = nmove;
while (nmove--)
*d++ = *p++;
if (m->m_len == 0) {
struct mbuf *n;
sc->txRealignDrop++;
MFREE(m, n);
m = n;
}
}
nAdded++;
if (++sc->txBdHead == sc->txBdCount) {
status |= MCF5282_FEC_TxBD_W;
sc->txBdHead = 0;
}
txBd->status = status;
}
else {
/*
* Just toss empty mbufs
*/
struct mbuf *n;
MFREE(m, n);
m = n;
}
}
if (nAdded) {
txBd->status = status | MCF5282_FEC_TxBD_R
| MCF5282_FEC_TxBD_L
| MCF5282_FEC_TxBD_TC;
if (nAdded > 1)
firstTxBd->status |= MCF5282_FEC_TxBD_R;
MCF5282_FEC_TDAR = 0;
sc->txBdActiveCount += nAdded;
}
}
void
fec_txDaemon(void *arg)
{
struct mcf5282_enet_struct *sc = (struct mcf5282_enet_struct *)arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
struct mbuf *m;
rtems_event_set events;
for (;;) {
/*
* Wait for packet
*/
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events);
/*
* Send packets till queue is empty
*/
for (;;) {
/*
* Get the next mbuf chain to transmit.
*/
IF_DEQUEUE(&ifp->if_snd, m);
if (!m)
break;
fec_sendpacket(ifp, m);
}
ifp->if_flags &= ~IFF_OACTIVE;
}
}
/*
* Send packet (caller provides header).
*/
static void
mcf5282_enet_start(struct ifnet *ifp)
{
struct mcf5282_enet_struct *sc = ifp->if_softc;
rtems_bsdnet_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT);
ifp->if_flags |= IFF_OACTIVE;
}
static void
fec_init(void *arg)
{
struct mcf5282_enet_struct *sc = arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
if (sc->txDaemonTid == 0) {
/*
* Set up hardware
*/
mcf5282_fec_initialize_hardware(sc);
/*
* Start driver tasks
*/
sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc);
sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc);
}
/*
* Set flags appropriately
*/
if (ifp->if_flags & IFF_PROMISC)
MCF5282_FEC_RCR |= MCF5282_FEC_RCR_PROM;
else
MCF5282_FEC_RCR &= ~MCF5282_FEC_RCR_PROM;
/*
* Tell the world that we're running.
*/
ifp->if_flags |= IFF_RUNNING;
/*
* Enable receiver and transmitter
*/
MCF5282_FEC_ECR = MCF5282_FEC_ECR_ETHER_EN;
}
static void
fec_stop(struct mcf5282_enet_struct *sc)
{
struct ifnet *ifp = &sc->arpcom.ac_if;
ifp->if_flags &= ~IFF_RUNNING;
/*
* Shut down receiver and transmitter
*/
MCF5282_FEC_ECR = 0x0;
}
/*
* Show interface statistics
*/
static void
enet_stats(struct mcf5282_enet_struct *sc)
{
printf(" Rx Interrupts:%-10lu", sc->rxInterrupts);
printf("Rx Packet Count:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_PACKETS);
printf(" Rx Broadcast:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_BC_PKT);
printf(" Rx Multicast:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_MC_PKT);
printf("CRC/Align error:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_CRC_ALIGN);
printf(" Rx Undersize:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_UNDERSIZE);
printf(" Rx Oversize:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_OVERSIZE);
printf(" Rx Fragment:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_FRAG);
printf(" Rx Jabber:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_JAB);
printf(" Rx 64:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P64);
printf(" Rx 65-127:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P65T0127);
printf(" Rx 128-255:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_P128TO255);
printf(" Rx 256-511:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P256TO511);
printf(" Rx 511-1023:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P512TO1023);
printf(" Rx 1024-2047:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_P1024TO2047);
printf(" Rx >=2048:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_GTE2048);
printf(" Rx Octets:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_OCTETS);
printf(" Rx Dropped:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_R_DROP);
printf(" Rx frame OK:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_FRAME_OK);
printf(" Rx CRC error:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_CRC);
printf(" Rx Align error:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_R_ALIGN);
printf(" FIFO Overflow:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_MACERR);
printf("Rx Pause Frames:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_FDXFC);
printf(" Rx Octets OK:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_R_OCTETS_OK);
printf(" Tx Interrupts:%-10lu", sc->txInterrupts);
printf("Tx Output Waits:%-10lu", sc->txRawWait);
printf("Tx mbuf realign:%-10lu\n", sc->txRealign);
printf("Tx realign drop:%-10lu", sc->txRealignDrop);
printf(" Tx Unaccounted:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_DROP);
printf("Tx Packet Count:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_PACKETS);
printf(" Tx Broadcast:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_BC_PKT);
printf(" Tx Multicast:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_MC_PKT);
printf("CRC/Align error:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_CRC_ALIGN);
printf(" Tx Undersize:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_UNDERSIZE);
printf(" Tx Oversize:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_OVERSIZE);
printf(" Tx Fragment:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_FRAG);
printf(" Tx Jabber:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_JAB);
printf(" Tx Collisions:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_COL);
printf(" Tx 64:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_P64);
printf(" Tx 65-127:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P65TO127);
printf(" Tx 128-255:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P128TO255);
printf(" Tx 256-511:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_P256TO511);
printf(" Tx 511-1023:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P512TO1023);
printf(" Tx 1024-2047:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P1024TO2047);
printf(" Tx >=2048:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_P_GTE2048);
printf(" Tx Octets:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_OCTETS);
printf(" Tx Dropped:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_DROP);
printf(" Tx Frame OK:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_FRAME_OK);
printf(" Tx 1 Collision:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_1COL);
printf("Tx >1 Collision:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_MCOL);
printf(" Tx Deferred:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_DEF);
printf(" Late Collision:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_LCOL);
printf(" Excessive Coll:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_EXCOL);
printf(" FIFO Underrun:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_MACERR);
printf(" Carrier Error:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_CSERR);
printf(" Tx SQE Error:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_SQE);
printf("Tx Pause Frames:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_FDXFC);
printf(" Tx Octets OK:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_OCTETS_OK);
printf(" MII interrupts:%-10lu\n", sc->miiInterrupts);
printf(" EIR:%8.8lx ", (uint32_t) MCF5282_FEC_EIR);
printf("EIMR:%8.8lx ", (uint32_t) MCF5282_FEC_EIMR);
printf("RDAR:%8.8lx ", (uint32_t) MCF5282_FEC_RDAR);
printf("TDAR:%8.8lx\n", (uint32_t) MCF5282_FEC_TDAR);
printf(" ECR:%8.8lx ", (uint32_t) MCF5282_FEC_ECR);
printf(" RCR:%8.8lx ", (uint32_t) MCF5282_FEC_RCR);
printf(" TCR:%8.8lx\n", (uint32_t) MCF5282_FEC_TCR);
printf("FRBR:%8.8lx ", (uint32_t) MCF5282_FEC_FRBR);
printf("FRSR:%8.8lx\n", (uint32_t) MCF5282_FEC_FRSR);
if (sc->txBdActiveCount != 0) {
int i, n;
/*
* Yes, there are races here with adding and retiring descriptors,
* but this diagnostic is more for when things have backed up.
*/
printf("Transmit Buffer Descriptors (Tail %d, Head %d, Unretired %d):\n",
sc->txBdTail,
sc->txBdHead,
sc->txBdActiveCount);
i = sc->txBdTail;
for (n = 0 ; n < sc->txBdCount ; n++) {
if ((sc->txBdBase[i].status & MCF5282_FEC_TxBD_R) != 0)
printf(" %3d: status:%4.4x length:%-4d buffer:%p\n",
i,
sc->txBdBase[i].status,
sc->txBdBase[i].length,
sc->txBdBase[i].buffer);
if (++i == sc->txBdCount)
i = 0;
}
}
}
static int
fec_ioctl(struct ifnet *ifp, ioctl_command_t command, caddr_t data)
{
struct mcf5282_enet_struct *sc = ifp->if_softc;
int error = 0;
switch (command) {
case SIOCGIFADDR:
case SIOCSIFADDR:
ether_ioctl(ifp, command, data);
break;
case SIOCSIFFLAGS:
switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
case IFF_RUNNING:
fec_stop(sc);
break;
case IFF_UP:
fec_init(sc);
break;
case IFF_UP | IFF_RUNNING:
fec_stop(sc);
fec_init(sc);
break;
default:
break;
}
break;
case SIO_RTEMS_SHOW_STATS:
enet_stats(sc);
break;
/*
* FIXME: All sorts of multicast commands need to be added here!
*/
default:
error = EINVAL;
break;
}
return error;
}
int
rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching )
{
struct mcf5282_enet_struct *sc;
struct ifnet *ifp;
int mtu;
int unitNumber;
char *unitName;
unsigned char *hwaddr;
/*
* Parse driver name
*/
if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
return 0;
/*
* Is driver free?
*/
if ((unitNumber <= 0) || (unitNumber > NIFACES)) {
printf("Bad FEC unit number.\n");
return 0;
}
sc = &enet_driver[unitNumber - 1];
ifp = &sc->arpcom.ac_if;
if (ifp->if_softc != NULL) {
printf("Driver already in use.\n");
return 0;
}
/*
* Process options
*/
printf("%s%d: Ethernet address: ", unitName, unitNumber );
if (config->hardware_address) {
hwaddr = config->hardware_address;
printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
hwaddr[0], hwaddr[1], hwaddr[2],
hwaddr[3], hwaddr[4], hwaddr[5]);
memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);
} else {
printf("UNKNOWN\n");
}
if (config->mtu)
mtu = config->mtu;
else
mtu = ETHERMTU;
if (config->rbuf_count)
sc->rxBdCount = config->rbuf_count;
else
sc->rxBdCount = RX_BUF_COUNT;
if (config->xbuf_count)
sc->txBdCount = config->xbuf_count;
else
sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
sc->acceptBroadcast = !config->ignore_broadcast;
/*
* Set up network interface values
*/
ifp->if_softc = sc;
ifp->if_unit = unitNumber;
ifp->if_name = unitName;
ifp->if_mtu = mtu;
ifp->if_init = fec_init;
ifp->if_ioctl = fec_ioctl;
ifp->if_start = mcf5282_enet_start;
ifp->if_output = ether_output;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
if (ifp->if_snd.ifq_maxlen == 0)
ifp->if_snd.ifq_maxlen = ifqmaxlen;
/*
* Attach the interface
*/
if_attach(ifp);
ether_ifattach(ifp);
return 1;
};

984
bsps/m68k/csb360/net/network.c
View File

@@ -1,984 +0,0 @@
/*
* RTEMS/TCPIP driver for MCF5272 Ethernet
*
* Modified for MPC860 by Jay Monkman (jmonkman@lopingdog.com)
*
* This supports Ethernet on either SCC1 or the FEC of the MPC860T.
* Right now, we only do 10 Mbps, even with the FEC. The function
* rtems_enet_driver_attach determines which one to use. Currently,
* only one may be used at a time.
*
* Based on the MC68360 network driver by
* W. Eric Norum
* Saskatchewan Accelerator Laboratory
* University of Saskatchewan
* Saskatoon, Saskatchewan, CANADA
* eric@skatter.usask.ca
*
* This supports ethernet on SCC1. Right now, we only do 10 Mbps.
*
* Modifications by Darlene Stewart <Darlene.Stewart@iit.nrc.ca>
* and Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca>
* Copyright (c) 1999, National Research Council of Canada
*/
#include <machine/rtems-bsd-kernel-space.h>
#include <bsp.h>
#include <stdio.h>
#include <rtems/error.h>
#include <rtems/rtems_bsdnet.h>
#include <sys/param.h>
#include <sys/mbuf.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <net/if.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
#include <sys/types.h>
#include <sys/socket.h>
/*
* Number of interfaces supported by this driver
*/
#define NIFACES 1
/*
* Default number of buffer descriptors set aside for this driver.
* The number of transmit buffer descriptors has to be quite large
* since a single frame often uses four or more buffer descriptors.
*/
#define RX_BUF_COUNT 32
#define TX_BUF_COUNT 16
#define TX_BD_PER_BUF 4
#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
/*
* RTEMS event used by interrupt handler to signal daemons.
* This must *not* be the same event used by the TCP/IP task synchronization.
*/
#define INTERRUPT_EVENT RTEMS_EVENT_1
/*
* RTEMS event used to start transmit daemon.
* This must not be the same as INTERRUPT_EVENT.
*/
#define START_TRANSMIT_EVENT RTEMS_EVENT_2
/*
* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
* Round off to nearest multiple of RBUF_ALIGN.
*/
#define MAX_MTU_SIZE 1518
#define RBUF_ALIGN 4
#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
#if (MCLBYTES < RBUF_SIZE)
# error "Driver must have MCLBYTES > RBUF_SIZE"
#endif
typedef struct {
uint16_t status;
uint16_t length;
void *buffer;
} bd_t;
#define MCF5272_BD_READY (bit(15))
#define MCF5272_BD_TO1 (bit(14))
#define MCF5272_BD_WRAP (bit(13))
#define MCF5272_BD_TO2 (bit(12))
#define MCF5272_BD_LAST (bit(11))
#define MCF5272_BD_TX_CRC (bit(10))
#define MCF5272_BD_DEFER (bit(9))
#define MCF5272_BD_HEARTBEAT (bit(8))
#define MCF5272_BD_LATE_COLLISION (bit(7))
#define MCF5272_BD_RETRY_LIMIT (bit(6))
#define MCF5272_BD_UNDERRUN (bit(1))
#define MCF5272_BD_CARRIER_LOST (bit(0))
#define MCF5272_BD_EMPTY (bit(15))
#define MCF5272_BD_RO1 (bit(14))
#define MCF5272_BD_WRAP (bit(13))
#define MCF5272_BD_RO2 (bit(12))
#define MCF5272_BD_M (bit(8))
#define MCF5272_BD_BC (bit(7))
#define MCF5272_BD_MC (bit(6))
#define MCF5272_BD_LONG (bit(5))
#define MCF5272_BD_NONALIGNED (bit(4))
#define MCF5272_BD_SHORT (bit(3))
#define MCF5272_BD_CRC_ERROR (bit(2))
#define MCF5272_BD_OVERRUN (bit(1))
#define MCF5272_BD_TRUNCATED (bit(0))
/*
* Per-device data
*/
struct mcf5272_enet_struct {
struct arpcom arpcom;
struct mbuf **rxMbuf;
struct mbuf **txMbuf;
int acceptBroadcast;
int rxBdCount;
int txBdCount;
int txBdHead;
int txBdTail;
int txBdActiveCount;
bd_t *rxBdBase;
bd_t *txBdBase;
rtems_id rxDaemonTid;
rtems_id txDaemonTid;
/*
* Statistics
*/
unsigned long rxInterrupts;
unsigned long rxNotFirst;
unsigned long rxNotLast;
unsigned long rxGiant;
unsigned long rxNonOctet;
unsigned long rxRunt;
unsigned long rxBadCRC;
unsigned long rxOverrun;
unsigned long rxTruncated;
unsigned long txInterrupts;
unsigned long txDeferred;
unsigned long txHeartbeat;
unsigned long txLateCollision;
unsigned long txRetryLimit;
unsigned long txUnderrun;
unsigned long txLostCarrier;
unsigned long txRawWait;
};
static struct mcf5272_enet_struct enet_driver[NIFACES];
void dump_enet_regs(void)
{
printf("**************************************************************\n");
printf("ecr: 0x%08x eir: 0x%08x eimr: 0x%08x ivsr: 0x%08x\n\r",
g_enet_regs->ecr, g_enet_regs->eir,
g_enet_regs->eimr, g_enet_regs->ivsr);
printf("rdar: 0x%08x tdar: 0x%08x mmfr: 0x%08x mscr: 0x%08x\n\r",
g_enet_regs->rdar, g_enet_regs->tdar,
g_enet_regs->mmfr, g_enet_regs->mscr);
printf("frbr: 0x%08x frsr: 0x%08x tfwr: 0x%08x tfsr: 0x%08x\n\r",
g_enet_regs->frbr, g_enet_regs->frsr,
g_enet_regs->tfwr, g_enet_regs->tfsr);
printf("rcr: 0x%08x mflr: 0x%08x tcr: 0x%08x malr: 0x%08x\n\r",
g_enet_regs->rcr, g_enet_regs->mflr,
g_enet_regs->tcr, g_enet_regs->malr);
printf("maur: 0x%08x htur: 0x%08x htlr: 0x%08x erdsr: 0x%08x\n\r",
g_enet_regs->maur, g_enet_regs->htur,
g_enet_regs->htlr, g_enet_regs->erdsr);
printf("etdsr: 0x%08x emrbr: 0x%08x\n\r",
g_enet_regs->etdsr, g_enet_regs->emrbr);
}
/*#define cp printk("%s:%d\n\r", __FUNCTION__, __LINE__) */
#define cp
#define mcf5272_bd_allocate(_n_) malloc((_n_) * sizeof(bd_t), 0, M_NOWAIT)
rtems_isr enet_rx_isr(rtems_vector_number vector)
{
cp;
/*
* Frame received?
*/
if (g_enet_regs->eir & MCF5272_ENET_EIR_RXF) {
cp;
g_enet_regs->eir = MCF5272_ENET_EIR_RXF;
enet_driver[0].rxInterrupts++;
rtems_bsdnet_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT);
}
cp;
}
rtems_isr enet_tx_isr(rtems_vector_number vector)
{
cp;
/*
* Buffer transmitted or transmitter error?
*/
if (g_enet_regs->eir & MCF5272_ENET_EIR_TXF) {
cp;
g_enet_regs->eir = MCF5272_ENET_EIR_TXF;
enet_driver[0].txInterrupts++;
rtems_bsdnet_event_send (enet_driver[0].txDaemonTid, INTERRUPT_EVENT);
}
cp;
}
/*
* Initialize the ethernet hardware
*/
static void
mcf5272_enet_initialize_hardware (struct mcf5272_enet_struct *sc)
{
int i;
unsigned char *hwaddr;
uint32_t icr;
/*
* Issue reset to FEC
*/
g_enet_regs->ecr=0x1;
/*
* Set the TX and RX fifo sizes. For now, we'll split it evenly
*/
/* If you uncomment these, the FEC will not work right.
g_enet_regs->r_fstart = ((g_enet_regs->r_bound & 0x3ff) >> 2) & 0x3ff;
g_enet_regs->x_fstart = 0;
*/
/* Copy mac address to device */
hwaddr = sc->arpcom.ac_enaddr;
g_enet_regs->malr = (hwaddr[0] << 24 |
hwaddr[1] << 16 |
hwaddr[2] << 8 |
hwaddr[3]);
g_enet_regs->maur = (hwaddr[4] << 24 |
hwaddr[5] << 16);
/*
* Clear the hash table
*/
g_enet_regs->htlr = 0;
g_enet_regs->htur = 0;
/*
* Set up receive buffer size
*/
g_enet_regs->emrbr = 0x5f0; /* set to 1520 */
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
M_MBUF, M_NOWAIT);
sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf) {
rtems_panic ("No memory for mbuf pointers");
}
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = mcf5272_bd_allocate(sc->rxBdCount);
sc->txBdBase = mcf5272_bd_allocate(sc->txBdCount);
g_enet_regs->erdsr = (int)sc->rxBdBase;
g_enet_regs->etdsr = (int)sc->txBdBase;
/*
* Set up Receive Control Register:
* Not promiscuous mode
* MII mode
* Full duplex
* No loopback
*/
g_enet_regs->rcr = 0x00000004;
/*
* Set up Transmit Control Register:
* Full duplex
* No heartbeat
*/
g_enet_regs->tcr = 0x00000004;
/*
* Set MII speed to 2.5 MHz for 25 Mhz system clock
*/
g_enet_regs->mscr = 0x0a;
g_enet_regs->mmfr = 0x58021000;
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++) {
(sc->rxBdBase + i)->status = 0;
}
/*
* Set up transmit buffer descriptors
*/
for (i = 0 ; i < sc->txBdCount ; i++) {
(sc->txBdBase + i)->status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Mask all FEC interrupts and clear events
*/
g_enet_regs->eimr = (MCF5272_ENET_EIR_TXF |
MCF5272_ENET_EIR_RXF);
g_enet_regs->eir = ~0;
/*
* Set up interrupts
*/
set_vector(enet_rx_isr, BSP_INTVEC_ERX, 1);
set_vector(enet_tx_isr, BSP_INTVEC_ETX, 1);
/* Configure ethernet interrupts */
icr = g_intctrl_regs->icr3;
icr = icr & ~((MCF5272_ICR3_ERX_MASK | MCF5272_ICR3_ERX_PI) |
(MCF5272_ICR3_ETX_MASK | MCF5272_ICR3_ETX_PI));
icr |= ((MCF5272_ICR3_ERX_IPL(BSP_INTLVL_ERX) | MCF5272_ICR3_ERX_PI)|
(MCF5272_ICR3_ETX_IPL(BSP_INTLVL_ETX) | MCF5272_ICR3_ETX_PI));
g_intctrl_regs->icr3 = icr;
}
/*
* Soak up buffer descriptors that have been sent.
* Note that a buffer descriptor can't be retired as soon as it becomes
* ready. The MPC860 manual (MPC860UM/AD 07/98 Rev.1) and the MPC821
* manual state that, "If an Ethernet frame is made up of multiple
* buffers, the user should not reuse the first buffer descriptor until
* the last buffer descriptor of the frame has had its ready bit cleared
* by the CPM".
*/
static void
mcf5272_enet_retire_tx_bd (struct mcf5272_enet_struct *sc)
{
uint16_t status;
int i;
int nRetired;
struct mbuf *m, *n;
i = sc->txBdTail;
nRetired = 0;
while ((sc->txBdActiveCount != 0) &&
(((status = sc->txBdBase[i].status) & MCF5272_BD_READY) == 0)) {
/*
* See if anything went wrong
*/
if (status & (MCF5272_BD_DEFER |
MCF5272_BD_HEARTBEAT |
MCF5272_BD_LATE_COLLISION |
MCF5272_BD_RETRY_LIMIT |
MCF5272_BD_UNDERRUN |
MCF5272_BD_CARRIER_LOST)) {
/*
* Check for errors which stop the transmitter.
*/
if (status & (MCF5272_BD_LATE_COLLISION |
MCF5272_BD_RETRY_LIMIT |
MCF5272_BD_UNDERRUN)) {
if (status & MCF5272_BD_LATE_COLLISION) {
enet_driver[0].txLateCollision++;
}
if (status & MCF5272_BD_RETRY_LIMIT) {
enet_driver[0].txRetryLimit++;
}
if (status & MCF5272_BD_UNDERRUN) {
enet_driver[0].txUnderrun++;
}
}
if (status & MCF5272_BD_DEFER) {
enet_driver[0].txDeferred++;
}
if (status & MCF5272_BD_HEARTBEAT) {
enet_driver[0].txHeartbeat++;
}
if (status & MCF5272_BD_CARRIER_LOST) {
enet_driver[0].txLostCarrier++;
}
}
nRetired++;
if (status & MCF5272_BD_LAST) {
/*
* A full frame has been transmitted.
* Free all the associated buffer descriptors.
*/
sc->txBdActiveCount -= nRetired;
while (nRetired) {
nRetired--;
m = sc->txMbuf[sc->txBdTail];
MFREE (m, n);
if (++sc->txBdTail == sc->txBdCount)
sc->txBdTail = 0;
}
}
if (++i == sc->txBdCount) {
i = 0;
}
}
}
static void
mcf5272_enet_rxDaemon (void *arg)
{
struct mcf5272_enet_struct *sc = (struct mcf5272_enet_struct *)arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
struct mbuf *m;
uint16_t status;
bd_t *rxBd;
int rxBdIndex;
/*
* Allocate space for incoming packets and start reception
*/
for (rxBdIndex = 0 ; ;) {
rxBd = sc->rxBdBase + rxBdIndex;
MGETHDR (m, M_WAIT, MT_DATA);
MCLGET (m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
rxBd->buffer = mtod (m, void *);
rxBd->status = MCF5272_BD_EMPTY;
g_enet_regs->rdar = 0x1000000;
if (++rxBdIndex == sc->rxBdCount) {
rxBd->status |= MCF5272_BD_WRAP;
break;
}
}
/*
* Input packet handling loop
*/
rxBdIndex = 0;
for (;;) {
rxBd = sc->rxBdBase + rxBdIndex;
/*
* Wait for packet if there's not one ready
*/
if ((status = rxBd->status) & MCF5272_BD_EMPTY) {
/*
* Clear old events
*/
g_enet_regs->eir = MCF5272_ENET_EIR_RXF;
/*
* Wait for packet
* Note that the buffer descriptor is checked
* *before* the event wait -- this catches the
* possibility that a packet arrived between the
* `if' above, and the clearing of the event register.
*/
while ((status = rxBd->status) & MCF5272_BD_EMPTY) {
rtems_event_set events;
/*
* Unmask RXF (Full frame received) event
*/
g_enet_regs->eir |= MCF5272_ENET_EIR_RXF;
rtems_bsdnet_event_receive (INTERRUPT_EVENT,
RTEMS_WAIT|RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT,
&events);
cp;
}
}
cp;
/*
* Check that packet is valid
*/
if (status & MCF5272_BD_LAST) {
/*
* Pass the packet up the chain.
* FIXME: Packet filtering hook could be done here.
*/
struct ether_header *eh;
m = sc->rxMbuf[rxBdIndex];
m->m_len = m->m_pkthdr.len = (rxBd->length -
sizeof(uint32_t) -
sizeof(struct ether_header));
eh = mtod (m, struct ether_header *);
m->m_data += sizeof(struct ether_header);
ether_input (ifp, eh, m);
/*
* Allocate a new mbuf
*/
MGETHDR (m, M_WAIT, MT_DATA);
MCLGET (m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
rxBd->buffer = mtod (m, void *);
}
else {
/*
* Something went wrong with the reception
*/
if (!(status & MCF5272_BD_LAST)) {
sc->rxNotLast++;
}
if (status & MCF5272_BD_LONG) {
sc->rxGiant++;
}
if (status & MCF5272_BD_NONALIGNED) {
sc->rxNonOctet++;
}
if (status & MCF5272_BD_SHORT) {
sc->rxRunt++;
}
if (status & MCF5272_BD_CRC_ERROR) {
sc->rxBadCRC++;
}
if (status & MCF5272_BD_OVERRUN) {
sc->rxOverrun++;
}
if (status & MCF5272_BD_TRUNCATED) {
sc->rxTruncated++;
}
}
/*
* Reenable the buffer descriptor
*/
rxBd->status = (status & MCF5272_BD_WRAP) | MCF5272_BD_EMPTY;
g_enet_regs->rdar = 0x1000000;
/*
* Move to next buffer descriptor
*/
if (++rxBdIndex == sc->rxBdCount) {
rxBdIndex = 0;
}
}
}
static void
mcf5272_enet_sendpacket (struct ifnet *ifp, struct mbuf *m)
{
struct mcf5272_enet_struct *sc = ifp->if_softc;
volatile bd_t *firstTxBd, *txBd;
/* struct mbuf *l = NULL; */
uint16_t status;
int nAdded;
cp;
/*
* Free up buffer descriptors
*/
mcf5272_enet_retire_tx_bd (sc);
/*
* Set up the transmit buffer descriptors.
* No need to pad out short packets since the
* hardware takes care of that automatically.
* No need to copy the packet to a contiguous buffer
* since the hardware is capable of scatter/gather DMA.
*/
nAdded = 0;
txBd = firstTxBd = sc->txBdBase + sc->txBdHead;
for (;;) {
cp;
/*
* Wait for buffer descriptor to become available.
*/
if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
/*
* Clear old events
*/
g_enet_regs->eir = MCF5272_ENET_EIR_TXF;
/*
* Wait for buffer descriptor to become available.
* Note that the buffer descriptors are checked
* *before* * entering the wait loop -- this catches
* the possibility that a buffer descriptor became
* available between the `if' above, and the clearing
* of the event register.
* This is to catch the case where the transmitter
* stops in the middle of a frame -- and only the
* last buffer descriptor in a frame can generate
* an interrupt.
*/
mcf5272_enet_retire_tx_bd (sc);
while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
rtems_event_set events;
cp;
/*
* Unmask TXB (buffer transmitted) and
* TXE (transmitter error) events.
*/
g_enet_regs->eir |= MCF5272_ENET_EIR_TXF;
rtems_bsdnet_event_receive (INTERRUPT_EVENT,
RTEMS_WAIT|RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT,
&events);
cp;
mcf5272_enet_retire_tx_bd (sc);
}
}
/*
* Don't set the READY flag till the
* whole packet has been readied.
*/
status = nAdded ? MCF5272_BD_READY : 0;
cp;
/*
* FIXME: Why not deal with empty mbufs at at higher level?
* The IP fragmentation routine in ip_output
* can produce packet fragments with zero length.
* I think that ip_output should be changed to get
* rid of these zero-length mbufs, but for now,
* I'll deal with them here.
*/
if (m->m_len) {
cp;
/*
* Fill in the buffer descriptor
*/
txBd->buffer = mtod (m, void *);
txBd->length = m->m_len;
sc->txMbuf[sc->txBdHead] = m;
nAdded++;
if (++sc->txBdHead == sc->txBdCount) {
status |= MCF5272_BD_WRAP;
sc->txBdHead = 0;
}
/* l = m;*/
m = m->m_next;
}
else {
/*
* Just toss empty mbufs
*/
struct mbuf *n;
cp;
MFREE (m, n);
m = n;
/*
if (l != NULL)
l->m_next = m;
*/
}
/*
* Set the transmit buffer status.
* Break out of the loop if this mbuf is the last in the frame.
*/
if (m == NULL) {
cp;
if (nAdded) {
cp;
status |= MCF5272_BD_LAST | MCF5272_BD_TX_CRC;
txBd->status = status;
firstTxBd->status |= MCF5272_BD_READY;
g_enet_regs->tdar = 0x1000000;
sc->txBdActiveCount += nAdded;
}
break;
}
txBd->status = status;
txBd = sc->txBdBase + sc->txBdHead;
}
cp;
/*
dump_enet_regs();
dump_intctrl;
*/
}
void
mcf5272_enet_txDaemon (void *arg)
{
struct mcf5272_enet_struct *sc = (struct mcf5272_enet_struct *)arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
struct mbuf *m;
rtems_event_set events;
cp;
for (;;) {
/*
* Wait for packet
*/
rtems_bsdnet_event_receive (START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events);
cp;
/*
* Send packets till queue is empty
*/
cp;
for (;;) {
cp;
/*
* Get the next mbuf chain to transmit.
*/
IF_DEQUEUE(&ifp->if_snd, m);
if (!m)
break;
mcf5272_enet_sendpacket (ifp, m);
}
ifp->if_flags &= ~IFF_OACTIVE;
}
}
/*
* Send packet (caller provides header).
*/
static void
mcf5272_enet_start (struct ifnet *ifp)
{
struct mcf5272_enet_struct *sc = ifp->if_softc;
cp;
rtems_bsdnet_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT);
cp;
ifp->if_flags |= IFF_OACTIVE;
}
static void
mcf5272_enet_init (void *arg)
{
struct mcf5272_enet_struct *sc = arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
if (sc->txDaemonTid == 0) {
/*
* Set up SCC hardware
*/
mcf5272_enet_initialize_hardware (sc);
/*
* Start driver tasks
*/
sc->txDaemonTid = rtems_bsdnet_newproc("SCtx",
4096,
mcf5272_enet_txDaemon,
sc);
sc->rxDaemonTid = rtems_bsdnet_newproc("SCrx",
4096,
mcf5272_enet_rxDaemon,
sc);
}
/*
* Set flags appropriately
*/
if (ifp->if_flags & IFF_PROMISC) {
g_enet_regs->rcr |= 0x8;
} else {
g_enet_regs->rcr &= ~0x8;
}
/*
* Tell the world that we're running.
*/
ifp->if_flags |= IFF_RUNNING;
/*
* Enable receiver and transmitter
*/
g_enet_regs->ecr = 0x2;
}
static void
mcf5272_enet_stop (struct mcf5272_enet_struct *sc)
{
struct ifnet *ifp = &sc->arpcom.ac_if;
ifp->if_flags &= ~IFF_RUNNING;
/*
* Shut down receiver and transmitter
*/
g_enet_regs->ecr = 0x0;
}
/*
* Show interface statistics
*/
static void
enet_stats (struct mcf5272_enet_struct *sc)
{
printf (" Rx Interrupts:%-8lu", sc->rxInterrupts);
printf (" Not First:%-8lu", sc->rxNotFirst);
printf (" Not Last:%-8lu\n", sc->rxNotLast);
printf (" Giant:%-8lu", sc->rxGiant);
printf (" Runt:%-8lu", sc->rxRunt);
printf (" Non-octet:%-8lu\n", sc->rxNonOctet);
printf (" Bad CRC:%-8lu", sc->rxBadCRC);
printf (" Overrun:%-8lu", sc->rxOverrun);
printf (" Truncated:%-8lu\n", sc->rxTruncated);
/* printf (" Discarded:%-8lu\n", (unsigned long)mcf5272.scc1p.un.ethernet.disfc); */
printf (" Tx Interrupts:%-8lu", sc->txInterrupts);
printf (" Deferred:%-8lu", sc->txDeferred);
printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat);
printf (" No Carrier:%-8lu", sc->txLostCarrier);
printf ("Retransmit Limit:%-8lu", sc->txRetryLimit);
printf (" Late Collision:%-8lu\n", sc->txLateCollision);
printf (" Underrun:%-8lu", sc->txUnderrun);
printf (" Raw output wait:%-8lu\n", sc->txRawWait);
}
/*
* Driver ioctl handler
*/
static int
mcf5272_enet_ioctl (struct ifnet *ifp, int command, caddr_t data)
{
struct mcf5272_enet_struct *sc = ifp->if_softc;
int error = 0;
switch (command) {
case SIOCGIFADDR:
case SIOCSIFADDR:
ether_ioctl (ifp, command, data);
break;
case SIOCSIFFLAGS:
switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
case IFF_RUNNING:
mcf5272_enet_stop (sc);
break;
case IFF_UP:
mcf5272_enet_init (sc);
break;
case IFF_UP | IFF_RUNNING:
mcf5272_enet_stop (sc);
mcf5272_enet_init (sc);
break;
default:
break;
}
break;
case SIO_RTEMS_SHOW_STATS:
enet_stats (sc);
break;
/*
* FIXME: All sorts of multicast commands need to be added here!
*/
default:
error = EINVAL;
break;
}
return error;
}
int
rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config)
{
struct mcf5272_enet_struct *sc;
struct ifnet *ifp;
int mtu;
int unitNumber;
char *unitName;
/*
* Parse driver name
*/
unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName);
if (unitNumber < 0){
return 0;
}
/*
* Is driver free?
*/
if ((unitNumber < 0) || (unitNumber > NIFACES)) {
printf ("Bad unit number: %d.\n", unitNumber);
return 0;
}
sc = &enet_driver[unitNumber];
ifp = &sc->arpcom.ac_if;
if (ifp->if_softc != NULL) {
printf ("Driver already in use.\n");
return 0;
}
/*
* Process options
*/
sc->arpcom.ac_enaddr[0] = (g_enet_regs->malr >> 24) & 0xff;
sc->arpcom.ac_enaddr[1] = (g_enet_regs->malr >> 16) & 0xff;
sc->arpcom.ac_enaddr[2] = (g_enet_regs->malr >> 8) & 0xff;
sc->arpcom.ac_enaddr[3] = (g_enet_regs->malr >> 0) & 0xff;
sc->arpcom.ac_enaddr[4] = (g_enet_regs->maur >> 24) & 0xff;
sc->arpcom.ac_enaddr[5] = (g_enet_regs->maur >> 16) & 0xff;
if (config->mtu) {
mtu = config->mtu;
} else {
mtu = ETHERMTU;
}
if (config->rbuf_count) {
sc->rxBdCount = config->rbuf_count;
} else {
sc->rxBdCount = RX_BUF_COUNT;
}
if (config->xbuf_count) {
sc->txBdCount = config->xbuf_count;
} else {
sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
}
sc->acceptBroadcast = !config->ignore_broadcast;
/*
* Set up network interface values
*/
ifp->if_softc = sc;
ifp->if_unit = unitNumber;
ifp->if_name = unitName;
ifp->if_mtu = mtu;
ifp->if_init = mcf5272_enet_init;
ifp->if_ioctl = mcf5272_enet_ioctl;
ifp->if_start = mcf5272_enet_start;
ifp->if_output = ether_output;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
if (ifp->if_snd.ifq_maxlen == 0) {
ifp->if_snd.ifq_maxlen = ifqmaxlen;
}
/*
* Attach the interface
*/
if_attach (ifp);
cp;
ether_ifattach (ifp);
cp;
return 1;
};

1062
bsps/m68k/gen68360/net/network.c
View File

File diff suppressed because it is too large Load Diff

1696
bsps/m68k/genmcf548x/net/network.c
View File

File diff suppressed because it is too large Load Diff

879
bsps/m68k/mcf5235/net/network.c
View File

@@ -1,879 +0,0 @@
/*
* RTEMS/TCPIP driver for MCF5235 Fast Ethernet Controller
*
* TO DO: Check network stack code -- force longword alignment of all tx mbufs?
*/
#include <machine/rtems-bsd-kernel-space.h>
#include <bsp.h>
#include <stdio.h>
#include <errno.h>
#include <stdarg.h>
#include <string.h>
#include <rtems.h>
#include <rtems/error.h>
#include <rtems/rtems_bsdnet.h>
#include <sys/param.h>
#include <sys/mbuf.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
/*
* Number of interfaces supported by this driver
*/
#define NIFACES 1
#define FEC_INTC0_TX_VECTOR (64+23)
#define FEC_INTC0_RX_VECTOR (64+27)
/*
* Default number of buffer descriptors set aside for this driver.
* The number of transmit buffer descriptors has to be quite large
* since a single frame often uses three or more buffer descriptors.
*/
#define RX_BUF_COUNT 32
#define TX_BUF_COUNT 20
#define TX_BD_PER_BUF 3
#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
/*
* RTEMS event used by interrupt handler to signal daemons.
* This must *not* be the same event used by the TCP/IP task synchronization.
*/
#define TX_INTERRUPT_EVENT RTEMS_EVENT_1
#define RX_INTERRUPT_EVENT RTEMS_EVENT_1
/*
* RTEMS event used to start transmit daemon.
* This must not be the same as INTERRUPT_EVENT.
*/
#define START_TRANSMIT_EVENT RTEMS_EVENT_2
/*
* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
* Round off to nearest multiple of RBUF_ALIGN.
*/
#define MAX_MTU_SIZE 1518
#define RBUF_ALIGN 4
#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
#if (MCLBYTES < RBUF_SIZE)
#error "Driver must have MCLBYTES > RBUF_SIZE"
#endif
typedef struct mcf5235BufferDescriptor_ {
volatile uint16_t status;
uint16_t length;
volatile void *buffer;
} mcf5235BufferDescriptor_t;
/*
* Per-device data
*/
struct mcf5235_enet_struct {
struct arpcom arpcom;
struct mbuf **rxMbuf;
struct mbuf **txMbuf;
int acceptBroadcast;
int rxBdCount;
int txBdCount;
int txBdHead;
int txBdTail;
int txBdActiveCount;
mcf5235BufferDescriptor_t *rxBdBase;
mcf5235BufferDescriptor_t *txBdBase;
rtems_id rxDaemonTid;
rtems_id txDaemonTid;
/*
* Statistics
*/
unsigned long rxInterrupts;
unsigned long txInterrupts;
unsigned long txRawWait;
unsigned long txRealign;
};
static struct mcf5235_enet_struct enet_driver[NIFACES];
static rtems_isr
mcf5235_fec_rx_interrupt_handler( rtems_vector_number v )
{
MCF5235_FEC_EIR = MCF5235_FEC_EIR_RXF;
MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_RXF;
enet_driver[0].rxInterrupts++;
rtems_bsdnet_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
}
static rtems_isr
mcf5235_fec_tx_interrupt_handler( rtems_vector_number v )
{
MCF5235_FEC_EIR = MCF5235_FEC_EIR_TXF;
MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_TXF;
enet_driver[0].txInterrupts++;
rtems_bsdnet_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
}
/*
* Allocate buffer descriptors from (non-cached) on-chip static RAM
* Ensure 128-bit (16-byte) alignment
*/
extern char __SRAMBASE[];
static mcf5235BufferDescriptor_t *
mcf5235_bd_allocate(unsigned int count)
{
static mcf5235BufferDescriptor_t *bdp = (mcf5235BufferDescriptor_t *)__SRAMBASE;
mcf5235BufferDescriptor_t *p = bdp;
bdp += count;
if ((int)bdp & 0xF)
bdp = (mcf5235BufferDescriptor_t *)((char *)bdp + (16 - ((int)bdp & 0xF)));
return p;
}
#if UNUSED
/*
* Read MII register
* Busy-waits, but transfer time should be short!
*/
static int
getMII(int phyNumber, int regNumber)
{
MCF5235_FEC_MMFR = (0x1 << 30) |
(0x2 << 28) |
(phyNumber << 23) |
(regNumber << 18) |
(0x2 << 16);
while ((MCF5235_FEC_EIR & MCF5235_FEC_EIR_MII) == 0);
MCF5235_FEC_EIR = MCF5235_FEC_EIR_MII;
return MCF5235_FEC_MMFR & 0xFFFF;
}
#endif
/*
* Write MII register
* Busy-waits, but transfer time should be short!
*/
static void
setMII(int phyNumber, int regNumber, int value)
{
MCF5235_FEC_MMFR = (0x1 << 30) |
(0x1 << 28) |
(phyNumber << 23) |
(regNumber << 18) |
(0x2 << 16) |
(value & 0xFFFF);
while ((MCF5235_FEC_EIR & MCF5235_FEC_EIR_MII) == 0);
MCF5235_FEC_EIR = MCF5235_FEC_EIR_MII;
}
static void
mcf5235_fec_initialize_hardware(struct mcf5235_enet_struct *sc)
{
int i;
const unsigned char *hwaddr = 0;
rtems_status_code status;
rtems_isr_entry old_handler;
uint32_t clock_speed = get_CPU_clock_speed();
/*
* Issue reset to FEC
*/
MCF5235_FEC_ECR = MCF5235_FEC_ECR_RESET;
rtems_task_wake_after(1);
MCF5235_FEC_ECR = 0;
/*
* Configuration of I/O ports is done outside of this function
*/
#if 0
imm->gpio.pbcnt |= MCF5235_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
#endif
/*
* Set our physical address
*/
hwaddr = sc->arpcom.ac_enaddr;
MCF5235_FEC_PALR = (hwaddr[0] << 24) | (hwaddr[1] << 16) |
(hwaddr[2] << 8) | (hwaddr[3] << 0);
MCF5235_FEC_PAUR = (hwaddr[4] << 24) | (hwaddr[5] << 16);
/*
* Clear the hash table
*/
MCF5235_FEC_GAUR = 0;
MCF5235_FEC_GALR = 0;
/*
* Set up receive buffer size
*/
MCF5235_FEC_EMRBR = 1520; /* Standard Ethernet */
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf)
rtems_panic("No memory for mbuf pointers");
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = mcf5235_bd_allocate(sc->rxBdCount);
sc->txBdBase = mcf5235_bd_allocate(sc->txBdCount);
MCF5235_FEC_ERDSR = (int)sc->rxBdBase;
MCF5235_FEC_ETDSR = (int)sc->txBdBase;
/*
* Set up Receive Control Register:
* Not promiscuous
* MII mode
* Full duplex
* No loopback
*/
MCF5235_FEC_RCR = MCF5235_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5235_FEC_RCR_MII_MODE;
/*
* Set up Transmit Control Register:
* Full duplex
* No heartbeat
*/
MCF5235_FEC_TCR = MCF5235_FEC_TCR_FDEN;
/*
* Initialize statistic counters
*/
MCF5235_FEC_MIBC = MCF5235_FEC_MIBC_MIB_DISABLE;
{
vuint32 *vuip = &MCF5235_FEC_RMON_T_DROP;
while (vuip <= &MCF5235_FEC_IEEE_R_OCTETS_OK)
*vuip++ = 0;
}
MCF5235_FEC_MIBC = 0;
/*
* Set MII speed to <= 2.5 MHz
*/
i = (clock_speed + 5000000 - 1) / 5000000;
MCF5235_FEC_MSCR = MCF5235_FEC_MSCR_MII_SPEED(i);
/*
* Set PHYS to 100 Mb/s, full duplex
*/
setMII(1, 0, 0x2100);
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++)
(sc->rxBdBase + i)->status = 0;
/*
* Set up transmit buffer descriptors
*/
for (i = 0 ; i < sc->txBdCount ; i++) {
sc->txBdBase[i].status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Set up interrupts
*/
status = rtems_interrupt_catch( mcf5235_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5235 FEC TX interrupt handler: %s\n",
rtems_status_text(status));
status = rtems_interrupt_catch(mcf5235_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5235 FEC RX interrupt handler: %s\n",
rtems_status_text(status));
MCF5235_INTC0_ICR23 = MCF5235_INTC_ICR_IL(FEC_IRQ_LEVEL) |
MCF5235_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
MCF5235_INTC0_IMRL &= ~(MCF5235_INTC0_IMRL_INT23 | MCF5235_INTC0_IMRL_MASKALL);
MCF5235_INTC0_ICR27 = MCF5235_INTC_ICR_IL(FEC_IRQ_LEVEL) |
MCF5235_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
MCF5235_INTC0_IMRL &= ~(MCF5235_INTC0_IMRL_INT27 | MCF5235_INTC0_IMRL_MASKALL);
}
/*
* Get the MAC address from the hardware.
*/
static void
fec_get_mac_address(volatile struct mcf5235_enet_struct *sc, unsigned char* hwaddr)
{
unsigned long addr;
addr = MCF5235_FEC_PALR;
hwaddr[0] = (addr >> 24) & 0xff;
hwaddr[1] = (addr >> 16) & 0xff;
hwaddr[2] = (addr >> 8) & 0xff;
hwaddr[3] = (addr >> 0) & 0xff;
addr = MCF5235_FEC_PAUR;
hwaddr[4] = (addr >> 24) & 0xff;
hwaddr[5] = (addr >> 16) & 0xff;
}
/*
* Soak up buffer descriptors that have been sent.
*/
static void
fec_retire_tx_bd(volatile struct mcf5235_enet_struct *sc )
{
struct mbuf *m, *n;
while ((sc->txBdActiveCount != 0)
&& ((sc->txBdBase[sc->txBdTail].status & MCF5235_FEC_TxBD_R) == 0)) {
m = sc->txMbuf[sc->txBdTail];
MFREE(m, n);
if (++sc->txBdTail == sc->txBdCount)
sc->txBdTail = 0;
sc->txBdActiveCount--;
}
}
static void
fec_rxDaemon (void *arg)
{
volatile struct mcf5235_enet_struct *sc = (volatile struct mcf5235_enet_struct *)arg;
struct ifnet *ifp = (struct ifnet* )&sc->arpcom.ac_if;
struct mbuf *m;
volatile uint16_t status;
volatile mcf5235BufferDescriptor_t *rxBd;
int rxBdIndex;
/*
* Allocate space for incoming packets and start reception
*/
for (rxBdIndex = 0 ; ;) {
rxBd = sc->rxBdBase + rxBdIndex;
MGETHDR(m, M_WAIT, MT_DATA);
MCLGET(m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
rxBd->buffer = mtod(m, void *);
rxBd->status = MCF5235_FEC_RxBD_E;
if (++rxBdIndex == sc->rxBdCount) {
rxBd->status |= MCF5235_FEC_RxBD_W;
break;
}
}
/*
* Input packet handling loop
*/
/* Indicate we have some ready buffers available */
MCF5235_FEC_RDAR = MCF5235_FEC_RDAR_R_DES_ACTIVE;
rxBdIndex = 0;
for (;;) {
rxBd = sc->rxBdBase + rxBdIndex;
/*
* Wait for packet if there's not one ready
*/
if ((status = rxBd->status) & MCF5235_FEC_RxBD_E) {
/*
* Clear old events.
*/
MCF5235_FEC_EIR = MCF5235_FEC_EIR_RXF;
/*
* Wait for packet to arrive.
* Check the buffer descriptor before waiting for the event.
* This catches the case when a packet arrives between the
* `if' above, and the clearing of the RXF bit in the EIR.
*/
while ((status = rxBd->status) & MCF5235_FEC_RxBD_E) {
rtems_event_set events;
int level;
rtems_interrupt_disable(level);
MCF5235_FEC_EIMR |= MCF5235_FEC_EIMR_RXF;
rtems_interrupt_enable(level);
rtems_bsdnet_event_receive (RX_INTERRUPT_EVENT,
RTEMS_WAIT|RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT,
&events);
}
}
/*
* Check that packet is valid
*/
if (status & MCF5235_FEC_RxBD_L) {
/*
* Pass the packet up the chain.
* FIXME: Packet filtering hook could be done here.
*/
struct ether_header *eh;
int len = rxBd->length - sizeof(uint32_t);
/*
* Invalidate the cache and push the packet up.
* The cache is so small that it's more efficient to just
* invalidate the whole thing unless the packet is very small.
*/
m = sc->rxMbuf[rxBdIndex];
if (len < 128)
rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
else
rtems_cache_invalidate_entire_data();
m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
eh = mtod(m, struct ether_header *);
m->m_data += sizeof(struct ether_header);
ether_input(ifp, eh, m);
/*
* Allocate a new mbuf
*/
MGETHDR(m, M_WAIT, MT_DATA);
MCLGET(m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
rxBd->buffer = mtod(m, void *);
}
/*
* Reenable the buffer descriptor
*/
rxBd->status = (status & MCF5235_FEC_RxBD_W) | MCF5235_FEC_RxBD_E;
MCF5235_FEC_RDAR = MCF5235_FEC_RDAR_R_DES_ACTIVE;
/*
* Move to next buffer descriptor
*/
if (++rxBdIndex == sc->rxBdCount)
rxBdIndex = 0;
}
}
static void
fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
{
struct mcf5235_enet_struct *sc = ifp->if_softc;
volatile mcf5235BufferDescriptor_t *firstTxBd, *txBd;
uint16_t status;
int nAdded;
/*
* Free up buffer descriptors
*/
fec_retire_tx_bd(sc);
/*
* Set up the transmit buffer descriptors.
* No need to pad out short packets since the
* hardware takes care of that automatically.
* No need to copy the packet to a contiguous buffer
* since the hardware is capable of scatter/gather DMA.
*/
nAdded = 0;
firstTxBd = sc->txBdBase + sc->txBdHead;
for (;;) {
/*
* Wait for buffer descriptor to become available
*/
if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
/*
* Clear old events.
*/
MCF5235_FEC_EIR = MCF5235_FEC_EIR_TXF;
/*
* Wait for buffer descriptor to become available.
* Check for buffer descriptors before waiting for the event.
* This catches the case when a buffer became available between
* the `if' above, and the clearing of the TXF bit in the EIR.
*/
fec_retire_tx_bd(sc);
while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
rtems_event_set events;
int level;
rtems_interrupt_disable(level);
MCF5235_FEC_EIMR |= MCF5235_FEC_EIMR_TXF;
rtems_interrupt_enable(level);
sc->txRawWait++;
rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
RTEMS_WAIT|RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT,
&events);
fec_retire_tx_bd(sc);
}
}
/*
* Don't set the READY flag on the first fragment
* until the whole packet has been readied.
*/
status = nAdded ? MCF5235_FEC_TxBD_R : 0;
/*
* The IP fragmentation routine in ip_output
* can produce fragments with zero length.
*/
txBd = sc->txBdBase + sc->txBdHead;
if (m->m_len) {
char *p = mtod(m, char *);
/*
* Stupid FEC can't handle misaligned data!
* Given the way that mbuf's are layed out it should be
* safe to shuffle the data down like this.....
* Perhaps this code could be improved with a "Duff's Device".
*/
if ((int)p & 0x3) {
int l = m->m_len;
char *dest = p - ((int)p & 0x3);
uint16_t *o = (uint16_t *)dest, *i = (uint16_t *)p;
while (l > 0) {
*o++ = *i++;
l -= sizeof(uint16_t);
}
p = dest;
sc->txRealign++;
}
txBd->buffer = p;
txBd->length = m->m_len;
sc->txMbuf[sc->txBdHead] = m;
nAdded++;
if (++sc->txBdHead == sc->txBdCount) {
status |= MCF5235_FEC_TxBD_W;
sc->txBdHead = 0;
}
m = m->m_next;
}
else {
/*
* Just toss empty mbufs
*/
struct mbuf *n;
MFREE(m, n);
m = n;
}
if (m == NULL) {
if (nAdded) {
txBd->status = status | MCF5235_FEC_TxBD_R
| MCF5235_FEC_TxBD_L
| MCF5235_FEC_TxBD_TC;
if (nAdded > 1)
firstTxBd->status |= MCF5235_FEC_TxBD_R;
MCF5235_FEC_TDAR = MCF5235_FEC_TDAR_X_DES_ACTIVE;
sc->txBdActiveCount += nAdded;
}
break;
}
txBd->status = status;
}
}
void
fec_txDaemon(void *arg)
{
struct mcf5235_enet_struct *sc = (struct mcf5235_enet_struct *)arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
struct mbuf *m;
rtems_event_set events;
for (;;) {
/*
* Wait for packet
*/
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events);
/*
* Send packets till queue is empty
*/
for (;;) {
/*
* Get the next mbuf chain to transmit.
*/
IF_DEQUEUE(&ifp->if_snd, m);
if (!m)
break;
fec_sendpacket(ifp, m);
}
ifp->if_flags &= ~IFF_OACTIVE;
}
}
/*
* Send packet (caller provides header).
*/
static void
mcf5235_enet_start(struct ifnet *ifp)
{
struct mcf5235_enet_struct *sc = ifp->if_softc;
rtems_bsdnet_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT);
ifp->if_flags |= IFF_OACTIVE;
}
static void
fec_init(void *arg)
{
struct mcf5235_enet_struct *sc = arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
if (sc->txDaemonTid == 0) {
/*
* Set up hardware
*/
mcf5235_fec_initialize_hardware(sc);
/*
* Start driver tasks
*/
sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc);
sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc);
}
/*
* Set flags appropriately
*/
if (ifp->if_flags & IFF_PROMISC)
MCF5235_FEC_RCR |= MCF5235_FEC_RCR_PROM;
else
MCF5235_FEC_RCR &= ~MCF5235_FEC_RCR_PROM;
/*
* Tell the world that we're running.
*/
ifp->if_flags |= IFF_RUNNING;
/*
* Enable receiver and transmitter
*/
MCF5235_FEC_ECR = MCF5235_FEC_ECR_ETHER_EN;
}
static void
fec_stop(struct mcf5235_enet_struct *sc)
{
struct ifnet *ifp = &sc->arpcom.ac_if;
ifp->if_flags &= ~IFF_RUNNING;
/*
* Shut down receiver and transmitter
*/
MCF5235_FEC_ECR = 0x0;
}
/*
* Show interface statistics
*/
static void
enet_stats(struct mcf5235_enet_struct *sc)
{
printf(" Rx Interrupts:%-10lu", sc->rxInterrupts);
printf("Rx Packet Count:%-10lu", MCF5235_FEC_RMON_R_PACKETS);
printf(" Rx Broadcast:%-10lu\n", MCF5235_FEC_RMON_R_BC_PKT);
printf(" Rx Multicast:%-10lu", MCF5235_FEC_RMON_R_MC_PKT);
printf("CRC/Align error:%-10lu", MCF5235_FEC_RMON_R_CRC_ALIGN);
printf(" Rx Undersize:%-10lu\n", MCF5235_FEC_RMON_R_UNDERSIZE);
printf(" Rx Oversize:%-10lu", MCF5235_FEC_RMON_R_OVERSIZE);
printf(" Rx Fragment:%-10lu", MCF5235_FEC_RMON_R_FRAG);
printf(" Rx Jabber:%-10lu\n", MCF5235_FEC_RMON_R_JAB);
printf(" Rx 64:%-10lu", MCF5235_FEC_RMON_R_P64);
printf(" Rx 65-127:%-10lu", MCF5235_FEC_RMON_R_P65T0127);
printf(" Rx 128-255:%-10lu\n", MCF5235_FEC_RMON_R_P128TO255);
printf(" Rx 256-511:%-10lu", MCF5235_FEC_RMON_R_P256TO511);
printf(" Rx 511-1023:%-10lu", MCF5235_FEC_RMON_R_P512TO1023);
printf(" Rx 1024-2047:%-10lu\n", MCF5235_FEC_RMON_R_P1024TO2047);
printf(" Rx >=2048:%-10lu", MCF5235_FEC_RMON_R_GTE2048);
printf(" Rx Octets:%-10lu", MCF5235_FEC_RMON_R_OCTETS);
printf(" Rx Dropped:%-10lu\n", MCF5235_FEC_IEEE_R_DROP);
printf(" Rx frame OK:%-10lu", MCF5235_FEC_IEEE_R_FRAME_OK);
printf(" Rx CRC error:%-10lu", MCF5235_FEC_IEEE_R_CRC);
printf(" Rx Align error:%-10lu\n", MCF5235_FEC_IEEE_R_ALIGN);
printf(" FIFO Overflow:%-10lu", MCF5235_FEC_IEEE_R_MACERR);
printf("Rx Pause Frames:%-10lu", MCF5235_FEC_IEEE_R_FDXFC);
printf(" Rx Octets OK:%-10lu\n", MCF5235_FEC_IEEE_R_OCTETS_OK);
printf(" Tx Interrupts:%-10lu", sc->txInterrupts);
printf("Tx Output Waits:%-10lu", sc->txRawWait);
printf("Tx Realignments:%-10lu\n", sc->txRealign);
printf(" Tx Unaccounted:%-10lu", MCF5235_FEC_RMON_T_DROP);
printf("Tx Packet Count:%-10lu", MCF5235_FEC_RMON_T_PACKETS);
printf(" Tx Broadcast:%-10lu\n", MCF5235_FEC_RMON_T_BC_PKT);
printf(" Tx Multicast:%-10lu", MCF5235_FEC_RMON_T_MC_PKT);
printf("CRC/Align error:%-10lu", MCF5235_FEC_RMON_T_CRC_ALIGN);
printf(" Tx Undersize:%-10lu\n", MCF5235_FEC_RMON_T_UNDERSIZE);
printf(" Tx Oversize:%-10lu", MCF5235_FEC_RMON_T_OVERSIZE);
printf(" Tx Fragment:%-10lu", MCF5235_FEC_RMON_T_FRAG);
printf(" Tx Jabber:%-10lu\n", MCF5235_FEC_RMON_T_JAB);
printf(" Tx Collisions:%-10lu", MCF5235_FEC_RMON_T_COL);
printf(" Tx 64:%-10lu", MCF5235_FEC_RMON_T_P64);
printf(" Tx 65-127:%-10lu\n", MCF5235_FEC_RMON_T_P65TO127);
printf(" Tx 128-255:%-10lu", MCF5235_FEC_RMON_T_P128TO255);
printf(" Tx 256-511:%-10lu", MCF5235_FEC_RMON_T_P256TO511);
printf(" Tx 511-1023:%-10lu\n", MCF5235_FEC_RMON_T_P512TO1023);
printf(" Tx 1024-2047:%-10lu", MCF5235_FEC_RMON_T_P1024TO2047);
printf(" Tx >=2048:%-10lu", MCF5235_FEC_RMON_T_P_GTE2048);
printf(" Tx Octets:%-10lu\n", MCF5235_FEC_RMON_T_OCTETS);
printf(" Tx Dropped:%-10lu", MCF5235_FEC_IEEE_T_DROP);
printf(" Tx Frame OK:%-10lu", MCF5235_FEC_IEEE_T_FRAME_OK);
printf(" Tx 1 Collision:%-10lu\n", MCF5235_FEC_IEEE_T_1COL);
printf("Tx >1 Collision:%-10lu", MCF5235_FEC_IEEE_T_MCOL);
printf(" Tx Deferred:%-10lu", MCF5235_FEC_IEEE_T_DEF);
printf(" Late Collision:%-10lu\n", MCF5235_FEC_IEEE_T_LCOL);
printf(" Excessive Coll:%-10lu", MCF5235_FEC_IEEE_T_EXCOL);
printf(" FIFO Underrun:%-10lu", MCF5235_FEC_IEEE_T_MACERR);
printf(" Carrier Error:%-10lu\n", MCF5235_FEC_IEEE_T_CSERR);
printf(" Tx SQE Error:%-10lu", MCF5235_FEC_IEEE_T_SQE);
printf("Tx Pause Frames:%-10lu", MCF5235_FEC_IEEE_T_FDXFC);
printf(" Tx Octets OK:%-10lu\n", MCF5235_FEC_IEEE_T_OCTETS_OK);
}
static int
fec_ioctl(struct ifnet *ifp, ioctl_command_t command, caddr_t data)
{
struct mcf5235_enet_struct *sc = ifp->if_softc;
int error = 0;
switch (command) {
case SIOCGIFADDR:
case SIOCSIFADDR:
ether_ioctl(ifp, command, data);
break;
case SIOCSIFFLAGS:
switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
case IFF_RUNNING:
fec_stop(sc);
break;
case IFF_UP:
fec_init(sc);
break;
case IFF_UP | IFF_RUNNING:
fec_stop(sc);
fec_init(sc);
break;
default:
break;
}
break;
case SIO_RTEMS_SHOW_STATS:
enet_stats(sc);
break;
/*
* FIXME: All sorts of multicast commands need to be added here!
*/
default:
error = EINVAL;
break;
}
return error;
}
int
rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching )
{
struct mcf5235_enet_struct *sc;
struct ifnet *ifp;
int mtu;
int unitNumber;
char *unitName;
unsigned char *hwaddr;
/*
* Parse driver name
*/
if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
return 0;
/*
* Is driver free?
*/
if ((unitNumber < 0) || (unitNumber >= NIFACES)) {
printf("mcf5235: bad FEC unit number.\n");
return 0;
}
sc = &enet_driver[unitNumber];
ifp = &sc->arpcom.ac_if;
if (ifp->if_softc != NULL) {
printf("mcf5235: driver already in use.\n");
return 0;
}
/*
* Process options
*/
if (config->hardware_address)
memcpy(sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN);
else
fec_get_mac_address(sc, sc->arpcom.ac_enaddr);
hwaddr = config->hardware_address;
printf("%s%d: mac: %02x:%02x:%02x:%02x:%02x:%02x\n",
unitName, unitNumber,
hwaddr[0], hwaddr[1], hwaddr[2],
hwaddr[3], hwaddr[4], hwaddr[5]);
if (config->mtu)
mtu = config->mtu;
else
mtu = ETHERMTU;
if (config->rbuf_count)
sc->rxBdCount = config->rbuf_count;
else
sc->rxBdCount = RX_BUF_COUNT;
if (config->xbuf_count)
sc->txBdCount = config->xbuf_count;
else
sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
sc->acceptBroadcast = !config->ignore_broadcast;
/*
* Set up network interface values
*/
ifp->if_softc = sc;
ifp->if_unit = unitNumber;
ifp->if_name = unitName;
ifp->if_mtu = mtu;
ifp->if_init = fec_init;
ifp->if_ioctl = fec_ioctl;
ifp->if_start = mcf5235_enet_start;
ifp->if_output = ether_output;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
if (ifp->if_snd.ifq_maxlen == 0)
ifp->if_snd.ifq_maxlen = ifqmaxlen;
/*
* Attach the interface
*/
if_attach(ifp);
ether_ifattach(ifp);
return 1;
};

857
bsps/m68k/mcf5329/net/network.c
View File

@@ -1,857 +0,0 @@
/*
* RTEMS/TCPIP driver for MCF5329 Fast Ethernet Controller
*
* TO DO: Check network stack code -- force longword alignment of all tx mbufs?
*/
#include <machine/rtems-bsd-kernel-space.h>
#include <bsp.h>
#include <stdio.h>
#include <errno.h>
#include <stdarg.h>
#include <string.h>
#include <rtems.h>
#include <rtems/error.h>
#include <rtems/rtems_bsdnet.h>
#include <sys/param.h>
#include <sys/mbuf.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
/*
* Number of interfaces supported by this driver
*/
#define NIFACES 1
#define FEC_INTC0_TX_VECTOR (64+36)
#define FEC_INTC0_RX_VECTOR (64+40)
/*
* Default number of buffer descriptors set aside for this driver.
* The number of transmit buffer descriptors has to be quite large
* since a single frame often uses three or more buffer descriptors.
*/
#define RX_BUF_COUNT 32
#define TX_BUF_COUNT 20
#define TX_BD_PER_BUF 3
#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
/*
* RTEMS event used by interrupt handler to signal daemons.
* This must *not* be the same event used by the TCP/IP task synchronization.
*/
#define TX_INTERRUPT_EVENT RTEMS_EVENT_1
#define RX_INTERRUPT_EVENT RTEMS_EVENT_1
/*
* RTEMS event used to start transmit daemon.
* This must not be the same as INTERRUPT_EVENT.
*/
#define START_TRANSMIT_EVENT RTEMS_EVENT_2
/*
* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
* Round off to nearest multiple of RBUF_ALIGN.
*/
#define MAX_MTU_SIZE 1518
#define RBUF_ALIGN 4
#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
#if (MCLBYTES < RBUF_SIZE)
# error "Driver must have MCLBYTES > RBUF_SIZE"
#endif
typedef struct mcf5329BufferDescriptor_
{
volatile uint16_t status;
uint16_t length;
volatile void *buffer;
} mcf5329BufferDescriptor_t;
/*
* Per-device data
*/
struct mcf5329_enet_struct
{
struct arpcom arpcom;
struct mbuf **rxMbuf;
struct mbuf **txMbuf;
int acceptBroadcast;
int rxBdCount;
int txBdCount;
int txBdHead;
int txBdTail;
int txBdActiveCount;
mcf5329BufferDescriptor_t *rxBdBase;
mcf5329BufferDescriptor_t *txBdBase;
rtems_id rxDaemonTid;
rtems_id txDaemonTid;
/*
* Statistics
*/
unsigned long rxInterrupts;
unsigned long txInterrupts;
unsigned long txRawWait;
unsigned long txRealign;
};
static struct mcf5329_enet_struct enet_driver[NIFACES];
static rtems_isr mcf5329_fec_rx_interrupt_handler(rtems_vector_number v)
{
MCF_FEC_EIR = MCF_FEC_EIR_RXF;
MCF_FEC_EIMR &= ~MCF_FEC_EIMR_RXF;
enet_driver[0].rxInterrupts++;
rtems_bsdnet_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
}
static rtems_isr mcf5329_fec_tx_interrupt_handler(rtems_vector_number v)
{
MCF_FEC_EIR = MCF_FEC_EIR_TXF;
MCF_FEC_EIMR &= ~MCF_FEC_EIMR_TXF;
enet_driver[0].txInterrupts++;
rtems_bsdnet_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
}
extern char _CoreSRamBase[];
/*
* Allocate buffer descriptors from (non-cached) on-chip static RAM
* Ensure 128-bit (16-byte) alignment
*/
static mcf5329BufferDescriptor_t *mcf5329_bd_allocate(unsigned int count)
{
static mcf5329BufferDescriptor_t *bdp =
(mcf5329BufferDescriptor_t *) _CoreSRamBase;
mcf5329BufferDescriptor_t *p = bdp;
bdp += count;
if ((int) bdp & 0xF)
bdp =
(mcf5329BufferDescriptor_t *) ((char *) bdp + (16 - ((int) bdp & 0xF)));
return p;
}
#if UNUSED
/*
* Read MII register
* Busy-waits, but transfer time should be short!
*/
static int getMII(int phyNumber, int regNumber)
{
MCF_FEC_MMFR = (0x1 << 30) |
(0x2 << 28) | (phyNumber << 23) | (regNumber << 18) | (0x2 << 16);
while ((MCF_FEC_EIR & MCF_FEC_EIR_MII) == 0) ;
MCF_FEC_EIR = MCF_FEC_EIR_MII;
return MCF_FEC_MMFR & 0xFFFF;
}
#endif
/*
* Write MII register
* Busy-waits, but transfer time should be short!
*/
static void setMII(int phyNumber, int regNumber, int value)
{
MCF_FEC_MMFR = (0x1 << 30) |
(0x1 << 28) |
(phyNumber << 23) | (regNumber << 18) | (0x2 << 16) | (value & 0xFFFF);
while ((MCF_FEC_EIR & MCF_FEC_EIR_MII) == 0) ;
MCF_FEC_EIR = MCF_FEC_EIR_MII;
}
static void mcf5329_fec_initialize_hardware(struct mcf5329_enet_struct *sc)
{
int i;
const unsigned char *hwaddr = 0;
rtems_status_code status;
rtems_isr_entry old_handler;
uint32_t clock_speed = bsp_get_BUS_clock_speed();
/*
* Issue reset to FEC
*/
MCF_FEC_ECR = MCF_FEC_ECR_RESET;
rtems_task_wake_after(1);
MCF_FEC_ECR = 0;
/*
* Configuration of I/O ports is done outside of this function
*/
#if 0
imm->gpio.pbcnt |= MCF_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
#endif
/*
* Set our physical address
*/
hwaddr = sc->arpcom.ac_enaddr;
MCF_FEC_PALR = (hwaddr[0] << 24) | (hwaddr[1] << 16) |
(hwaddr[2] << 8) | (hwaddr[3] << 0);
MCF_FEC_PAUR = (hwaddr[4] << 24) | (hwaddr[5] << 16);
/*
* Clear the hash table
*/
MCF_FEC_GAUR = 0;
MCF_FEC_GALR = 0;
/*
* Set up receive buffer size
*/
MCF_FEC_EMRBR = 1520; /* Standard Ethernet */
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf)
rtems_panic("No memory for mbuf pointers");
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = mcf5329_bd_allocate(sc->rxBdCount);
sc->txBdBase = mcf5329_bd_allocate(sc->txBdCount);
MCF_FEC_ERDSR = (int) sc->rxBdBase;
MCF_FEC_ETDSR = (int) sc->txBdBase;
/*
* Set up Receive Control Register:
* Not promiscuous
* MII mode
* Full duplex
* No loopback
*/
MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL(MAX_MTU_SIZE) | MCF_FEC_RCR_MII_MODE;
/*
* Set up Transmit Control Register:
* Full duplex
* No heartbeat
*/
MCF_FEC_TCR = MCF_FEC_TCR_FDEN;
/*
* Initialize statistic counters
*/
MCF_FEC_MIBC = MCF_FEC_MIBC_MIB_DISABLE;
{
vuint32 *vuip = &MCF_FEC_RMON_T_DROP;
while (vuip <= &MCF_FEC_IEEE_R_OCTETS_OK)
*vuip++ = 0;
}
MCF_FEC_MIBC = 0;
/*
* Set MII speed to <= 2.5 MHz
*/
i = (clock_speed + 5000000 - 1) / 5000000;
MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED(i);
/*
* Set PHYS to 100 Mb/s, full duplex
*/
setMII(1, 0, 0x2100);
/*
* Set up receive buffer descriptors
*/
for (i = 0; i < sc->rxBdCount; i++)
(sc->rxBdBase + i)->status = 0;
/*
* Set up transmit buffer descriptors
*/
for (i = 0; i < sc->txBdCount; i++) {
sc->txBdBase[i].status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Set up interrupts
*/
status =
rtems_interrupt_catch(mcf5329_fec_tx_interrupt_handler,
FEC_INTC0_TX_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic("Can't attach MCF FEC TX interrupt handler: %s\n",
rtems_status_text(status));
status =
rtems_interrupt_catch(mcf5329_fec_rx_interrupt_handler,
FEC_INTC0_RX_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic("Can't attach MCF FEC RX interrupt handler: %s\n",
rtems_status_text(status));
MCF_INTC0_ICR36 = MCF_INTC_ICR_IL(FEC_IRQ_LEVEL);
MCF_INTC0_IMRH &= ~(MCF_INTC_IMRH_INT_MASK36);
MCF_INTC0_ICR40 = MCF_INTC_ICR_IL(FEC_IRQ_LEVEL);
MCF_INTC0_IMRH &= ~(MCF_INTC_IMRH_INT_MASK40);
}
/*
* Get the MAC address from the hardware.
*/
static void
fec_get_mac_address(volatile struct mcf5329_enet_struct *sc,
unsigned char *hwaddr)
{
unsigned long addr;
addr = MCF_FEC_PALR;
hwaddr[0] = (addr >> 24) & 0xff;
hwaddr[1] = (addr >> 16) & 0xff;
hwaddr[2] = (addr >> 8) & 0xff;
hwaddr[3] = (addr >> 0) & 0xff;
addr = MCF_FEC_PAUR;
hwaddr[4] = (addr >> 24) & 0xff;
hwaddr[5] = (addr >> 16) & 0xff;
}
/*
* Soak up buffer descriptors that have been sent.
*/
static void fec_retire_tx_bd(volatile struct mcf5329_enet_struct *sc)
{
struct mbuf *m, *n;
while ((sc->txBdActiveCount != 0)
&& ((sc->txBdBase[sc->txBdTail].status & MCF_FEC_TxBD_R) == 0)) {
m = sc->txMbuf[sc->txBdTail];
MFREE(m, n);
if (++sc->txBdTail == sc->txBdCount)
sc->txBdTail = 0;
sc->txBdActiveCount--;
}
}
static void fec_rxDaemon(void *arg)
{
volatile struct mcf5329_enet_struct *sc =
(volatile struct mcf5329_enet_struct *) arg;
struct ifnet *ifp = (struct ifnet *) &sc->arpcom.ac_if;
struct mbuf *m;
volatile uint16_t status;
volatile mcf5329BufferDescriptor_t *rxBd;
int rxBdIndex;
/*
* Allocate space for incoming packets and start reception
*/
for (rxBdIndex = 0;;) {
rxBd = sc->rxBdBase + rxBdIndex;
MGETHDR(m, M_WAIT, MT_DATA);
MCLGET(m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
rxBd->buffer = mtod(m, void *);
rxBd->status = MCF_FEC_RxBD_E;
if (++rxBdIndex == sc->rxBdCount) {
rxBd->status |= MCF_FEC_RxBD_W;
break;
}
}
/*
* Input packet handling loop
*/
/* Indicate we have some ready buffers available */
MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
rxBdIndex = 0;
for (;;) {
rxBd = sc->rxBdBase + rxBdIndex;
/*
* Wait for packet if there's not one ready
*/
if ((status = rxBd->status) & MCF_FEC_RxBD_E) {
/*
* Clear old events.
*/
MCF_FEC_EIR = MCF_FEC_EIR_RXF;
/*
* Wait for packet to arrive.
* Check the buffer descriptor before waiting for the event.
* This catches the case when a packet arrives between the
* `if' above, and the clearing of the RXF bit in the EIR.
*/
while ((status = rxBd->status) & MCF_FEC_RxBD_E) {
rtems_event_set events;
int level;
rtems_interrupt_disable(level);
MCF_FEC_EIMR |= MCF_FEC_EIMR_RXF;
rtems_interrupt_enable(level);
rtems_bsdnet_event_receive(RX_INTERRUPT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT, &events);
}
}
/*
* Check that packet is valid
*/
if (status & MCF_FEC_RxBD_L) {
/*
* Pass the packet up the chain.
* FIXME: Packet filtering hook could be done here.
*/
struct ether_header *eh;
int len = rxBd->length - sizeof(uint32_t);
m = sc->rxMbuf[rxBdIndex];
rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
eh = mtod(m, struct ether_header *);
m->m_data += sizeof(struct ether_header);
ether_input(ifp, eh, m);
/*
* Allocate a new mbuf
*/
MGETHDR(m, M_WAIT, MT_DATA);
MCLGET(m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
rxBd->buffer = mtod(m, void *);
}
/*
* Reenable the buffer descriptor
*/
rxBd->status = (status & MCF_FEC_RxBD_W) | MCF_FEC_RxBD_E;
MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
/*
* Move to next buffer descriptor
*/
if (++rxBdIndex == sc->rxBdCount)
rxBdIndex = 0;
}
}
static void fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
{
struct mcf5329_enet_struct *sc = ifp->if_softc;
volatile mcf5329BufferDescriptor_t *firstTxBd, *txBd;
uint16_t status;
int nAdded;
/*
* Free up buffer descriptors
*/
fec_retire_tx_bd(sc);
/*
* Set up the transmit buffer descriptors.
* No need to pad out short packets since the
* hardware takes care of that automatically.
* No need to copy the packet to a contiguous buffer
* since the hardware is capable of scatter/gather DMA.
*/
nAdded = 0;
firstTxBd = sc->txBdBase + sc->txBdHead;
for (;;) {
/*
* Wait for buffer descriptor to become available
*/
if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
/*
* Clear old events.
*/
MCF_FEC_EIR = MCF_FEC_EIR_TXF;
/*
* Wait for buffer descriptor to become available.
* Check for buffer descriptors before waiting for the event.
* This catches the case when a buffer became available between
* the `if' above, and the clearing of the TXF bit in the EIR.
*/
fec_retire_tx_bd(sc);
while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
rtems_event_set events;
int level;
rtems_interrupt_disable(level);
MCF_FEC_EIMR |= MCF_FEC_EIMR_TXF;
rtems_interrupt_enable(level);
sc->txRawWait++;
rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT, &events);
fec_retire_tx_bd(sc);
}
}
/*
* Don't set the READY flag on the first fragment
* until the whole packet has been readied.
*/
status = nAdded ? MCF_FEC_TxBD_R : 0;
/*
* The IP fragmentation routine in ip_output
* can produce fragments with zero length.
*/
txBd = sc->txBdBase + sc->txBdHead;
if (m->m_len) {
char *p = mtod(m, char *);
/*
* Stupid FEC can't handle misaligned data!
* Given the way that mbuf's are layed out it should be
* safe to shuffle the data down like this.....
* Perhaps this code could be improved with a "Duff's Device".
*/
if ((int) p & 0x3) {
int l = m->m_len;
char *dest = p - ((int) p & 0x3);
uint16_t *o = (uint16_t *) dest, *i = (uint16_t *) p;
while (l > 0) {
*o++ = *i++;
l -= sizeof(uint16_t);
}
p = dest;
sc->txRealign++;
}
txBd->buffer = p;
txBd->length = m->m_len;
rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length);
sc->txMbuf[sc->txBdHead] = m;
nAdded++;
if (++sc->txBdHead == sc->txBdCount) {
status |= MCF_FEC_TxBD_W;
sc->txBdHead = 0;
}
m = m->m_next;
} else {
/*
* Just toss empty mbufs
*/
struct mbuf *n;
MFREE(m, n);
m = n;
}
if (m == NULL) {
if (nAdded) {
txBd->status = status | MCF_FEC_TxBD_R
| MCF_FEC_TxBD_L | MCF_FEC_TxBD_TC;
if (nAdded > 1)
firstTxBd->status |= MCF_FEC_TxBD_R;
MCF_FEC_TDAR = MCF_FEC_TDAR_X_DES_ACTIVE;
sc->txBdActiveCount += nAdded;
}
break;
}
txBd->status = status;
}
}
void fec_txDaemon(void *arg)
{
struct mcf5329_enet_struct *sc = (struct mcf5329_enet_struct *) arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
struct mbuf *m;
rtems_event_set events;
for (;;) {
/*
* Wait for packet
*/
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT, &events);
/*
* Send packets till queue is empty
*/
for (;;) {
/*
* Get the next mbuf chain to transmit.
*/
IF_DEQUEUE(&ifp->if_snd, m);
if (!m)
break;
fec_sendpacket(ifp, m);
}
ifp->if_flags &= ~IFF_OACTIVE;
}
}
/*
* Send packet (caller provides header).
*/
static void mcf5329_enet_start(struct ifnet *ifp)
{
struct mcf5329_enet_struct *sc = ifp->if_softc;
rtems_bsdnet_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT);
ifp->if_flags |= IFF_OACTIVE;
}
static void fec_init(void *arg)
{
struct mcf5329_enet_struct *sc = arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
if (sc->txDaemonTid == 0) {
/*
* Set up hardware
*/
mcf5329_fec_initialize_hardware(sc);
/*
* Start driver tasks
*/
sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc);
sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc);
}
/*
* Set flags appropriately
*/
if (ifp->if_flags & IFF_PROMISC)
MCF_FEC_RCR |= MCF_FEC_RCR_PROM;
else
MCF_FEC_RCR &= ~MCF_FEC_RCR_PROM;
/*
* Tell the world that we're running.
*/
ifp->if_flags |= IFF_RUNNING;
/*
* Enable receiver and transmitter
*/
MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;
}
static void fec_stop(struct mcf5329_enet_struct *sc)
{
struct ifnet *ifp = &sc->arpcom.ac_if;
ifp->if_flags &= ~IFF_RUNNING;
/*
* Shut down receiver and transmitter
*/
MCF_FEC_ECR = 0x0;
}
/*
* Show interface statistics
*/
static void enet_stats(struct mcf5329_enet_struct *sc)
{
printf(" Rx Interrupts:%-10lu", sc->rxInterrupts);
printf("Rx Packet Count:%-10lu", MCF_FEC_RMON_R_PACKETS);
printf(" Rx Broadcast:%-10lu\n", MCF_FEC_RMON_R_BC_PKT);
printf(" Rx Multicast:%-10lu", MCF_FEC_RMON_R_MC_PKT);
printf("CRC/Align error:%-10lu", MCF_FEC_RMON_R_CRC_ALIGN);
printf(" Rx Undersize:%-10lu\n", MCF_FEC_RMON_R_UNDERSIZE);
printf(" Rx Oversize:%-10lu", MCF_FEC_RMON_R_OVERSIZE);
printf(" Rx Fragment:%-10lu", MCF_FEC_RMON_R_FRAG);
printf(" Rx Jabber:%-10lu\n", MCF_FEC_RMON_R_JAB);
printf(" Rx 64:%-10lu", MCF_FEC_RMON_R_P64);
printf(" Rx 65-127:%-10lu", MCF_FEC_RMON_R_P65TO127);
printf(" Rx 128-255:%-10lu\n", MCF_FEC_RMON_R_P128TO255);
printf(" Rx 256-511:%-10lu", MCF_FEC_RMON_R_P256TO511);
printf(" Rx 511-1023:%-10lu", MCF_FEC_RMON_R_512TO1023);
printf(" Rx 1024-2047:%-10lu\n", MCF_FEC_RMON_R_1024TO2047);
printf(" Rx >=2048:%-10lu", MCF_FEC_RMON_R_P_GTE2048);
printf(" Rx Octets:%-10lu", MCF_FEC_RMON_R_OCTETS);
printf(" Rx Dropped:%-10lu\n", MCF_FEC_IEEE_R_DROP);
printf(" Rx frame OK:%-10lu", MCF_FEC_IEEE_R_FRAME_OK);
printf(" Rx CRC error:%-10lu", MCF_FEC_IEEE_R_CRC);
printf(" Rx Align error:%-10lu\n", MCF_FEC_IEEE_R_ALIGN);
printf(" FIFO Overflow:%-10lu", MCF_FEC_IEEE_R_MACERR);
printf("Rx Pause Frames:%-10lu", MCF_FEC_IEEE_R_FDXFC);
printf(" Rx Octets OK:%-10lu\n", MCF_FEC_IEEE_R_OCTETS_OK);
printf(" Tx Interrupts:%-10lu", sc->txInterrupts);
printf("Tx Output Waits:%-10lu", sc->txRawWait);
printf("Tx Realignments:%-10lu\n", sc->txRealign);
printf(" Tx Unaccounted:%-10lu", MCF_FEC_RMON_T_DROP);
printf("Tx Packet Count:%-10lu", MCF_FEC_RMON_T_PACKETS);
printf(" Tx Broadcast:%-10lu\n", MCF_FEC_RMON_T_BC_PKT);
printf(" Tx Multicast:%-10lu", MCF_FEC_RMON_T_MC_PKT);
printf("CRC/Align error:%-10lu", MCF_FEC_RMON_T_CRC_ALIGN);
printf(" Tx Undersize:%-10lu\n", MCF_FEC_RMON_T_UNDERSIZE);
printf(" Tx Oversize:%-10lu", MCF_FEC_RMON_T_OVERSIZE);
printf(" Tx Fragment:%-10lu", MCF_FEC_RMON_T_FRAG);
printf(" Tx Jabber:%-10lu\n", MCF_FEC_RMON_T_JAB);
printf(" Tx Collisions:%-10lu", MCF_FEC_RMON_T_COL);
printf(" Tx 64:%-10lu", MCF_FEC_RMON_T_P64);
printf(" Tx 65-127:%-10lu\n", MCF_FEC_RMON_T_P65TO127);
printf(" Tx 128-255:%-10lu", MCF_FEC_RMON_T_P128TO255);
printf(" Tx 256-511:%-10lu", MCF_FEC_RMON_T_P256TO511);
printf(" Tx 511-1023:%-10lu\n", MCF_FEC_RMON_T_P512TO1023);
printf(" Tx 1024-2047:%-10lu", MCF_FEC_RMON_T_P1024TO2047);
printf(" Tx >=2048:%-10lu", MCF_FEC_RMON_T_P_GTE2048);
printf(" Tx Octets:%-10lu\n", MCF_FEC_RMON_T_OCTETS);
printf(" Tx Dropped:%-10lu", MCF_FEC_IEEE_T_DROP);
printf(" Tx Frame OK:%-10lu", MCF_FEC_IEEE_T_FRAME_OK);
printf(" Tx 1 Collision:%-10lu\n", MCF_FEC_IEEE_T_1COL);
printf("Tx >1 Collision:%-10lu", MCF_FEC_IEEE_T_MCOL);
printf(" Tx Deferred:%-10lu", MCF_FEC_IEEE_T_DEF);
printf(" Late Collision:%-10lu\n", MCF_FEC_IEEE_T_LCOL);
printf(" Excessive Coll:%-10lu", MCF_FEC_IEEE_T_EXCOL);
printf(" FIFO Underrun:%-10lu", MCF_FEC_IEEE_T_MACERR);
printf(" Carrier Error:%-10lu\n", MCF_FEC_IEEE_T_CSERR);
printf(" Tx SQE Error:%-10lu", MCF_FEC_IEEE_T_SQE);
printf("Tx Pause Frames:%-10lu", MCF_FEC_IEEE_T_FDXFC);
printf(" Tx Octets OK:%-10lu\n", MCF_FEC_IEEE_T_OCTETS_OK);
}
static int fec_ioctl(struct ifnet *ifp, ioctl_command_t command, caddr_t data)
{
struct mcf5329_enet_struct *sc = ifp->if_softc;
int error = 0;
switch (command) {
case SIOCGIFADDR:
case SIOCSIFADDR:
ether_ioctl(ifp, command, data);
break;
case SIOCSIFFLAGS:
switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
case IFF_RUNNING:
fec_stop(sc);
break;
case IFF_UP:
fec_init(sc);
break;
case IFF_UP | IFF_RUNNING:
fec_stop(sc);
fec_init(sc);
break;
default:
break;
}
break;
case SIO_RTEMS_SHOW_STATS:
enet_stats(sc);
break;
/*
* FIXME: All sorts of multicast commands need to be added here!
*/
default:
error = EINVAL;
break;
}
return error;
}
int
rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
{
struct mcf5329_enet_struct *sc;
struct ifnet *ifp;
int mtu;
int unitNumber;
char *unitName;
unsigned char *hwaddr;
/*
* Parse driver name
*/
if ((unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName)) < 0)
return 0;
/*
* Is driver free?
*/
if ((unitNumber < 0) || (unitNumber >= NIFACES)) {
printf("mcf5329: bad FEC unit number.\n");
return 0;
}
sc = &enet_driver[unitNumber];
ifp = &sc->arpcom.ac_if;
if (ifp->if_softc != NULL) {
printf("mcf5329: driver already in use.\n");
return 0;
}
/*
* Process options
*/
if (config->hardware_address)
memcpy(sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN);
else
fec_get_mac_address(sc, sc->arpcom.ac_enaddr);
hwaddr = config->hardware_address;
printf("%s%d: mac: %02x:%02x:%02x:%02x:%02x:%02x\n",
unitName, unitNumber,
hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
if (config->mtu)
mtu = config->mtu;
else
mtu = ETHERMTU;
if (config->rbuf_count)
sc->rxBdCount = config->rbuf_count;
else
sc->rxBdCount = RX_BUF_COUNT;
if (config->xbuf_count)
sc->txBdCount = config->xbuf_count;
else
sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
sc->acceptBroadcast = !config->ignore_broadcast;
/*
* Set up network interface values
*/
ifp->if_softc = sc;
ifp->if_unit = unitNumber;
ifp->if_name = unitName;
ifp->if_mtu = mtu;
ifp->if_init = fec_init;
ifp->if_ioctl = fec_ioctl;
ifp->if_start = mcf5329_enet_start;
ifp->if_output = ether_output;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
if (ifp->if_snd.ifq_maxlen == 0)
ifp->if_snd.ifq_maxlen = ifqmaxlen;
/*
* Attach the interface
*/
if_attach(ifp);
ether_ifattach(ifp);
return 1;
};

3098
bsps/m68k/mvme167/net/network.c
View File

File diff suppressed because it is too large Load Diff

369
bsps/m68k/mvme167/net/uti596.h
View File

@@ -1,369 +0,0 @@
/* uti596.h: Contains the defines and structures used by the uti596 driver */
/*
* EII: March 11: Created v. 0.0
*/
#ifndef UTI596_H
#define UTI596_H
#include <rtems/error.h>
#include <rtems/rtems_bsdnet.h>
#include <sys/param.h>
#include <sys/mbuf.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <net/if.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
/* Ethernet statistics */
struct enet_statistics{
int rx_packets; /* total packets received */
int tx_packets; /* total packets transmitted */
int rx_errors; /* bad packets received */
int tx_errors; /* packet transmit problems */
int rx_dropped; /* no space in buffers */
int tx_dropped;
int tx_retries_exceeded; /* excessive retries */
int multicast; /* multicast packets received */
int collisions;
/* detailed rx_errors: */
int rx_length_errors;
int rx_over_errors; /* receiver ring buff overflow */
int rx_crc_errors; /* recved pkt with crc error */
int rx_frame_errors; /* recv'd frame alignment error */
int rx_fifo_errors; /* recv'r fifo overrun */
int rx_missed_errors; /* receiver missed packet */
/* detailed tx_errors */
int tx_aborted_errors;
int tx_carrier_errors;
int tx_fifo_errors;
int tx_heartbeat_errors;
int tx_window_errors;
/* NIC reset errors */
int nic_reset_count; /* The number of times uti596reset() has been called. */
};
#define CMD_EOL 0x8000 /* The last command of the list, stop. */
#define CMD_SUSP 0x4000 /* Suspend after doing cmd. */
#define CMD_INTR 0x2000 /* Interrupt after doing cmd. */
#define CMD_FLEX 0x0008 /* Enable flexible memory model */
#define SCB_STAT_CX 0x8000 /* Cmd completes with 'I' bit set */
#define SCB_STAT_FR 0x4000 /* Frame Received */
#define SCB_STAT_CNA 0x2000 /* Cmd unit Not Active */
#define SCB_STAT_RNR 0x1000 /* Receiver Not Ready */
#define SCB_CUS_SUSPENDED 0x0100
#define SCB_CUS_ACTIVE 0x0200
#define STAT_C 0x8000 /* Set to 1 after execution */
#define STAT_B 0x4000 /* 1 : Cmd being executed, 0 : Cmd done. */
#define STAT_OK 0x2000 /* 1: Command executed ok 0 : Error */
#define STAT_A 0x1000 /* command has been aborted */
#define STAT_S11 0x0800
#define STAT_S10 0x0400
#define STAT_S9 0x0200
#define STAT_S8 0x0100
#define STAT_S7 0x0080
#define STAT_S6 0x0040
#define STAT_S5 0x0020
#define STAT_MAX_COLLS 0x000F
#define RBD_STAT_P 0x4000 /* prefetch */
#define RBD_STAT_F 0x4000 /* used */
#define CUC_START 0x0100
#define CUC_RESUME 0x0200
#define CUC_SUSPEND 0x0300
#define CUC_ABORT 0x0400
#define RX_START 0x0010
#define RX_RESUME 0x0020
#define RX_SUSPEND 0x0030
#define RX_ABORT 0x0040
#define RU_SUSPENDED 0x0010
#define RU_NO_RESOURCES 0x0020
#define RU_READY 0x0040
#define I596_NULL ( ( void * ) 0xffffffff)
#define UTI_596_END_OF_FRAME 0x8000
struct i596_tbd; /* necessary forward declaration */
enum commands {
CmdNOp = 0,
CmdSASetup = 1,
CmdConfigure = 2,
CmdMulticastList = 3,
CmdTx = 4,
CmdTDR = 5,
CmdDump = 6,
CmdDiagnose = 7
};
/*
* 82596 Dump Command Result
*/
typedef volatile struct i596_dump_result {
unsigned char bf;
unsigned char config_bytes[11];
unsigned char reserved1[2];
unsigned char ia_bytes[6];
unsigned short last_tx_status;
unsigned short tx_crc_byte01;
unsigned short tx_crc_byte23;
unsigned short rx_crc_byte01;
unsigned short rx_crc_byte23;
unsigned short rx_temp_mem01;
unsigned short rx_temp_mem23;
unsigned short rx_temp_mem45;
unsigned short last_rx_status;
unsigned short hash_reg01;
unsigned short hash_reg23;
unsigned short hash_reg45;
unsigned short hash_reg67;
unsigned short slot_time_counter;
unsigned short wait_time_counter;
unsigned short rx_frame_length;
unsigned long reserved2;
unsigned long cb_in3;
unsigned long cb_in2;
unsigned long cb_in1;
unsigned long la_cb_addr;
unsigned long rdb_pointer;
unsigned long int_memory;
unsigned long rfd_size;
unsigned long tbd_pointer;
unsigned long base_addr;
unsigned long ru_temp_reg;
unsigned long tcb_count;
unsigned long next_rb_size;
unsigned long next_rb_addr;
unsigned long curr_rb_size;
unsigned long la_rbd_addr;
unsigned long next_rbd_addr;
unsigned long curr_rbd_addr;
unsigned long curr_rb_count;
unsigned long next_fd_addr;
unsigned long curr_fd_add;
unsigned long temp_cu_reg;
unsigned long next_tb_count;
unsigned long buffer_addr;
unsigned long la_tbd_addr;
unsigned long next_tbd_addr;
unsigned long cb_command;
unsigned long next_cb_addr;
unsigned long curr_cb_addr;
unsigned long scb_cmd_word;
unsigned long scb_pointer;
unsigned long cb_stat_word;
unsigned long mm_lfsr;
unsigned char micro_machine_bit_array[28];
unsigned char cu_port[16];
unsigned long mm_alu;
unsigned long reserved3;
unsigned long mm_temp_a_rr;
unsigned long mm_temp_a;
unsigned long tx_dma_b_cnt;
unsigned long mm_input_port_addr_reg;
unsigned long tx_dma_addr;
unsigned long mm_port_reg1;
unsigned long rx_dma_b_cnt;
unsigned long mm_port_reg2;
unsigned long rx_dma_addr;
unsigned long reserved4;
unsigned long bus_t_timers;
unsigned long diu_cntrl_reg;
unsigned long reserved5;
unsigned long sysbus;
unsigned long biu_cntrl_reg;
unsigned long mm_disp_reg;
unsigned long mm_status_reg;
unsigned short dump_status;
} i596_dump_result;
typedef volatile struct i596_selftest {
unsigned long rom_signature;
unsigned long results;
} i596_selftest;
/*
* Action commands
* (big endian, linear mode)
*/
typedef volatile struct i596_cmd {
unsigned short status;
unsigned short command;
volatile struct i596_cmd *next;
} i596_cmd;
typedef volatile struct i596_nop {
i596_cmd cmd;
} i596_nop;
typedef volatile struct i596_set_add {
i596_cmd cmd;
char data[8];
} i596_set_add;
typedef volatile struct i596_configure {
i596_cmd cmd;
char data[16];
} i596_configure;
typedef volatile struct i596_tx {
i596_cmd cmd;
volatile struct i596_tbd *pTbd;
unsigned short count;
unsigned short pad;
char data[6];
unsigned short length;
} i596_tx;
typedef volatile struct i596_tdr {
i596_cmd cmd;
unsigned long data;
} i596_tdr;
typedef volatile struct i596_dump {
i596_cmd cmd;
char *pData;
} i596_dump;
/*
* Transmit buffer descriptor
*/
typedef volatile struct i596_tbd {
unsigned short size;
unsigned short pad;
volatile struct i596_tbd *next;
char *data;
} i596_tbd;
/*
* Receive buffer descriptor
* (flexible memory structure)
*/
typedef volatile struct i596_rbd {
unsigned short count;
unsigned short offset;
volatile struct i596_rbd *next;
char *data;
unsigned short size;
unsigned short pad;
} i596_rbd;
/*
* Receive Frame Descriptor
*/
typedef volatile struct i596_rfd {
unsigned short stat;
unsigned short cmd;
volatile struct i596_rfd *next;
i596_rbd *pRbd;
unsigned short count;
unsigned short size;
char data [1532];
} i596_rfd;
/*
* System Control Block
*/
typedef volatile struct i596_scb {
unsigned short status;
unsigned short command;
unsigned long cmd_pointer;
unsigned long rfd_pointer;
unsigned long crc_err;
unsigned long align_err;
unsigned long resource_err;
unsigned long over_err;
unsigned long rcvdt_err;
unsigned long short_err;
unsigned short t_off;
unsigned short t_on;
i596_cmd *pCmd;
i596_rfd *pRfd;
} i596_scb;
/*
* Intermediate System Configuration Pointer
*/
typedef volatile struct i596_iscp {
uint8_t null1; /* Always zero */
uint8_t busy; /* Busy byte */
unsigned short scb_offset; /* Not used in linear mode */
unsigned long scb_pointer; /* Swapped pointer to scb */
i596_scb *scb; /* Real pointer to scb */
} i596_iscp;
/*
* System Configuration Pointer
*/
typedef volatile struct i596_scp {
unsigned long sysbus; /* Only low 8 bits are used */
unsigned long pad; /* Must be zero */
unsigned long iscp_pointer; /* Swapped pointer to iscp */
i596_iscp *iscp; /* Real pointer to iscp */
} i596_scp;
/*
* Device Dependent Data Structure
*/
typedef volatile struct uti596_softc {
struct arpcom arpcom;
i596_scp *pScp; /* Block aligned on 16 byte boundary */
i596_scp *base_scp; /* Unaligned block. Need for free() */
i596_iscp iscp;
i596_scb scb;
i596_set_add set_add;
i596_configure set_conf;
i596_tdr tdr;
i596_nop nop;
i596_tx *pTxCmd;
i596_tbd *pTbd;
i596_rfd *pBeginRFA;
i596_rfd *pEndRFA;
i596_rfd *pLastUnkRFD;
i596_rbd *pLastUnkRBD;
i596_rfd *pEndSavedQueue;
i596_cmd *pCmdHead;
i596_cmd *pCmdTail; /* unneeded, as chaining not used, but implemented */
rtems_id rxDaemonTid;
rtems_id txDaemonTid;
rtems_id resetDaemonTid;
struct enet_statistics stats;
int started;
unsigned long rxInterrupts;
unsigned long txInterrupts;
volatile int cmdOk;
unsigned short * pCurrent_command_status;
int resetDone;
unsigned long txRawWait;
i596_rfd *pInboundFrameQueue;
short int rxBdCount;
short int txBdCount;
short int countRFD;
short int savedCount;
i596_rfd *pSavedRfdQueue;
rtems_name semaphore_name;
rtems_id semaphore_id;
char zeroes[64];
unsigned long rawsndcnt;
int nic_reset; /* flag for requesting that ISR issue a reset quest */
} uti596_softc_;
#endif /* UTI596_H */

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bsps/m68k/uC5282/net/network.c
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