2009-12-01 Till Straumann <strauman@slac.stanford.edu>

* new-exceptions/cpu.c, new-exceptions/cpu_asm.S,
	new-exceptions/bspsupport/ppc_exc_asm_macros.h,
	new-exceptions/bspsupport/ppc_exc_initialize.c,
	new-exceptions/bspsupport/vectors.h:
	Added AltiVec support (save/restore volatile vregs
	across exceptions).

c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h

@@ -520,6 +520,27 @@ wrap_disable_thread_dispatching_done_\_FLVR:
 
 wrap_change_msr_done_\_FLVR:
 
+#ifdef __ALTIVEC__
+	LA  SCRATCH_REGISTER_0, _CPU_save_altivec_volatile
+	mtctr SCRATCH_REGISTER_0
+	addi r3, FRAME_REGISTER, EXC_VEC_OFFSET
+	bctrl
+	/*
+	 * Establish defaults for vrsave and vscr
+	 */
+	li       SCRATCH_REGISTER_0, 0
+	mtvrsave SCRATCH_REGISTER_0
+	/*
+	 * Use java/c9x mode; clear saturation bit 
+	 */
+	vxor     0, 0, 0
+	mtvscr   0
+	/*
+	 * Reload VECTOR_REGISTER
+	 */
+	lwz	     VECTOR_REGISTER, EXCEPTION_NUMBER_OFFSET(FRAME_REGISTER)
+#endif
+
 	/*
 	 * Call high level exception handler
 	 */
@@ -619,6 +640,13 @@ wrap_handler_done_\_FLVR:
 
 wrap_thread_dispatching_done_\_FLVR:
 
+#ifdef __ALTIVEC__
+	LA  SCRATCH_REGISTER_0, _CPU_load_altivec_volatile
+	mtctr   SCRATCH_REGISTER_0  	
+	addi    r3, FRAME_REGISTER, EXC_VEC_OFFSET	
+	bctrl
+#endif
+
 	/* Restore MSR? */
 	bne	CR_MSR, wrap_restore_msr_\_FLVR
 

c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c

@@ -135,6 +135,11 @@ rtems_status_code ppc_exc_initialize(
   /* Use current MMU / RI settings when running C exception handlers */
   ppc_exc_msr_bits = ppc_machine_state_register() & (MSR_DR | MSR_IR | MSR_RI);
 
+#ifdef __ALTIVEC__
+  /* Need vector unit enabled to save/restore altivec context */
+  ppc_exc_msr_bits |= MSR_VE;
+#endif
+ 
   if (ppc_cpu_is(PPC_e200z6)) {
     ppc_exc_initialize_e200();
   } else if (ppc_cpu_is_bookE() == PPC_BOOKE_STD || ppc_cpu_is_bookE() == PPC_BOOKE_E500) {

c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h

@@ -189,6 +189,22 @@
 #define EXC_XER_OFFSET 156
 #define EXC_LR_OFFSET 160
 
+#define EXC_GENERIC_SIZE 176
+
+#ifdef __ALTIVEC__
+#define EXC_VEC_OFFSET EXC_GENERIC_SIZE
+#ifndef PPC_CACHE_ALIGNMENT
+#error "Missing include file!"
+#endif
+/*   20 volatile registers
+ * + cache-aligned area for vcsr, vrsave
+ * + area for alignment
+ */
+#define EXC_VEC_SIZE   (16*20 + 2*PPC_CACHE_ALIGNMENT)
+#else
+#define EXC_VEC_SIZE   (0)
+#endif
+
 /* Exception stack frame -> BSP_Exception_frame */
 #define FRAME_LINK_SPACE 8
 
@@ -197,7 +213,7 @@
  * As SVR4 ABI requires 16, make it 16 (as some
  * exception may need more registers to be processed...)
  */
-#define EXCEPTION_FRAME_END 176
+#define EXCEPTION_FRAME_END (EXC_GENERIC_SIZE + EXC_VEC_SIZE)
 
 /** @} */