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powerpc: Fix AltiVec context switch

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Update #2751.
This commit is contained in:
Sebastian Huber
2017-03-07 07:50:12 +01:00
parent 696b5b1e4e
commit c6f7639250
1 changed files with 12 additions and 12 deletions
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24
c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup_asm.S
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@@ -76,10 +76,10 @@
.set r5, 5 .set r5, 5
.set r6, 6 .set r6, 6
.set r7, 7 .set r7, 7
.set r9, 9
.set r10, 10 .set r10, 10
.set r11, 11 .set r11, 11
.set r12, 12 /* Do not use r12, since this is used by _CPU_Context_switch() */
.set cr5, 5 .set cr5, 5
@@ -575,7 +575,7 @@ _CPU_save_altivec_volatile:
/* Save CRC -- it is used implicitly by all the LOAD/STORE macros /* Save CRC -- it is used implicitly by all the LOAD/STORE macros
* when testing if we really should do the load/store operation. * when testing if we really should do the load/store operation.
*/ */
mfcr r12 mfcr r9
#endif #endif
PREP_FOR_SAVE r0, r3, r4, r5, r6, r10 PREP_FOR_SAVE r0, r3, r4, r5, r6, r10
@@ -590,7 +590,7 @@ _CPU_save_altivec_volatile:
#ifndef IGNORE_VRSAVE #ifndef IGNORE_VRSAVE
/* Restore CRC */ /* Restore CRC */
mtcr r12 mtcr r9
#endif #endif
blr blr
@@ -603,7 +603,7 @@ _CPU_load_altivec_volatile:
/* Save CRC -- it is used implicitly by all the LOAD/STORE macros /* Save CRC -- it is used implicitly by all the LOAD/STORE macros
* when testing if we really should do the load/store operation. * when testing if we really should do the load/store operation.
*/ */
mfcr r12 mfcr r9
#endif #endif
/* Try to preload 1st line (where vscr and vrsave are stored) */ /* Try to preload 1st line (where vscr and vrsave are stored) */
@@ -619,7 +619,7 @@ _CPU_load_altivec_volatile:
L_V0TOV19 r3, r4, r5, r6, r10, r11 L_V0TOV19 r3, r4, r5, r6, r10, r11
#ifndef IGNORE_VRSAVE #ifndef IGNORE_VRSAVE
mtcr r12 mtcr r9
#endif #endif
blr blr
@@ -649,7 +649,7 @@ _CPU_Context_switch_altivec:
/* Save CRC -- it is used implicitly by all the LOAD/STORE macros /* Save CRC -- it is used implicitly by all the LOAD/STORE macros
* when testing if we really should do the load/store operation. * when testing if we really should do the load/store operation.
*/ */
mfcr r12 mfcr r9
#endif #endif
/* Is 'from' context == NULL ? (then we just do a 'restore') */ /* Is 'from' context == NULL ? (then we just do a 'restore') */
@@ -685,7 +685,7 @@ _CPU_Context_switch_altivec:
L_V20TOV31 r4, r5, r6, r7, r10, r11 L_V20TOV31 r4, r5, r6, r7, r10, r11
#ifndef IGNORE_VRSAVE #ifndef IGNORE_VRSAVE
mtcr r12 mtcr r9
#endif #endif
blr blr
@@ -761,7 +761,7 @@ _CPU_altivec_load_all:
/* Save CRC -- it is used implicitly by all the LOAD/STORE macros /* Save CRC -- it is used implicitly by all the LOAD/STORE macros
* when testing if we really should do the load/store operation. * when testing if we really should do the load/store operation.
*/ */
mfcr r12 mfcr r9
#endif #endif
/* Try to preload 1st line (where vscr and vrsave are stored) */ /* Try to preload 1st line (where vscr and vrsave are stored) */
@@ -777,7 +777,7 @@ _CPU_altivec_load_all:
L_V0TOV31 r3, r4, r5, r6, r10, r11 L_V0TOV31 r3, r4, r5, r6, r10, r11
#ifndef IGNORE_VRSAVE #ifndef IGNORE_VRSAVE
mtcr r12 mtcr r9
#endif #endif
blr blr
@@ -791,7 +791,7 @@ _CPU_altivec_save_all:
/* Save CRC -- it is used implicitly by all the LOAD/STORE macros /* Save CRC -- it is used implicitly by all the LOAD/STORE macros
* when testing if we really should do the load/store operation. * when testing if we really should do the load/store operation.
*/ */
mfcr r12 mfcr r9
#endif #endif
PREP_FOR_SAVE r0, r3, r4, r5, r6, r10 PREP_FOR_SAVE r0, r3, r4, r5, r6, r10
@@ -806,7 +806,7 @@ _CPU_altivec_save_all:
#ifndef IGNORE_VRSAVE #ifndef IGNORE_VRSAVE
/* Restore CRC */ /* Restore CRC */
mtcr r12 mtcr r9
#endif #endif
blr blr