From 4868027727cb94b4520db9cb51d5547f345c50e9 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 15 Jan 2016 13:18:48 +0100 Subject: [PATCH 1/5] doc: Mention Cortex-M7 multilib --- doc/cpu_supplement/arm.t | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/doc/cpu_supplement/arm.t b/doc/cpu_supplement/arm.t index e24ca00ca8..34fb017d22 100644 --- a/doc/cpu_supplement/arm.t +++ b/doc/cpu_supplement/arm.t @@ -73,6 +73,9 @@ with hard-float ABI VFP-D16 support integer division (SDIV/UDIV) @item @code{thumb/armv7-m/fpv4-sp-d16}: ARMv7-M, Thumb-2 instruction set with hardware integer division (SDIV/UDIV) and hard-float ABI FPv4-SP support +@item @code{thumb/cortex-m7/fpv5-d16}: ARMv7M, Thumb-2 instruction set +optimized for Cortex-M7 with hard-float ABI VFP-D16 support and support for the +64-bit floating point unit @item @code{eb/thumb/armv7-r}: ARMv7-R, Big-endian Thumb-2 instruction set @item @code{eb/thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Big-endian Thumb-2 instruction set with hard-float ABI VFP-D16 support @@ -82,15 +85,17 @@ Multilib 1. and 2. support the standard ARM7TDMI and ARM926EJ-S targets. Multilib 3. supports the Cortex-M0 and Cortex-M1 cores. -Multilib 8. supports the Cortex-M3 and Cortex-M4 cores, which have a special -hardware integer division instruction (this is not present in the A and R -profiles). +Multilib 8. supports the Cortex-M3, Cortex-M4 and Cortex-M7 cores, which have a +special hardware integer division instruction (this is not present in the A and +R profiles). Multilib 9. supports the Cortex-M4 cores with a floating point unit. +Multilib 10. supports the Cortex-M7 core with a floating point unit. + Multilib 4. and 5. support the Cortex-A processors. -Multilib 6., 7., 10. and 11. support the Cortex-R processors. Here also +Multilib 6., 7., 11. and 12. support the Cortex-R processors. Here also big-endian variants are available. Use for example the following GCC options From 47a471a7dd5181a432af643abd8f91fafcc3d9d8 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 15 Jan 2016 14:11:03 +0100 Subject: [PATCH 2/5] libblock: Fix ramdisk::free_at_delete_request init Avoid uninitialized ramdisk::free_at_delete_request. The error was visible in sporadic libtests/block01 failures. --- cpukit/libblock/src/ramdisk-init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpukit/libblock/src/ramdisk-init.c b/cpukit/libblock/src/ramdisk-init.c index 45b1329e6d..cc2ad3e0bb 100644 --- a/cpukit/libblock/src/ramdisk-init.c +++ b/cpukit/libblock/src/ramdisk-init.c @@ -36,7 +36,7 @@ ramdisk *ramdisk_allocate( bool trace ) { - struct ramdisk *rd = malloc(sizeof(struct ramdisk)); + struct ramdisk *rd = calloc(1, sizeof(*rd)); if (rd == NULL) { return NULL; From 6da81e25bab847715bb91edd3f6e380ea889bbf4 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 15 Jan 2016 14:13:35 +0100 Subject: [PATCH 3/5] sptests/sp37: Enable interrupts after test case This avoids a test failure on ARMv7-M targets. --- testsuites/sptests/sp37/init.c | 4 ++++ testsuites/sptests/sp37/sp37.scn | 11 ++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/testsuites/sptests/sp37/init.c b/testsuites/sptests/sp37/init.c index 2fbe1172c1..2059030f09 100644 --- a/testsuites/sptests/sp37/init.c +++ b/testsuites/sptests/sp37/init.c @@ -467,6 +467,10 @@ static void test_interrupt_body(void) */ puts( "interrupt is in progress (use body)" ); in_isr = rtems_interrupt_is_in_progress(); + + puts( "interrupt enable (use body)" ); + rtems_interrupt_enable( level ); + if ( in_isr ) { puts( "interrupt reported to be is in progress (body)" ); rtems_test_exit( 0 ); diff --git a/testsuites/sptests/sp37/sp37.scn b/testsuites/sptests/sp37/sp37.scn index adfa9eedd4..e3349fce0d 100644 --- a/testsuites/sptests/sp37/sp37.scn +++ b/testsuites/sptests/sp37/sp37.scn @@ -1,4 +1,4 @@ -*** TEST 37 *** +*** BEGIN OF TEST SP 37 *** clock_tick from task level Blocking task... suspending self clock_tick from task level with preempt -- OK @@ -6,15 +6,16 @@ interrupt is in progress (use body) interrupt disable (use inline) interrupt flash (use inline) interrupt enable (use inline) -interrupt level attribute (use inline) +interrupt level mode (use inline) test case working.. -interrupt is in progress (use body) interrupt disable (use body) interrupt disable (use body) interrupt flash (use body) interrupt enable (use body) -interrupt level attribute (use body) +interrupt level mode (use body) test seems to work +interrupt is in progress (use body) +interrupt enable (use body) isr_in_progress(inline) from ISR -- OK isr_in_progress(body) from ISR -- OK -*** END OF TEST 37 *** +*** END OF TEST SP 37 *** From 32521269dc162764afe995e2684a2dddc8de1196 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 12 Jan 2016 14:36:56 +0100 Subject: [PATCH 4/5] arm: Accept Cortex-M7 multilib --- cpukit/score/cpu/arm/rtems/score/arm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h index 6d1f8502a3..2114f773d4 100644 --- a/cpukit/score/cpu/arm/rtems/score/arm.h +++ b/cpukit/score/cpu/arm/rtems/score/arm.h @@ -29,7 +29,7 @@ extern "C" { */ /**@{**/ -#if defined(__ARM_ARCH_7M__) +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) #define CPU_MODEL_NAME "ARMv7M" #define ARM_MULTILIB_ARCH_V7M #elif defined(__ARM_ARCH_6M__) From 819a6b35cc7ad4b3bc542e738c0933d55a132ccf Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 14 Jan 2016 08:07:06 +0100 Subject: [PATCH 5/5] arm: Honor cache for Cortex-M7 support --- cpukit/score/cpu/arm/armv7m-exception-handler-set.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c index d76dfa88b4..2718f80838 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c +++ b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c @@ -5,10 +5,10 @@ */ /* - * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * Copyright (c) 2011, 2016 Sebastian Huber. All rights reserved. * * embedded brains GmbH - * Obere Lagerstr. 30 + * Dornierstr. 4 * 82178 Puchheim * Germany * @@ -23,6 +23,7 @@ #endif #include +#include #ifdef ARM_MULTILIB_ARCH_V7M @@ -33,6 +34,14 @@ void _ARMV7M_Set_exception_handler( { if ( _ARMV7M_SCB->vtor [index] != handler ) { _ARMV7M_SCB->vtor [index] = handler; + rtems_cache_flush_multiple_data_lines( + &_ARMV7M_SCB->vtor [index], + sizeof(_ARMV7M_SCB->vtor [index]) + ); + rtems_cache_invalidate_multiple_instruction_lines( + &_ARMV7M_SCB->vtor [index], + sizeof(_ARMV7M_SCB->vtor [index]) + ); } }