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Intel i960HA support submitted by Jimen Ching <jimen@adtech-inc.com>

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based on 3.6.0.  It was very lucky that this went in as well as it
did.
This commit is contained in:
Joel Sherrill
1999-04-19 21:02:31 +00:00
parent 338502f1ad
commit c2463d94b3
4 changed files with 154 additions and 12 deletions
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6
c/src/exec/score/cpu/i960/rtems/score/cpu.h
View File

@@ -67,7 +67,7 @@ extern "C" {
#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
#define CPU_STACK_GROWS_UP TRUE
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
#define CPU_STRUCTURE_ALIGNMENT /* __attribute__ ((aligned (16))) */
/*
* Define what is required to specify how the network to host conversion
@@ -169,9 +169,7 @@ typedef struct {
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
i960ca_PRCB *Prcb;
#endif
i960_PRCB *Prcb;
} rtems_cpu_table;
/* variables */

77
c/src/exec/score/cpu/i960/rtems/score/i960.h
View File

@@ -37,6 +37,11 @@ extern "C" {
#define CPU_MODEL_NAME "i960ca"
#define I960_HAS_FPU 0
#elif defined(i960ha)
#define CPU_MODEL_NAME "i960ha"
#define I960_HAS_FPU 0
#else
#error "Unsupported CPU Model"
@@ -94,10 +99,10 @@ typedef struct {
unsigned int mcon14; /* memory region 14 configuration */
unsigned int mcon15; /* memory region 15 configuration */
/* Control Group 6 */
unsigned int reserved; /* reserved */
unsigned int bpcon; /* breakpoint control */
unsigned int tc; /* trace control */
unsigned int bcon; /* bus configuration control */
unsigned int reserved; /* reserved */
} i960ca_control_table;
/* Intel i960CA Processor Control Block */
@@ -117,7 +122,75 @@ typedef struct {
configuration word */
unsigned int reg_cache_cfg; /* register cache configuration word */
} i960ca_PRCB;
typedef i960ca_control_table i960_control_table;
typedef i960ca_PRCB i960_PRCB;
#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
/* i960HA control structures */
/* Intel i960HA Control Table */
typedef struct {
/* Control Group 0 */
unsigned int ipb0; /* IP breakpoint 0 */
unsigned int ipb1; /* IP breakpoint 1 */
unsigned int dab0; /* data address breakpoint 0 */
unsigned int dab1; /* data address breakpoint 1 */
/* Control Group 1 */
unsigned int imap0; /* interrupt map 0 */
unsigned int imap1; /* interrupt map 1 */
unsigned int imap2; /* interrupt map 2 */
unsigned int icon; /* interrupt control */
/* Control Group 2 */
unsigned int mcon0; /* memory region 0 configuration */
unsigned int mcon1; /* memory region 1 configuration */
unsigned int mcon2; /* memory region 2 configuration */
unsigned int mcon3; /* memory region 3 configuration */
/* Control Group 3 */
unsigned int mcon4; /* memory region 4 configuration */
unsigned int mcon5; /* memory region 5 configuration */
unsigned int mcon6; /* memory region 6 configuration */
unsigned int mcon7; /* memory region 7 configuration */
/* Control Group 4 */
unsigned int mcon8; /* memory region 8 configuration */
unsigned int mcon9; /* memory region 9 configuration */
unsigned int mcon10; /* memory region 10 configuration */
unsigned int mcon11; /* memory region 11 configuration */
/* Control Group 5 */
unsigned int mcon12; /* memory region 12 configuration */
unsigned int mcon13; /* memory region 13 configuration */
unsigned int mcon14; /* memory region 14 configuration */
unsigned int mcon15; /* memory region 15 configuration */
/* Control Group 6 */
unsigned int reserved; /* reserved */
unsigned int bpcon; /* breakpoint control */
unsigned int tc; /* trace control */
unsigned int bcon; /* bus configuration control */
} i960ha_control_table;
/* Intel i960HA Processor Control Block */
typedef struct {
unsigned int *fault_tbl; /* fault table base address */
i960ha_control_table
*control_tbl; /* control table base address */
unsigned int initial_ac; /* AC register initial value */
unsigned int fault_config; /* fault configuration word */
void **intr_tbl; /* interrupt table base address */
void *sys_proc_tbl; /* system procedure table
base address */
unsigned int reserved; /* reserved */
unsigned int *intr_stack; /* interrupt stack pointer */
unsigned int ins_cache_cfg; /* instruction cache
configuration word */
unsigned int reg_cache_cfg; /* register cache configuration word */
} i960ha_PRCB;
typedef i960ha_control_table i960_control_table;
typedef i960ha_PRCB i960_PRCB;
#endif
/*

6
cpukit/score/cpu/i960/rtems/score/cpu.h
View File

@@ -67,7 +67,7 @@ extern "C" {
#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
#define CPU_STACK_GROWS_UP TRUE
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
#define CPU_STRUCTURE_ALIGNMENT /* __attribute__ ((aligned (16))) */
/*
* Define what is required to specify how the network to host conversion
@@ -169,9 +169,7 @@ typedef struct {
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
i960ca_PRCB *Prcb;
#endif
i960_PRCB *Prcb;
} rtems_cpu_table;
/* variables */

77
cpukit/score/cpu/i960/rtems/score/i960.h
View File

@@ -37,6 +37,11 @@ extern "C" {
#define CPU_MODEL_NAME "i960ca"
#define I960_HAS_FPU 0
#elif defined(i960ha)
#define CPU_MODEL_NAME "i960ha"
#define I960_HAS_FPU 0
#else
#error "Unsupported CPU Model"
@@ -94,10 +99,10 @@ typedef struct {
unsigned int mcon14; /* memory region 14 configuration */
unsigned int mcon15; /* memory region 15 configuration */
/* Control Group 6 */
unsigned int reserved; /* reserved */
unsigned int bpcon; /* breakpoint control */
unsigned int tc; /* trace control */
unsigned int bcon; /* bus configuration control */
unsigned int reserved; /* reserved */
} i960ca_control_table;
/* Intel i960CA Processor Control Block */
@@ -117,7 +122,75 @@ typedef struct {
configuration word */
unsigned int reg_cache_cfg; /* register cache configuration word */
} i960ca_PRCB;
typedef i960ca_control_table i960_control_table;
typedef i960ca_PRCB i960_PRCB;
#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
/* i960HA control structures */
/* Intel i960HA Control Table */
typedef struct {
/* Control Group 0 */
unsigned int ipb0; /* IP breakpoint 0 */
unsigned int ipb1; /* IP breakpoint 1 */
unsigned int dab0; /* data address breakpoint 0 */
unsigned int dab1; /* data address breakpoint 1 */
/* Control Group 1 */
unsigned int imap0; /* interrupt map 0 */
unsigned int imap1; /* interrupt map 1 */
unsigned int imap2; /* interrupt map 2 */
unsigned int icon; /* interrupt control */
/* Control Group 2 */
unsigned int mcon0; /* memory region 0 configuration */
unsigned int mcon1; /* memory region 1 configuration */
unsigned int mcon2; /* memory region 2 configuration */
unsigned int mcon3; /* memory region 3 configuration */
/* Control Group 3 */
unsigned int mcon4; /* memory region 4 configuration */
unsigned int mcon5; /* memory region 5 configuration */
unsigned int mcon6; /* memory region 6 configuration */
unsigned int mcon7; /* memory region 7 configuration */
/* Control Group 4 */
unsigned int mcon8; /* memory region 8 configuration */
unsigned int mcon9; /* memory region 9 configuration */
unsigned int mcon10; /* memory region 10 configuration */
unsigned int mcon11; /* memory region 11 configuration */
/* Control Group 5 */
unsigned int mcon12; /* memory region 12 configuration */
unsigned int mcon13; /* memory region 13 configuration */
unsigned int mcon14; /* memory region 14 configuration */
unsigned int mcon15; /* memory region 15 configuration */
/* Control Group 6 */
unsigned int reserved; /* reserved */
unsigned int bpcon; /* breakpoint control */
unsigned int tc; /* trace control */
unsigned int bcon; /* bus configuration control */
} i960ha_control_table;
/* Intel i960HA Processor Control Block */
typedef struct {
unsigned int *fault_tbl; /* fault table base address */
i960ha_control_table
*control_tbl; /* control table base address */
unsigned int initial_ac; /* AC register initial value */
unsigned int fault_config; /* fault configuration word */
void **intr_tbl; /* interrupt table base address */
void *sys_proc_tbl; /* system procedure table
base address */
unsigned int reserved; /* reserved */
unsigned int *intr_stack; /* interrupt stack pointer */
unsigned int ins_cache_cfg; /* instruction cache
configuration word */
unsigned int reg_cache_cfg; /* register cache configuration word */
} i960ha_PRCB;
typedef i960ha_control_table i960_control_table;
typedef i960ha_PRCB i960_PRCB;
#endif
/*